Siemens C505 Technical data

Microcomputer Components

8-Bit CMOS Microcontroller

C505
C505C/C505A
C505CA

Data Sheet 12.97

Edition 12.97
Published by Siemens AG,

Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

Siemens AG 1997.

©

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

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will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in­curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

2

with the express

written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

8-Bit CMOS Microcontroller

Advance Information

• Fully compatible to standard 8051 microcontroller

• Superset of the 8051 architecture with 8 datapointers

• Up to 20 MHz operating frequency
– 375 ns instruction cycle time @16 MHz
– 300 ns instruction cycle time @20 MHz (50 % duty cycle)

• On-chip program memory (with optional memory protection)
– C505-2R/C505C-2R : 16k byte on-chip ROM
– C505A-4E/C505CA-4E: 32k byte on-chip OTP
– alternatively up to 64k byte external program memory

• 256 byte on-chip RAM

• On-chip XRAM
– C505/C505C : 256 byte
– C505A/C505CA : 1K byte

• 32 + 2 digital I/O lines
– Four 8-bit digital I/O ports
– One 2-bit digital I/O port (port 4)
– Port 1 with mixed analog/digital I/O capability

C505
C505C
C505A

C505CA

(more features on next page)

Oscillator Watchdog

A / D Converter

C505 / C505C: 8-Bit

C505A / C505CA: 10-Bit

Timer 2

Support Module

On-Chip Emulation

Full-CAN Controller

C505C / C505CA only

Watchdog Timer

Figure 1
C505 Functional Units

XRAM

C505 / C505C: 256 Byte

C505A / C505CA: 1 KByte

Timer

0

Timer

1

C500

Core

8 Datapointers

Program Memory

C505 / C505C: 16 k ROM

C505A / C505CA: 32 k OTP

USART

RAM

256 Byte

8-Bit

Port 0

Port 1
Port 2
Port 3
Port 4

I / O
8 Analog Inputs /

8 Digit. I / O
I / O

I / O
I / O (2-Bit I / O Port)

MCB03628

Semiconductor Group 3 1997-12-01

✓

C505A / C505CA

Features (cont’d):

• Three 16-bit timers/counters
– Timer 0 / 1 (C501 compatible)
– Timer 2 with 4 channels for 16-bit capture/compare operation

• Full duplex serial interface with programmable baudrate generator (USART)

• Full CAN Module, version 2.0 B compliant (C505C and C505CA only)
– 256 register/data bytes located in external data memory area
– 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz
– internal CAN clock prescaler when input frequency is over 10 MHz

• On-chip A/D Converter
– up to 8 analog inputs
– C505/C505C : 8-bit resolution
– C505A/C505CA: 10-bit resolution

• Twelve interrupt sources with four priority levels

• On-chip emulation support logic (Enhanced Hooks Technology

• Programmable 15-bit watchdog timer

• Oscillator watchdog

• Fast power on reset

• Power Saving Modes
– Slow-down mode
– Idle mode (can be combined with slow-down mode)
– Software power-down mode with wake up capability through P3.2/INT0

• P-MQFP-44 package

• Pin configuration is compatible to C501, C504, C511/C513-family

• Temperature ranges:

SAB-C505 versions
SAF-C505 versions
SAH-C505 versions
SAK-C505 versions

= 0 to 70 ° C

T

A

T

= – 40 to 85 ° C

A

T

= – 40 to 110 ° C (max. operating frequency: TBD)

A

T

= – 40 to 125 ° C (max. operating frequency: 12 MHz

A

with 50% duty cycle)

TM

1)

)

or P4.1/RXDC pin

C505 / C505C

Table 1
Differences in Functionality of the C505 MCUs

Device Internal Program Memory XRAM Size A/D Converter

Resolution

8 Bit
8 Bit

8 Bit
8 Bit

C505-2RM
C505-LM

C505C-2RM
C505C-LM

ROM OTP

16 KB
–

16 KB
–

–
–

–
–

256 B
256 B

256 B
256 B

CAN
Controller

–
–

✓
✓

C505A-4EM – 32 KB 1 KB 10 Bit –
C505CA-4EM – 32 KB 1 KB 10 Bit

1)

“Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group 4 1997-12-01

°

°

°

Table 2
Ordering Information

Type Ordering Code Package Description

(8-Bit CMOS microcontroller)

C505 / C505C

C505A / C505CA

SAB-C505-2RM
SAB-C505-LM

SAF-C505-2RM
SAF-C505-LM

SAB-C505C-2RM
SAB-C505C-LM

SAF-C505C-2RM
SAF-C505C-LM

SAB-C505A-4EM Q67127-C2060 P-MQFP-44 with OTP memory (32K), 20 MHz

SAF-C505A-4EM Q67127-C2061 P-MQFP-44
SAB-C505CA-4EM Q67127-C1082 P-MQFP-44 with OTP memory (32K) and CAN, 20 MHz

SAB-C505CA-4EM Q67127-C2058 P-MQFP-44

Q67127-DXXXX
Q67127-C2057

Q67127-DXXXX
Q67127-C2056

Q67127-DXXXX
Q67127-C2029

Q67127-DXXXX
Q67127-C2030

P-MQFP-44
P-MQFP-44

P-MQFP-44
P-MQFP-44

P-MQFP-44
P-MQFP-44

P-MQFP-44
P-MQFP-44

with mask-programmable ROM (16K), 20 MHz
for external memory (20 MHz)

Extended temperature. – 40 ° C to 85 ° C :
with mask-programmable ROM (16K), 20 MHz
for external memory (20 MHz)

with mask-progr. ROM (16K) and CAN, 20 MHz
for external memory, with CAN (20 MHz)

Extended temperature. – 40
with mask-progr. ROM (16K) and CAN, 20 MHz
for external memory, with CAN (20 MHz)

Extended temperature. – 40
with OTP memory (32K), 20 MHz

Extended temperature. – 40
with OTP memory (32K) and CAN, 20 MHz

C to 85 ° C :

C to 85 ° C :

C to 85 ° C :

Note: The ordering number of the ROM types (DXXXX extension) is defined after program release

(verification) of the customer.
Versions for the extended temperature range – 40
125

°

C (SAK-C505) are available on request.

°

C to 110

°

C (SAH-C505) and – 40

°

C to

Semiconductor Group 5 1997-12-01

C505 / C505C

C505A / C505CA

V

AREF

V

AGND

XTAL1
XTAL2

RESET
EA

ALE
PSEN

V

CC

C505
C505C
C505A

C505CA

V

SS

Port

0

8-Bit Digital I / O
Port

1
8-Bit Digital I / O /
8-Bit Analog Inputs

Port

2
8-Bit Digital I / O

Port

3
8-Bit Digital I / O

Port4Port
2-Bit Digital I / O

MCL03629

Figure 2
Logic Symbol

Additional Literature

For further information about the C505/C505C/C505A/C505CA the following literature is available:

Title Ordering Number

C505 8-Bit CMOS Microcontroller User’s Manual B158-H7116-X-X-7600
C500 Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual
C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600

Semiconductor Group 6 1997-12-01

P0.6 / AD6

P0.7 / AD7

P0.5 / AD5

P0.4 / AD4

P4.1 / RXDCP4.0 / TXDC

EA

ALE

P2.6 / A14

PSEN

P2.7 / A15

C505 / C505C

C505A / C505CA

P2.5 / A13

P0.3 / AD3
P0.2 / AD2

P0.1 / AD1

P0.0 / AD0

V

AREF

V

AGND

P1.0 / AN0 / INT3 / CC0

P1.1 / AN1 / INT4 / CC1
P1.2 / AN2 / INT5 / CC2
P1.3 / AN3 / INT6 / CC3

P1.4 / AN4

This pin functionality is not available in the C505 and C505A.

33 31 30 29
34
35
36
37
38
39
40
41
42
43
44

2345 78 109

RESET

P1.7 / AN7 / T2

P1.5 / AN5 / T2EX

P1.6 / AN6 / CLKOUT

282726 25

C505
C505C
C505A

C505CA

P3.1 / TxD

P3.0 / RxD

2332

24

22

20
19
18
17
16
15
14
13
12

1116

P3.4 / T0

P3.5 / / T1

P3.3 / INT1

P3.2 / INT0

21

P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8

V

CC

V

SS

XTAL1
XTAL2
P3.7 / RD
P3.6 / WR

MCP03630

Figure 3
C505 Pin Configuration P-MQFP-44 Package (top view)

Semiconductor Group 7 1997-12-01

Table 3
Pin Definitions and Functions

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

P1.0-P1.7 40-44,1-3

40

41

42

43

44
1

2

3

I/O

Function

Port 1

is an 8-bit quasi-bidirectional port with internal pull-up ar­rangement. Port 1 pins can be used for digital input/output
or as analog inputs of the A/D converter. Port 1 pins that
have 1’s written to them are pulled high by internal pull-up
transistors and in that state can be used as inputs. As in­puts, port 1 pins being externally pulled low will source cur­rent (
pullup transistors. Port 1 pins are assigned to be used as
analog inputs via the register P1ANA.
As secondary digital functions, port 1 contains the interrupt,
timer, clock, capture and compare pins. The output latch
corresponding to a secondary function must be pro­grammed to a one (1) for that function to operate (except for
compare functions). The secondary functions are assigned
to the pins of port 1 as follows:

P1.0 / AN0 / INT3

P1.1 / AN1 / INT4 / CC1 Analog input channel 1/

P1.2 / AN2 / INT5 / CC2 Analog input channel 2 /

P1.3 / AN3 / INT6 / CC3 Analog input channel 3

P1.4 / AN4 Analog input channel 4
P1.5 / AN5 / T2EX Analog input channel 5 / Timer 2

P1.6 / AN6 / CLKOUT Analog input channel 6 /

P1.7 / AN7 / T2 Analog input channel 7 /

Port 1 is used for the low-order address byte during program
verification of the C505-2R and C505C-2R.

, in the DC characteristics) because of the internal

I

IL

/ CC0 Analog input channel 0

interrupt 3 input /
capture/compare channel 0 I/O

interrupt 4 input /
capture/compare channel 1 I/O

interrupt 5 input /
capture/compare channel 2 I/O

interrupt 6 input /
capture/compare channel 4 I/O

external reload / trigger input

system clock output

counter 2 input

*) I = Input

O= Output

Semiconductor Group 8 1997-12-01

Table 3
Pin Definitions and Functions (cont’d)

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

RESET 4 I

P3.0-P3.7 5, 7-13

5

7

8

9

10
11
12

13

I/O

Function

RESET

A high level on this pin for one machine cycle while the
oscillator is running resets the device. An internal diffused
resistor to
external capacitor to

Port 3

is an 8-bit quasi-bidirectional port with internal pull-up
arrangement. Port 3 pins that have 1’s written to them are
pulled high by the internal pull-up transistors and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (
characteristics) because of the internal pullup transistors.
The output latch corresponding to a secondary function
must be programmed to a one (1) for that function to operate
(except for TxD and WR
assigned to the pins of port 3 as follows:
P3.0 / RxD Receiver data input (asynch.) or data

P3.1 / TxD Transmitter data output (asynch.) or

P3.2 / INT0 External interrupt 0 input / timer 0 gate

P3.3 / INT1 External interrupt 1 input / timer 1 gate

P3.4 / T0 Timer 0 counter input
P3.5 / T1 Timer 1 counter input
P3.6 / WR

P3.7 / RD RD control output; enables the external

permits power-on reset using only an

V

SS

.

V

CC

, in the DC

I

IL

). The secondary functions are

input/output (synch.) of serial interface

clock output (synch.) of serial interface

control input

control input

WR control output; latches the data
byte from port 0 into the external data
memory

data memory

*) I = Input

O= Output

Semiconductor Group 9 1997-12-01

Table 3
Pin Definitions and Functions (cont’d)

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

P4.0
P4.1

XTAL2 14 O

XTAL1 15 I

6
28

I/O
I/O

Function

Port 4

is a 2-bit quasi-bidirectional port with internal pull-up
arrangement. Port 4 pins that have 1’s written to them are
pulled high by the internal pull-up transistors and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (
characteristics) because of the internal pullup transistors.
The output latch corresponding to the secondary function
RXDC must be programmed to a one (1) for that function to
operate. The secondary functions are assigned to the two
pins of port 4 as follows (C505C and C505CA only) :
P4.0 / TXDC Transmitter output of CAN controller
P4.1 / RXDC Receiver input of CAN controller

XTAL2

Output of the inverting oscillator amplifier.

XTAL1

Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL1
should be driven, while XTAL2 is left unconnected. To
operate above a frequency of 16 MHz, a duty cycle of the
etxernal clock signal of 50 % should be maintained.
Minimum and maximum high and low times as well as rise/
fall times specified in the AC characteristics must be
observed.

, in the DC

I

IL

*) I = Input

O = Output

Semiconductor Group 10 1997-12-01

Table 3
Pin Definitions and Functions (cont’d)

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

P2.0-P2.7 18-25 I/O

PSEN

26 O The Program Store

Function

Port 2

is a an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1’s written to them are pulled
high by the internal pullup resistors, and in that state can be
used as inputs. As inputs, port 2 pins being externally pulled
low will source current (
because of the internal pullup resistors. Port 2 emits the
high-order address byte during fetches from external
program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). In this
application it uses strong internal pullup transistors when
issuing 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 issues the
contents of the P2 special function register and uses only
the internal pullup resistors.

Enable

output is a control signal that enables the external program
memory to the bus during external fetch operations. It is
activated every three oscillator periods except during
external data memory accesses. Remains high during
internal program execution. This pin should not be driven
during reset operation.

, in the DC characteristics)

I

IL

ALE 27 O The Address Latch Enable

output is used for latching the low-byte of the address into
external memory during normal operation. It is activated
every three oscillator periods except during an external data
memory access. When instructions are executed from
internal ROM or OTP (EA
disabled by bit EALE in SFR SYSCON.
ALE should not be driven during reset operation.

*) I = Input

O= Output

=1) the ALE generation can be

Semiconductor Group 11 1997-12-01

Table 3
Pin Definitions and Functions (cont’d)

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

EA

P0.0-P0.7 37-30 I/O

29 I

Function

External Access Enable

When held at high level, instructions are fetched from the
internal ROM or OTP memory when the PC is less than
4000H (C505 and C505C) or less than 8000H (C505A and
C505CA). When held at low level, the C505 fetches all
instructions from external program memory. EA
be driven during reset operation.
For the C505-L and the C505C-L this pin must be tied low.

Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1’s written to them float, and in that state can be used
as high-impendance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external
program or data memory. In this application it uses strong
internal pullup transistors when issuing 1’s.
Port 0 also outputs the code bytes during program
verification in the C505-2R/C505C-2R. External pullup
resistors are required during program verification.

should not

V

AREF

V

AGND

V

SS

V

CC

*) I = Input

O= Output

38 – Reference voltage for the A/D converter.
39 – Reference ground for the A/D converter.
16 – Ground (0 V)
17 – Power Supply (+ 5 V)

Semiconductor Group 12 1997-12-01

V

CC

V

SS

XTAL1
XTAL2

Oscillator

Watchdog

OSC & Timing

XRAM

1)

256 Byte

1 KByte

RAM

256 Byte

C505 / C505C

C505A / C505CA

ROM OTP

1)

16 K /

32 KByte

RESET
ALE
PSEN
EA

CPU

8 Datapointers

Programmable

Watchdog Timer

Timer 0

Timer 1

Timer 2

USART

Baudrate Generator

Full-CAN

Controller

256 Byte

Reg. / Data

Port 0

Port 1

Port 2

Port 3

Port 4

Port 0
8-Bit Digit. I / O

Port 1
8-Bit Digit. I / O /
8-Bit Analog In

Port 2
8-Bit Digit. I / O

Port 3
8-Bit Digit. I / O

Port 4
2-Bit Digit. I / O

Interrupt Unit

V

AREF

V

AGND

A / D Converter

8- / 10-Bit

1)

Emulation

Support

S & H

C505C / C505CA only.

MUX

Logic

1) C505 / C505C: 256B XRAM / 16KB ROM / 8-Bit ADC
C505A / C505CA: 1KB XRAM / 32KB OTP / 10-Bit ADC

MCB03631

25.11.1997

26.09.1997

-

Figure 4
Block Diagram of the C505/C505C/C505A/C505CA

Semiconductor Group 13 1997-12-01

C505 / C505C

C505A / C505CA

CPU

The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three­byte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns.

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

H

D7

CY AC

H

D6

H

D5

F0

H

D4

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1

RS0

Register Bank Select Control Bits

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F

H

D3

H

D2

H

D1

H

D0

H

PSW

H
H
H
H

OV Overflow Flag

Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

Semiconductor Group 14 1997-12-01

Memory Organization

The C505 CPU manipulates operands in the following four address spaces:

– On-chip program memory : 16 Kbyte ROM (C505-2R/C505C-2R) or

32 Kbyte OTP (C505A-4E/C505CA-4E)
– Totally up to 64 Kbyte internal/external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– Internal XRAM data memory : 256 byte (C505/C505C)

1k byte (C505A/C505CA)

– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C505 versions.

Alternatively

C505 / C505C

C505A / C505CA

FFFF

H

Ext.

4000 /

H

8000

H

3FFF /
7FFF

Int.

(EA = 1)

Ext.

(EA = 0)

0000

"Code Space" "Data Space" "Internal Data Space"

"Data Space" F700 to FFFF :

Device

C505
C505C
C505A

C505CA

HH

CAN Area

F700 F7FF

HH

F700 F7FF

HH

Unused Area

F700 FEFF
F800 FEFF
F700 FBFF
F800 FBFF

Ext.

Data

Memory

H
H

Ext.

Data

Memory

H

XRAM Area

HH
HH
H
H

FF00 FFFF
FF00 FFFF

FC00 FFFF

H

FC00 FFFF

H

FFFF

Internal

XRAM

Unused

Area

Int. CAN

H

See table below
for detailed
Data Memory
partitioning

Contr.

(256 Byte)

F6FF

H

F700

H

Indirect

Addr.

Internal

RAM

0000

H

HH
HH
HH
HH

FF

H

80

H

Internal

RAM

Direct

Addr.

Special

Function

Regs.

7F

H

00

H

MCB03632

FF

80

H

H

Figure 5
C505 Memory Map Memory Map

Semiconductor Group 15 1997-12-01

C505 / C505C

C505A / C505CA

Reset and System Clock

The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting
the RESET pin to VCC via a capacitor. Figure 6 shows the possible reset circuitries.

V

CC

a)

C505

+

C505C
C505A

C505CA

RESET RESET

V

CC

V

CC

c)

C505

+

C505C
C505A

C505CA

RESET

&

b)

C505
C505C
C505A

C505CA

MCS03633

Figure 6
Reset Circuitries

Semiconductor Group 16 1997-12-01

C505 / C505C

C505A / C505CA

Figure 7 shows the recommended oscillator circuits for crystal and external clock operation.

C

XTAL2

C505

2 - 20 MHz

C

C = 20 pF 10 pF for crystal operation

C505C
C505A

C505CA

XTAL1

External
Clock
Signal

Figure 7
Recommended Oscillator Circuitries

V

CC

N.C.

XTAL2

C505
C505C
C505A

C505CA

XTAL1

MCS03634

Semiconductor Group 17 1997-12-01

C505 / C505C

C505A / C505CA

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit
datapointers instead of only one datapointer. The instruction set uses just one of these datapointers
at a time. The selection of the actual datapointer is done in the special function regsiter DPSEL.
Figure 8 illustrates the datapointer addressing mechanism.

Data­pointer

DPTR 0000

.0.1.2

DPTR7

DPTR0

DPH(83 ) DPL(82 )

HH

-----

DPSEL(92 )

DPSEL Selected

.2 .1 .0

0 0 1 DPTR 1
0 1 0 DPTR 2
0 1 1 DPTR 3
1 0 0 DPTR 4
1 0 1 DPTR 5
1 1 0 DPTR 6
1 1 1 DPTR 7

H

Figure 8
External Data Memory Addressing using Multiple Datapointers

External Data Memory

MCD00779

Semiconductor Group 18 1997-12-01

C505 / C505C

C505A / C505CA

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

1)

The Enhanced Hooks Technology
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

TM

, which requires embedded logic in the C500 allows the C500

to Emulation Hardware

SYSCON

PCON
TCON

RESET

EA

ALE

PSEN

RSYSCON

RPCON
RTCON

C500

MCU Interface Circuit

Optional

I/O Ports

Figure 9
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 3 Port 1

Port 0
Port 2

Target System Interface

ICE-System Interface

EH-IC

Enhanced Hooks

RPort 0RPort 2

TEA TALE TPSEN

MCS02647

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the program execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

1)

“Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group 19 1997-12-01

C505 / C505C

C505A / C505CA

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions : the
standard special function register area and the mapped special function register area. Five special
function register of the C505 (PCON1,P1ANA, VR0, VR1, VR2) are located in the mapped special
function register area. For accessing the mapped special function register area, bit RMAP in special
function register SYSCON must be set. All other special function registers are located in the
standard special function register area which is accessed when RMAP is cleared (“0“).

The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data
memory area at addresses F700H to F7FFH..

Special Function Register SYSCON (Address B1H) Reset Value : XX100X01

(C505CA only) Reset Value : XX100001

Bit No. MSB LSB

76543210

B1

H

Bit Function

RMAP Special function register map bit

As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not
cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,
the bit RMAP must be cleared/set respectively by software.

––

The functions of the shaded bits are not described here.

1) This bit is only available in the C505CA.

RMAP = 0 : The access to the non-mapped (standard) special function

RMAP = 1 : The access to the mapped special function register area is

EALE RMAP CMOD

register area is enabled.

enabled.

CSWO

1)

XMAP1

XMAP0

SYSCON

B
B

All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are
bitaddressable.

The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. The
SFRs of the C505 are listed in table 4 and table 5. In table 4 they are organized in groups which
refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C and C505CA
only) are also included in table 4. Table 5 illustrates the contents of the SFRs in numeric order of
their addresses. Table 6 list the CAN-SFRs in numeric order of their addresses. .

Semiconductor Group 20 1997-12-01

C505 / C505C

C505A / C505CA

Table 4
Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B
DPH
DPL
DPSEL
PSW
SP
SYSCON

VR0
VR1

VR2

A/D­Converter

ADCON0
ADCON1
ADDAT
ADST
ADDATH

4)

4)

4)

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer

2)

System Control Register

Version Register 0
Version Register 1

Version Register 2

2)

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Reg. (C505/C505C)
A/D Converter Start Reg. (C505/C505C)
A/D Converter High Byte Data Register
(C505A/C505CA)

ADDATL

A/D Converter Low Byte Data Register
(C505A/C505CA)

P1ANA

Interrupt
System

IEN0
IEN1
IP0
IP1
TCON
T2CON
SCON
IRCON

XRAM XPAGE

2) 4)

Port 1 Analog Input Selection Register

2)

2)

2)

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1

2)

Timer Control Register

2)

Timer 2 Control Register

2)

Serial Channel Control Register
Interrupt Request Control Register

Page Address Register for Extended on-chip
XRAM and CAN Controller

SYSCON

1)

Bit-addressable special function registers

2)

This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3)

“X“ means that the value is undefined and the location is reserved

4)

This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

5)

The content of this SFR varies with the actual step of the C505 (eg. 01H for the first step)

6)

C505 / C505A only

7)

C505C / C505CA only

2)

System Control Register

E0
F0

83
82
92

D0

81
B1

FC
FD
FD
FE

D8

DC
D9
DA
D9

DA

90
A8

B8

A9
B9

88
C8
98
C0

91

B1

H

H

H
H
H

H

H

H

H
H
H

H

H

H

H

H

H

H

H
H

H
H

H

H

H

H

H

H

H

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

00

H

00

H

00

H

00

H

XXXXX000
00

H

07

H

XX100X01
XX100001
C5

H

6)

05

H

7)

85

H

5)

00X00000
01XXX000
00

H

3)

XX

H

00

H

00XXXXXX

FF

H

00

H

00

H

00

H

XX000000
00

H

00X00000
00

H

00

H

00

H

XX100X01
XX100001

B

B

B

B

B

B

B

B

B

3) 7)

B

3)

3) 7)

3)

3) 6)

3)

3)

3)

3) 6)

Semiconductor Group 21 1997-12-01

C505 / C505C

C505A / C505CA

Table 4
Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Ports P0

P1
P1ANA
P2
P3
P4

Serial
Channel

ADCON0
PCON

2)

SBUF
SCON
SRELL
SRELH

Timer 0/
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

Compare/
Capture
Unit /
Timer 2

CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON

2)

IEN0

2)

IEN1

Watchdog WDTREL

2)

IEN0

2)

IEN1

2)

IP0

Pow. Save
Modes

1)

Bit-addressable special function registers

2)

This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3)

“X” means that the value is undefined and the location is reserved

4)

SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

PCON
PCON1

2)

Port 0
Port 1

2) 4)

Port 1 Analog Input Selection Register
Port 2
Port 3
Port 4

2)

A/D Converter Control Register 0
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
Serial Channel Reload Register, low byte
Serial Channel Reload Register, high byte

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Reload Register High Byte
Reload Register Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register
Interrupt Enable Register 0
Interrupt Enable Register 1

Watchdog Timer Reload Register
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0

Power Control Register

4)

Power Control Register 1

80

H

90

H

90

H

A0

H

B0

H

E8H
D8

H

87

H

99

H

98

H

AA

H

BA

H

88

H

8C

H

8D

H

8A

H

8B

H

89

H

C1

H

C3

H

C5

H

C7

H

C2

H

C4

H

C6

H

CB

H

CA

H

CD

H

CC

H

C8

H

A8

H

B8

H

86

H

A8

H

B8

H

A9

H

87

H

88

H

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

FF

H

FF

H

FF

H

FF

H

FF

1)

H

XXXXXX11
00X00000

00

H

3)

XX

H

00

H

D9

H

XXXXXX11
00

H

00

H

00

H

00

H

00

H

00

H

3)

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00X00000
00

H

00

H

00

H

00

H

00

H

00

H

00

H

0XX0XXXX

B

B

B

3)

3)

B

3)

3)

B

Semiconductor Group 22 1997-12-01

C505 / C505C

C505A / C505CA

Table 4
Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

H
H

H
H

H

01

H

3)

XX

H

3)

XX

H

3)

UU

H

0UUUUUUU

3)

UU

H

UUU11111

3)

UU

H

3)

UU

H

3)

UU

H

UUUUU000

3)

UU

H

3)

UU

H

3)

UU

H

UUUUU000

B

B

B

B

CAN
Controller

(C505C/
C505CA
only)

CR
SR
IR
BTR0
BTR1
GMS0
GMS1
UGML0
UGML1
LGML0
LGML1
UMLM0
UMLM1
LMLM0
LMLM1

Control Register
Status Register
Interrupt Register
Bit Timing Register Low
Bit Timing Register High
Global Mask Short Register Low
Global Mask Short Register High
Upper Global Mask Long Register Low
Upper Global Mask Long Register High
Lower Global Mask Long Register Low
Lower Global Mask Long Register High
Upper Mask of Last Message Register Low
Upper Mask of Last Message Register High
Lower Mask of Last Message Register Low
Lower Mask of Last Message Register High

F700
F701
F702
F704
F705
F706
F707
F708
F709
F70A
F70B
F70C
F70D
F70E
F70F

H
H
H
H
H
H
H
H
H

H

Message Object Registers :
MCR0
MCR1
UAR0
UAR1
LAR0
LAR1
MCFG
DB0n
DB1n
DB2n
DB3n
DB4n
DB5n
DB6n
DB7n

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X” means that the value is undefined and the location is reserved. “U“ means that the value is unchanged
by a reset operation. “U“ values are undefined (as “X”) after a power-on reset operation

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

5) The notation “n” (n= 1 to F) in the message object address definition defines the number of the related
message object.

Message Control Register Low
Message Control Register High
Upper Arbitration Register Low
Upper Arbitration Register High
Lower Arbitration Register Low
Lower Arbitration Register High
Message Configuration Register
Message Data Byte 0
Message Data Byte 1
Message Data Byte 2
Message Data Byte 3
Message Data Byte 4
Message Data Byte 5
Message Data Byte 6
Message Data Byte 7

F7n0
F7n1
F7n2
F7n3
F7n4
F7n5
F7n6
F7n7
F7n8
F7n9
F7nA
F7nB
F7nC
F7nD
F7nE

H
H
H
H
H
H
H
H
H
H

H
H

H

H
H

5)

5)

5)

5)

5)

5)

5)

5)

5)

5)

5)

5)

5)

5)

5)

3)

UU

H

3)

UU

H

3)

UU

H

3)

UU

H

3)

UU

H

UUUUU000
UUUUUU00

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

B

B

3)

3)

3)

3)

3)

3)

Semiconductor Group 23 1997-12-01

Table 5
Contents of the SFRs, SFRs in numeric order of their addresses

C505 / C505C

C505A / C505CA

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H
H
H
H

H

1)

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
WDT

.6 .5 .4 .3 .2 .1 .0

80
81
82
83
86

2)

P0 FF

H

SP 07

H

DPL 00

H

DPH 00

H

WDTREL 00

H

Reset

PSEL
87
88
88

89
8A
8B
8C
8D
90

PCON 00

H

2)

TCON 00

H

3)

PCON1 0XX0-

H

TMOD 00

H

TL0 00

H

TL1 00

H

TH0 00

H

TH1 00

H

2)

P1 FF

H

H
H

XXXX

H
H
H
H
H

H

SMOD PDS IDLS SD GF1 GF0 PDE IDLE

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

EWPD – – WS – – – –

B

GATE C/T M1 M0 GATE C/T M1 M0

.7 .6 .5 .4 .3 .2 .1 .0

.7 .6 .5 .4 .3 .2 .1 .0

.7 .6 .5 .4 .3 .2 .1 .0

.7 .6 .5 .4 .3 .2 .1 .0

T2 CLK-

T2EX .4 .3 INT5 INT4 .0

OUT

3)

90
91
92

98
99
A0
A8
A9
AA

1)

2)

3)

P1ANA FF

H

XPAGE 00

H

DPSEL XXXX-

H

H

H

X000

2)

SCON 00

H

SBUF XX

H

2)

P2 FF

H

2)

IEN0 00

H

IP0 00

H

SRELL D9

H

X means that the value is undefined and the location is reserved
Bit-addressable special function registers
SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

H

H

H
H
H

H

EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0
.7 .6 .5 .4 .3 .2 .1 .0
–––––.2.1.0

B

SM0 SM1 SM2 REN TB8 RB8 TI RI
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
EA WDT ET2 ES ET1 EX1 ET0 EX0
OWDS WDTS .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 24 1997-12-01

C505A / C505CA

Table 5
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C505 / C505C

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H
H

H
H

H
H
H
H
H
H

H
H
H
H
H

H

H

1)

RD WR T1 T0 INT1 INT0 TxD RxD
– – EALE RMAP CMOD – XMAP1 XMAP0

B

– – EALE RMAP CMOD CSWO XMAP1 XMAP0

B

EXEN2 SWDT EX6 EX5 EX4 EX3 0 EADC
EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC
– – .5.4.3.2.1.0

B

––––––.1.0

B

EXF2 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC
COCAH3COCAL3COCAH2COCAL2COCAH1COCAL1COCAH0COCAL

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
T2PS I3FR – T2R1 T2R0 T2CM T2I1 T2I0

B

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
CY AC F0 RS1 RS0 OV F1 P
BD CLK – BSY ADM MX2 MX1 MX0

B

.7 .6 .5 .4 .3 .2 .1 .0

Reset

2)

B0
B1

P3 FF

H

SYSCON4)XX10-

H

0X01

B1

SYSCON4)XX10-

H

0001
B8
B8
B9

H
H
H

2)

2)

3)

IEN1
IEN1

00

4)

00

IP1 XX00-

0000
BA

SRELH XXXX-

H

XX11

2)

C0
C1

C2
C3
C4
C5
C6
C7
C8

IRCON 00

H

CCEN 00

H

CCL1 00

H

CCH1 00

H

CCL2 00

H

CCH2 00

H

CCL3 00

H

CCH3 00

H

2)

T2CON 00X0-

H

0000
CA
CB
CC
CD
D0
D8

CRCL 00

H

CRCH 00

H

TL2 00

H

TH2 00

H

2)

PSW 00

H

2)

ADCON0 00X0-

H

0000
D9

1)

2)

3)

4)

ADDAT 3)00

H

X means that the value is undefined and the location is reserved
Bit-addressable special function registers
C505 / C505A only
C505C / C505CA only

0

Semiconductor Group 25 1997-12-01

C505A / C505CA

Table 5
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C505 / C505C

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H

H

H

H
H
H

H

1)

.9 .8 .7 .6 .5 .4 .3 .2

––––––––

B

.1.0––––––

B

ADCL1 ADCL0 – – – MX2 MX1 MX0

B

.7 .6 .5 .4 .3 .2 .1 .0
– – – – – – RXDC TXDC

B

.7 .6 .5 .4 .3 .2 .1 .0
110001ß1
00000101

5) 6)

.7 .6 .5 .4 .3 .2 .1 .0

5) 7)

Reset

D9

DA

ADDATH

H

7)

ADST 6)XXXX-

H

00

XXXX

DA

DC

ADDATL

H

7)

ADCON1 01XX-

H

00XX­XXXX

X000

2)

E0
E8

ACC 00

H

2)

P4 XXXX-

H

XX11

2)

F0
FC
FD
FE

B 00

H

3)4)

VR0 C5

H

3)4)

VR1 05

H

3)4)

VR2 01

H

11

1)

X means that the value is undefined and the location is reserved

2)

Bit-addressable special function registers

3)

SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

4)

These are read-only registers

5)

The content of this SFR varies with the actual of the step C505 (eg. 01H or 11H for the first step)

6)

C505 / C505C only

7)

C505A / C505CA only

Semiconductor Group 26 1997-12-01

Table 6
Contents of the CAN Registers in numeric order of their addresses
(C505C/C505CA only)

C505 / C505C

C505A / C505CA

Addr.

n=1-F

1)

F700
F701
F702
F704
F705

Register Content

H

CR 01

H

SR XX

H

IR XX

H

BTR0 UU

H

BTR1 0UUU.

H

after
Reset

H

H
H

H

UUUU
F706
F707

F708
F709
F70AHLGML0 UU

GMS0 UU

H

GMS1 UUU1.

H

UGML0 UU

H

UGML1 UU

H

H

1111

H
H
H

B

F70BHLGML1 UUUU.

U000

B

F70CHUMLM0 UU
F70DHUMLM1 UU
F70EHLMLM0 UU
F70F

F7n0
F7n1

LMLM1 UUUU.

H

MCR0 UU

H

MCR1 UU

H

H
H
H

U000

H
H

B

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2)

TEST CCE 0 0 EIE SIE IE INIT
BOFF EWRN – RXOK TXOK LEC2 LEC1 LEC0

INTID

SJW BRP

0 TSEG2 TSEG1

B

ID28-21

ID20-18 11111

ID28-21
ID20-13

ID12-5

ID4-0 0 0 0

ID28-21

ID20-18 ID17-13

ID12-5

ID4-0 0 0 0

MSGVAL TXIE RXIE INTPND
RMTPND TXRQ MSGLST

NEWDAT

CPUUPD
F7n2
F7n3
F7n4
F7n5

F7n6

1)

The notation “n“ (n= 1 to F) in the address definition defines the number of the related message object.

2)

“X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged

UAR0 UU

H

UAR1 UU

H

LAR0 UU

H

LAR1 UUUU.

H

MCFG UUUU.

H

by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation

H
H
H

U000

UU00

ID20-18 ID17-13

ID4-0 0 0 0

B

DLC DIR XTD 0 0

B

ID28-21

ID12-5

Semiconductor Group 27 1997-12-01

C505A / C505CA

Table 6
Contents of the CAN Registers in numeric order of their addresses (cont’d)
(C505C/C505CA only)

C505 / C505C

Addr.

n=1-F

1)

F7n7
F7n8
F7n9
F7nAHDB3n XX
F7nBHDB4n XX
F7nCHDB5n XX
F7nDHDB6n XX
F7nEHDB7n XX

1)

The notation “n“ (n= 1 to F) in the address definition defines the number of the related message object.

2)

Register Content

H

after
Reset

DB0n XX

H

DB1n XX

H

DB2n XX

H

H
H
H
H
H
H
H
H

“X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged
by a reset operation. “U” values are undefined (as “X” after a power-on reset operation

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2)

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 28 1997-12-01

C505 / C505C

C505A / C505CA

I/O Ports

The C505 has four 8-bit I/O ports and one 2-bit I/O port. Port 0 is an open-drain bidirectional I/O
port, while ports 1 to 4 are quasi-bidirectional I/O ports with internal pullup resistors. That means,
when configured as inputs, ports 1 to 4 will be pulled high and will source current when externally
pulled low. Port 0 will float when configured as input.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET.

Port 4 is 2-bit I/O port with CAN controller specific alternate functions. The eight analog input lines
are realized as mixed digital/analog inputs. The 8 analog inputs, AN0-AN7, are located at the port 1
pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are
configured as digital inputs. The analog function of a specific port 1 pin is enabled by bits in the SFR
P1ANA. Writing a 0 to a bit position of P1ANA assigns the corresponding pin to operate as analog
input.

Note: P1ANA is a mapped SFR and can be only accessed if bit RMAP in SFR SYSCON is set.

Semiconductor Group 29 1997-12-01

C505 / C505C

C505A / C505CA

Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 7 :
Table 7

Timer/Counter 0 and 1 Operating Modes
Mode Description TMOD Input Clock

M1 M0 internal external (max)

0 8-bit timer/counter with a

00 f

/6x32 f

OSC

OSC

/12x32

divide-by-32 prescaler
1 16-bit timer/counter 1 1
2 8-bit timer/counter with

10

8-bit autoreload
3 Timer/counter 0 used as one

11

/6 f

OSC

OSC

/12

f

8-bit timer/counter and one

8-bit timer

Timer 1 stops

In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is f

OSC

/6.

In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is f

/12. External inputs INT0 and INT1 (P3.2, P3.3) can be

OSC

programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the
input clock logic.

P3.4/T0
P3.5/T1

Gate
(TMOD)

P3.2/INT0
P3.3/INT1

OSC

=1

÷

6

C/T = 0

C/T = 1

Control

TR0
TR1

_

<

1

&

f

/6

OSC

Timer 0/1
Input Clock

MCS03117

Figure 10
Timer/Counter 0 and 1 Input Clock Logic

Semiconductor Group 30 1997-12-01

C505 / C505C

C505A / C505CA

Timer/Counter 2 with Compare/Capture/Reload

The timer 2 of the C505 provides additional compare/capture/reload features. which allow the
selection of the following operating modes:

– Compare : up to 4 PWM signals with 16-bit/300 ns resolution (@ 20 MHz clock)
– Capture : up to 4 high speed capture inputs with 300 ns resolution
– Reload : modulation of timer 2 cycle time

The block diagram in figure 11 shows the general configuration of timer 2 with the additional
compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as
multifunctional port functions at port 1.

P1.5/
T2EX

P1.7/
T2

OSC

Sync.

T2I0
T2I1

Sync.

&

÷6

f

OSC

÷12

T2PS

Bit16 16 Bit 16 Bit 16 Bit

Comparator

Comparator

Comparator

EXEN2

Reload

EXF2

Reload

Timer 2

TH2TL2

Compare

Comparator

Capture

_

<

1

TF2

Input/
Output
Control

Interrupt
Request

P1.0/
INT3/
CC0

P1.1/
INT4/
CC1

P1.2/
INT5/
CC2

P1.2/
INT6/

CCL3/CCH3

CCL2/CCH2

CCL1/CCH1

CRCL/CRCH

CC3

MCB02730

Figure 11
Timer 2 Block Diagram

Semiconductor Group 31 1997-12-01

C505 / C505C

C505A / C505CA

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A
roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR
IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2
operation.

Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency.

Gated Timer Mode : In gated timer function, the external input pin T2 (P1.7) functions as a gate to
the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the
counting procedure. This facilitates pulse width measurements. The external gate signal is sampled
once every machine cycle.

Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1­to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is
sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize
a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled
at least once before it changes, it must be held for at least one full machine cycle.

Reload of Timer 2 : Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer
2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon­ding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been
set.

Semiconductor Group 32 1997-12-01

C505 / C505C

C505A / C505CA

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows : the 16-bit value stored
in a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.

Compare Mode 0
In compare mode 0, upon matching the timer and compare register contents, the output signal

changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0
is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 12 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Compare Register

Circuit

Compare Reg.

16 Bit

Comparator

Bit16

Timer Register

Timer Circuit

Compare
Match

Timer

Overflow

Figure 12
Port Latch in Compare Mode 0

Port Circuit

Internal
Bus

Write to
Latch

S
D

CLK
R

Port

Latch

Read Latch

Q

Q

Read Pin

V

CC

Port

Pin

MCS02661

Semiconductor Group 33 1997-12-01

C505 / C505C

C505A / C505CA

Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the

new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.

In compare mode 1 (see figure 13) the port circuit consists of two separate latches. One latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.

Port Circuit

Compare Register

Circuit

Compare Reg.

Internal

16 Bit

Comparator

16 Bit

Timer Register

Timer Circuit

Compare
Match

Bus

Write to
Latch

Figure 13
Compare Function in Compare Mode 1

D

Shadow

Latch

CLK

Read Latch

Q

D

Port

Latch

Read Pin

Q

QCLK

V

CC

Port

Pin

MCS02662

Timer 2 Capture Modes

Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the
current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this
function.

In mode 0, the external event causing a capture is :

– for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1
– for the CRC register: a positive or negative transition at the corresponding pin, depending

on the status of the bit I3FR in SFR T2CON.

In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture
register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The timer 2
contents will be latched into the appropriate capture register in the cycle following the write
instruction. In this mode no interrupt request will be generated.

Semiconductor Group 34 1997-12-01

C505 / C505C

C505A / C505CA

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 8.

Table 8
USART Operating Modes

Mode

0 0 0 Shift register mode, fixed baud rate

1 0 1 8-bit UART, variable baud rate

2 1 0 9-bit UART, fixed baud rate

3 1 1 9-bit UART, variable baud rate

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a "baud rate clock" (output signal in figure 14 to the serial interface which - there divided
by 16 - results in the actual "baud rate". Further, the abbrevation f
frequency (crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1
or from a decdicated baud rate generator (see figure 14).

SCON Description

SM0 SM1

Serial data enters and exits through R×D; T×D outputs the shift
clock; 8-bit are transmitted/received (LSB first)

10 bits are transmitted (through T×D) or received (at R×D)

11 bits are transmitted (through T×D) or received (at R×D)

Like mode 2

refers to the oscillator

OSC

Semiconductor Group 35 1997-12-01

Timer 1
Overflow

f

OSC

Baud

Rate

Generator

(SRELH

SRELL)

6÷÷

ADCON0.7

(BD)

0
1

Mode 2
Mode 0

Mode 1
Mode 3

SCON.7
SCON.6

(SM0/

SM1)

Only one mode

can be selected

C505 / C505C

C505A / C505CA

PCON.7

2

(SMOD)

0
1

Baud
Rate
Clock

Note: The switch configuration shows the reset state.

MCS02733

Figure 14
Block Diagram of Baud Rate Generation for the Serial Interface

Table 9 below lists the values/formulas for the baud rate calculation of the serial interface with its
dependencies of the control bits BD and SMOD.

Table 9
Serial Interface - Baud Rate Dependencies

Serial Interface
Operating Modes

Mode 0 (Shift Register) – – f
Mode 1 (8-bit UART)

Mode 3 (9-bit UART)

Active Control Bits Baud Rate Calculation

BD SMOD

/ 6

OSC

0 X Controlled by timer 1 overflow :

SMOD

(2

× timer 1 overflow rate) / 32

1 X Controlled by baud rate generator

SMOD

(2

× f

OSC

) /

(32 × baud rate generator overflow rate)

Mode 2 (9-bit UART) – 0

1

f

/ 32

OSC

f

/ 16

OSC

Semiconductor Group 36 1997-12-01

C505 / C505C

C505A / C505CA

CAN Controller (C505C and C505CA only)

The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all
resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the
extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the
CPU of as much overhead as possible when controlling many different message objects (up to 15).
This includes bus arbitration, resending of garbled messages, error handling, interrupt generation,
etc. In order to implement the physical layer, external components have to be connected to the
C505.

The internal bus interface connects the on-chip CAN controller to the internal bus of the
microcontroller. The registers and data locations of the CAN interface are mapped to a specific
256 byte wide address range of the external data memory area (F700H to F7FFH) and can be
accessed using MOVX instructions. Figure 15 shows a block diagram of the on-chip CAN
controller.

TXDC RXDC

Messages

Handlers

BTL-Configuration

TX/RX Shift Register

Intelligent

Memory

Interrupt

Register

CRC

Gen./Check

Messages

Bit

Timing

Logic

Timing

Generator

Clocks

(to all)

Control

Status +

Control

Status

Register

to internal Bus

Bit

Stream

Processor

Error

Management

Logic

MCB02736

Figure 15
CAN Controller Block Diagram

Semiconductor Group 37 1997-12-01

C505 / C505C

C505A / C505CA

The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel
access to the whole data or remote frame for the acceptance match test and the parallel transfer of
the frame to and from the Intelligent Memory.

The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream between
the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and
the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the
processes of reception, arbitration, transmission, and error signalling are performed according to
the CAN protocol. Note that the automatic retransmission of messages which have been corrupted
by noise or other external error conditions on the bus line is handled by the BSP.

The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to
be transmitted after the data bytes and checks the CRC code of incoming messages. This is done
by dividing the data stream by the code generator polynomial.

The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its
counters, the Receive Error Counter and the Transmit Error Counter, are incremented and
decremented by commands from the Bit Stream Processor. According to the values of the error
counters, the CAN controller is set into the states error

active

, error

passive

and busoff.

The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit
timing according to the CAN protocol. The BTL synchronizes on a
transition at
transition, if the CAN controller itself does not transmit a
also provides programmable time segments to compensate for the propagation delay time and for
phase shifts and to define the position of the Sample Point in the bit time. The programming of the
BTL depends on the baudrate and on external physical delay times.

The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of
maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of
control and status bits. After the initial configuration, the Intelligent Memory can handle the
reception and transmission of data without further microcontroller actions.

Start of Frame

(hard synchronization) and on any further

dominant

recessive

recessive

bit (resynchronization). The BTL

to

dominant

to

dominant

busline

busline

Semiconductor Group 38 1997-12-01

C505 / C505C

C505A / C505CA

CAN Controller Software Initialization

The very first step of the initialization is the CAN controller input clock selection. A divide-by-2
prescaler is enabled by default after reset (figure 16). Setting bit CMOD (SYSCON.3) disables the
prescaler. The purpose of the prescaler selection is:

– to ensure that the CAN controller is operable when f
– to achieve the maximum CAN baudrate of 1 Mbaud when f

.

SYSCON.3

(CMOD)

f

OSC

2

1
0

f

is over 10 MHz (bit CMOD =0)

osc

is 8 MHz (bit CMOD=1)

osc

CAN

Full-CAN

Module

Condition: CMOD = 0, when > 10 MHz

f

OSC

Frequency (MHz) CMOD

f

OSC

f

CAN

(SYSCON.3)

8 8 1 000000
8 4 0 000000
16 8 0 000000

Note : The switch configuration shows the reset state of bit CMOD.

Figure 16
CAN Controller Input Clock Selection

BRP

(BTR0.0-5)

B
B
B

MCS03296

CAN

Baudrate

(Mbaud/sec)

1

0.5
1

Semiconductor Group 39 1997-12-01

C505 / C505C

C505A / C505CA

8-Bit A/D Converter (C505 and C505C only)

The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog
input channels. It operates with a successive approximation technique and provides the following
features:

– 8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs
– 8-bit resolution
– Internal start-of-conversion trigger
– Interrupt request generation after each conversion
– Single or continuous conversion mode

The 8-bit ADC uses two clock signals for operation : the conversion clock f
input clock fIN (1/tIN). f

is derived from the C505 system clock f

ADC

which is applied at the XTAL

OSC

pins via the ADC clock prescaler as shown in figure 17. The input clock is equal to f
conversion clock f

is limited to a maximum frequency of 1.25 MHz. Therefore, the ADC clock

ADC

ADC

(=1/t

) and the

ADC

OSC

. The

prescaler must be programmed to a value which assures that the conversion clock does not exceed

1.25 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.

MUX

ADCL0

Conversion Clock

f

ADC

f

OSC

ADCL1

32
16

8

A / D

Converter

MCS03299

Condition:

4

Clock Prescaler

f

ADC max

< 1.25 MHz

Input Clock

f

=

f

IN

OSC

=

CLP

f

IN

1

MCU System Clock
Rate (f

OSC

)

f

IN

[MHz]

Prescaler
Ratio

f

ADC

[MHz]

ADCL1 ADCL0

2 MHz 2 ÷ 4 0.5 0 0
5 MHz 5 ÷ 4 1.25 0 0
6 MHz 6 ÷ 8 0.75 0 1
10 MHz 10 ÷ 8 1.25 0 1
12 MHz 12 ÷ 16 0.75 1 0
16 MHz 16 ÷ 16 1 1 0
20 MHz 20 ÷ 16 1.25 1 0

Figure 17
8-Bit A/D Converter Clock Selection

Semiconductor Group 40 1997-12-01

C505 / C505C

IEN1 (B8 )

H

C505 / C505C

C505A / C505CA

Internal

Bus

Port 1

f

OSC

V

AREF

EXEN2

IRCON (C0 )

P1ANA (90 )

EAN7

ADCON1 (DC )

SWDT

H

TF2EXF2

H

EAN6

H

ADCL1HADCL0

ADCON0 (D8 )

BD

CLK

MUX

Conversion

Clock

Prescaler

EX5EX6

IEX5IEX6

EAN5

EAN4

BSY

S&H

f

f

ADC

IN

Conversion Clock

Input Clock

EX4

IEX4

EAN3

EX3

IEX3

EAN2

MX2

ADM MX2

Single /
Continuous Mode

Converter

A / D

ECAN

SWI

EAN1

MX1

MX1

EADC

IADC

EAN0

MX0

MX0

ADDAT

(D9 )

H

LSB

.1
.2
.3
.4
.5
.6

MSB

ADST
(DA )

H

V

AGND

Start of
conversion

Internal

Bus

Shaded Bit locations are not used in ADC-functions.

Write to ADST

MCB03298

Figure 18
Block Diagram of the 8-Bit A/D Converter

Semiconductor Group 41 1997-12-01

C505 / C505C

C505A / C505CA

10-Bit A/D Converter (C505A and C505CA only)

The C505 includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input
channels. It operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The A/D converter
provides the following features:

– 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs
– 10-bit resolution
– Single or continuous conversion mode
– Internal start-of-conversion trigger capability
– Interrupt request generation after each conversion
– Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors

The 10-bit ADC uses two clock signals for operation : the conversion clock f
input clock fIN (=1/tIN). f
XTAL pins. The input clock fIN is equal to f

is derived from the C505 system clock f

ADC

The conversion f

OSC

OSC

clock is limited to a maximum

ADC

ADC

(=1/t

ADC

) and the

which is applied at the

frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which
assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the
bits ADCL1 and ADCL0 of SFR ADCON1.

MUX

ADCL0

Conversion Clock

Input Clock

f

=

f

IN

OSC

=

Prescaler
Ratio

1

CLP

f

ADC

[MHz]

f

ADC

f

A / D

Converter

IN

MCS03635

ADCL1 ADCL0

f

OSC

Condition:

f

ADC max

MCU System Clock
Rate (f

OSC

)

ADCL1
32

16

8
4

Clock Prescaler

< 2 MHz

f

IN

[MHz]

2 MHz 2 ÷ 4 0.5 0 0
6 MHz 6 ÷ 4 1.5 0 0
8 MHz 8 ÷ 4200
12 MHz 12 ÷ 8 1.5 0 1
16 MHz 16 ÷ 8201
20 MHz 20 ÷ 16 1.25 1 0

Figure 19
10-Bit A/D Converter Clock Selection

Semiconductor Group 42 1997-12-01

IEN1 (B8 )

H

C505 / C505C

C505A / C505CA

Internal

Bus

Port 1

f

OSC

V

AREF

EXEN2

IRCON (C0 )

EXF2

P1ANA (90 )

EAN7

ADCON1 (DC )

SWDT

H

TF2

H

EAN6

H

ADCL1HADCL0

ADCON0 (D8 )

BD

CLK

MUX

Conversion

Clock

Prescaler

EX6

IEX6

EAN5

EX5

IEX5

EAN4

BSY

S&H

Conversion Clock

Input Clock

f

ADC

f

IN

EX4

IEX4

EAN3

EX3

IEX3

EAN2

MX2

ADM MX2

Single /
Continuous Mode

Converter

A / D

ECAN

SWI

EAN1

MX1

MX1

EADC

IADC

EAN0

MX0

MX0

ADDAT

(D9 )

H

.2
.3
.4
.5
.6
.7
.8

MSB

ADST
(DA )

H

LSB

.1

V

AGND

Start of
conversion

Internal

Bus

Shaded Bit locations are not used in ADC-functions.

Write to ADDATL

MCB03636

Figure 20
Block Diagram of the 10-Bit A/D Converter

Semiconductor Group 43 1997-12-01

C505 / C505C

C505A / C505CA

Interrupt System

The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be
generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter). One
interrupt can be generated by the CAN controller (C505C and C505CA only) or by a software setting
and in this case the interrupt vector is the same. Six interrupts may be triggered externally (P3.2/
INT0, P3.3/INT1, P1.0/AN0/INT3/CC0, P1.1/AN1/INT4/CC1, P1.2/AN2/INT5/CC2, P1.3/AN3/INT6/
CC3). Additionally, the P1.5/AN5/T2EX can trigger an interrupt. The wake-up from power-down
mode interrupt has a special functionality which allows to exit from the software power-down mode
by a short low pulse at either pin P3.2/INT0 or the pin P4.1/RXDC.

Figure 21 to 23 give a general overview of the interrupt sources and illustrate the request and the
control flags which are described in the next sections. Table 10 lists all interrupt sources with their
request flags and interrupt vectior addresses.

Table 10
Interrupt Source and Vectors

Interrupt Source Interrupt Vector Address Interrupt Request Flags

External Interrupt 0 0003
Timer 0 Overflow 000B
External Interrupt 1 0013
Timer 1 Overflow 001B
Serial Channel 0023
Timer 2 Overflow / Ext. Reload 002B
A/D Converter 0043
CAN Controller / Software Interrupt 004B
External interrupt 3 0053
External Interrupt 4 005B
External Interrupt 5 0063
External interrupt 6 006B
Wake-up from power-down mode 007B

H

H

H

H

H

H

H

H

H

H

H

H
H

IE0
TF0
IE1
TF1
RI / TI
TF2 / EXF2
IADC
– / SWI
IEX3
IEX4
IEX5
IEX6
–

Semiconductor Group 44 1997-12-01

P3.2 /
INT0

A / D Converter

Timer 0
Overflow

Status

Error

IT0

TCON.0

SWI

IRCON.1

SIE

CR.2

EIE

>1

IE0

TCON.1

IADC

IRCON.0

TF0

TCON.5

>1

IE

CR.1CR.3

EX0

IEN0.0

EADC

IEN1.0

ET0

IEN0.1

ECAN

IEN1.1

0003

0043

000B

004B

H

H

IP1.0 IP0.0

H

H

C505 / C505C

C505A / C505CA

Highest
Priority Level

Lowest
Priority Level

P

o

l
l

i
n
g

S

e
q

u
e
n
c
e

Message
Transmit

TXIE

MCR0.5 / 4

CAN Controller Interrupt Sources

Message

>1

INTPND

MCR0.0 / 1

Receive

RXIE

MCR0.3 / 2

EA

IEN0.7

IP1.1

IP0.1

Bit addressable
Request flag is cleared by hardware

C505C and C505CA Only

MCB03303

Figure 21
Interrupt Structure, Overview Part 1

Note: Each of the 15 CAN controller message objects (C505C and C505CA only), shown in the

shaded area of Figure 21 provides the bits/flags.

Semiconductor Group 45 1997-12-01

P3.3 /
INT1

P1.0 /
AN0 /

INT3 /
CC0

IT1

TCON.2

I3FR

T2CON.6

IE1

TCON.3

IEX3

IRCON.2

EX1

IEN0.2

EX3

IEN1.2

0013

0053

C505 / C505C

C505A / C505CA

Highest
Priority Level

H

Lowest
Priority Level

P

H

IP1.2

IP0.2

o

l
l

i
n
g

Timer 1
Overflow

TF1

TCON.7

P1.1 /
AN1 /
INT4 /
CC1

IEX4

IRCON.3

Bit addressable
Request flag is cleared by hardware

Figure 22
Interrupt Structure, Overview Part 2

ET1

IEN0.3

EX4

IEN1.3

001B

H

005B

H

EA

IEN0.7

S
e
q

u
e
n

c

e

IP0.3IP1.3

MCB03304

Semiconductor Group 46 1997-12-01

USART

P1.2 /
AN2 /
INT5 /
CC2

Timer 2
Overflow

P1.5 /
AN5 /
T2EX

P1.3 /
INT6 /
CC3

RI

SCON.0

TI

SCON.1

EXEN2

IEN1.7

Bit addressable

IRCON.4

TF2

IRCON.6

EXF2

IRCON.7

IRCON.5

>1

IEX5

>1

IEX6

ES

IEN0.4

EX5

IEN1.4

ET2

IEN0.5

EX6

IEN1.5

0023

H

0063

H

002B

H

006B

H

EA

IEN0.7

IP1.4

IP0.4

IP0.5IP1.5

C505 / C505C

C505A / C505CA

Highest
Priority Level

Lowest
Priority Level

P

o

l
l

i
n
g

S
e
q

u
e
n
c
e

Request flag is cleared by hardware

Figure 23
Interrupt Structure, Overview Part 3

MCB03305

Semiconductor Group 47 1997-12-01

C505 / C505C

C505A / C505CA

Fail Save Mechanisms

The C505 offers enhanced fail safe mechanisms, which allow an automatic recovery from software
upset or hardware failure :

– a programmable watchdog timer (WDT), with variable time-out period from 192 µs up to

approx. 412.5 ms at 16 MHz.

– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.

The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of f
upto f

/192. The system clock of the C505 is divided by two prescalers, a divide-by-two and a

OSC

OSC

/12

divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the
watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit.

07

f

/ 6

OSC

2

16

14

WDTL

8

WDT Reset - Request

WDTH

OWDS

IP0 (A9 )

WDTS

H

WDTPSEL

External HW Reset

670

WDTREL (86 )

H

Control Logic

WDT

SWDT

IEN0 (A8 )
IEN1 (B8 )

H
H

MCB03306

Figure 24
Block Diagram of the Programmable Watchdog Timer

The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped
during active mode of the device. If the software fails to refresh the running watchdog timer an
internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the
content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh
sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The
reset cause (external reset or reset caused by the watchdog) can be examined by software (flag
WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and
power down mode of the processor.

Semiconductor Group 48 1997-12-01

C505 / C505C

C505A / C505CA

Oscillator Watchdog

The oscillator watchdog unit serves for three functions:

– Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the
on-chip oscillator has a higher frequency than the RC oscillator), the part, in order to allow the
oscillator to stabilize, executes a final reset phase of typ. 1 ms; then the oscillator watchdog
reset is released and the part starts program execution from address 0000H again.

– Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.

– Control of external wake-up from software power-down mode

When the power-down mode is left by a low level at the P3.2/INT0 pin or the P4.1/RXDC pin,
the oscillator watchdog unit assures that the microcontroller resumes operation (execution of
the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the
RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when
power-down mode is released. When the on-chip oscillator has a higher frequency than the
RC oscillator, the microcontroller starts program execution by processing a power down
interrupt after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.

Semiconductor Group 49 1997-12-01

C505 / C505C

C505A / C505CA

EWPD

P4.1 / RXDC
P3.2 / INT0

XTAL1
XTAL2

WS
(PCON1.4)(PCON1.7)

Control

Logic

RC

Oscillator

On-Chip

Oscillator

Start /
Stop

f

RC

3 MHz

Start /
Stop

Power - Down

Mode Activated

f

10

1

Comparator

f

2

OWDS

Frequency

Power-Down Mode
Wake - Up Interrupt

Control

Logic

<

f

f

2

1

Delay

Internal Reset

>1

IP0 (A9 )

H

Int. Clock

Figure 25
Functional Block Diagram of the Oscillator Watchdog

MCB03308

Semiconductor Group 50 1997-12-01

C505 / C505C

C505A / C505CA

Power Saving Modes

The C505 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate
in normal operating mode and it can be also used for further power reduction in idle mode.

– Idle mode

In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from
the clock signal. All peripheral units are further provided with the clock. The CPU status is
preserved in its entirety. The idle mode can be terminated by any enabled interrupt of a
peripheral unit or by a hardware reset.

– Power down mode

The operation of the C505 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. Power down
mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/
INT0.or P4.1/RXDC.

– Slow down mode

The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption.

In the power down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that V
is restored to its normal operating level, before the power down mode is terminated. Table 11 gives
a general overview of the entry and exit procedures of the power saving modes.

Table 11
Power Saving Modes Overview

Mode Entering

(Instruction
Example)

Idle Mode ORL PCON, #01H

ORL PCON, #20H

Power Down Mode ORL PCON, #02H

ORL PCON, #40H

Leaving by Remarks

Ocurrence of an
interrupt from a
peripheral unit

Hardware Reset

Hardware Reset Oscillator is stopped;
Short low pulse at

pin P3.2/INT0
P4.1/RXDC

or

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

contents of on-chip RAM and
SFR’s are maintained;

CC

Slow Down Mode ORL PCON,#10H ANL PCON,#0EFH

or
Hardware Reset

Semiconductor Group 51 1997-12-01

Oscillator frequency is
reduced to 1/32 of its nominal
frequency

C505 / C505C

C505A / C505CA

OTP Memory Operation (C505A and C505CA only)

The C505A/C505CA contains a 32k byte one-time programmable (OTP) program memory. With the
C505A/C505CA fast programming cycles are achieved (1 byte in 100 µsec). Also several levels of
OTP memory protection can be selected.

For programming of the device, the C505A/C505CA must be put into the programming mode. This
typically is done not in-system but in a special programming hardware. In the programming mode
the C505A/C505CA operates as a slave device similar as an EPROM standalone memory device
and must be controlled with address/data information, control lines, and an external 11.5V
programming voltage. Figure 26 shows the pins of the C505A/C505CA which are required for
controlling of the OTP programming mode.

A0 - A7 /
A8 - A14

PALE

PMSEL0
PMSEL1

XTAL1
XTAL2

Figure 26
Programming Mode Configuration

V

CC

Port 2 Port 0

V

SS

C505A

C505CA

D0 - D7

EA /

V

PP

PROG
PRD

RESET
PSEN
PSEL

MCS03637

Semiconductor Group 52 1997-12-01

Pin Configuration in Programming Mode

D6

D7

D5

D4

PP

V

EA /

N.C.

PSEN

PROG

A6 / A14

A7

C505 / C505C

C505A / C505CA

A5 / A13

282726 25

C505A

C505CA

N.C.

RESET

PMSEL0

24

PRD

PSEL

PMSEL1

2332

22

21

20

19
18
17
16

15
14
13

12

1116

N.C.

PALE

A4 / A12
A3 / A11
A2 / A10
A1 / A9
A0 / A8

V

CC

V

SS

XTAL1
XTAL2
N.C.
N.C.

MCP03638

D3
D2

D1

D0
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.

33 31 30 29
34
35
36
37
38
39
40
41
42
43
44

2345 78 109

N.C.

N.C.

N.C.

Figure 27
P-MQFP-44 Pin Configuration of the C505A/C505CA in Programming Mode (Top View)

Semiconductor Group 53 1997-12-01

C505 / C505C

C505A / C505CA

The following table 12 contains the functional description of all C505A/C505CA pins which are
required for OTP memory programming.

Table 12
Pin Definitions and Functions in Programming Mode

Symbol Pin Number I/O*)Function

RESET 4 I Reset

This input must be at static “1“ (active) level during the whole
programming mode.

PMSEL0
PMSEL157

I
I

Programming mode selection pins

These pins are used to select the different access modes in
programming mode. PMSEL1,0 must satisfy a setup time to the
rising edge of PALE. When the logic level of PMSEL1,0 is
changed, PALE must be at low level.

PMSEL1 PMSEL0 Access Mode

0 0 Reserved
0 1 Read version bytes
1 0 Program/read lock bits
1 1 Program/read OTP memory byte

PSEL 8IBasic programming mode select

This input is used for the basic programming mode selection
and must be switched according figure 3-1.

PRD 9IProgramming mode read strobe

This input is used for read access control for OTP memory
read, Version Register read, and lock bit read operations.

PALE 10 I Programming address latch enable

PALE is used to latch the high address lines. The high address
lines must satisfy a setup and hold time to/from the falling edge
of PALE. PALE must be at low level when the logic level of
PMSEL1,0 is changed.

XTAL2 14 O XTAL2

Output of the inverting oscillator amplifier.

XTAL1 15 I XTAL1

Input to the oscillator amplifier.

V

SS

16 – Circuit ground potential

must be applied in programming mode.

V

CC

17 – Power supply terminal

must be applied in programming mode.

*) I = Input

O= Output

Semiconductor Group 54 1997-12-01

Table 12
Pin Definitions and Functions in Programming Mode (cont’d)

Symbol Pin Number I/O*)Function

P2.0-7 18-25 I Address lines

P2.0-7 are used as multiplexed address input lines A0-A7 and
A8-A14. A8-A14 must be latched with PALE.

PSEN 26 I Program store enable

This input must be at static “0“ level during the whole
programming mode.

PROG 27 I Programming mode write strobe

This input is used in programming mode as a write strobe for
OTP memory program, and lock bit write operations During
basic programming mode selection a low level must be applied
to PROG.

C505 / C505C

C505A / C505CA

EA/V

PP

D7-0 30-37 I/O Data lines 0-7

N.C. 1-3, 6, 11-13,

*) I = Input

O= Output

29 – External Access / Programming voltage

This pin must be at 11.5V (VPP) voltage level during
programming of an OTP memory byte or lock bit. During an
OTP memory read operation this pin must be at VIH high level.
This pin is also used for basic programming mode selection. At
basic programming mode selection a low level must be applied
to EA/VPP.

During programming mode, data bytes are transferred via the
bidirectional port 0 data lines.

– Not Connected

28, 38-44

These pins should not be connected in programming mode.

Semiconductor Group 55 1997-12-01

Basic Programming Mode Selection
The basic programming mode selection scheme is shown in figure 28.

C505 / C505C

C505A / C505CA

V

CC

Clock
(XTAL1 / XTAL2)

RESET

PSEN

PMSEL1,0

PROG

PRD

PSEL

PALE

5 V

Stable

"1"

"0"

0,1

"0"

"1"

"0"

V

EA /

PP

During this period signals
are not actively driven

Figure 28
Basic Programming Mode Selection

0 V

V

PP

V

IH

Ready for access
mode selection

MCS03639

Semiconductor Group 56 1997-12-01

Table 13
Access Modes Selection

C505 / C505C

C505A / C505CA

Access Mode

V

Program OTP memory byte V
Read OTP memory byte V
Program OTP lock bits V
Read OTP lock bits V
Read OTP version byte V

EA/

PROG PRD

PP

PP

IH

PP

IH
IH

H

H
H L H Byte addr.

H H H A0-7

H H L – D1,D0 see

PMSEL Address

10

(Port 2)

A8-14

Data

(Port 0)

D0-7

table 14

D0-7

of version

byte

Lock Bits Programming / Read

The C505A/C505CA has two programmable lock bits which, when programmed according table 14,
provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can
also be read.

Table 14
Lock Bit Protection Types

Lock Bits at D1,D0 Protection

D1 D0

Level

Protection Type

1 1 Level 0 The OTP lock feature is disabled. During normal operation of

the C505A/C505CA, the state of the EA pin is not latched on
reset.

1 0 Level 1 During normal operation of the C505A/C505CA, MOVC

instructions executed from external program memory are
disabled from fetching code bytes from internal memory. EA is
sampled and latched on reset. An OTP memory read operation
is only possible using the ROM/OTP verification mode 2 for
protection level 1. Further programming of the OTP memory is
disabled (reprogramming security).

0 1 Level 2 Same as level 1, but also OTP memory read operation using

OTP verification mode is disabled.

0 0 Level 3 Same as level 2; but additionally external code execution by

setting EA

=low during normal operation of the C505A/C505CA
is no more possible.
External code execution, which is initiated by an internal
program (e.g. by an internal jump instruction above the ROM
boundary), is still possible.

Semiconductor Group 57 1997-12-01

C505 / C505C

C505A / C505CA

Absolute Maximum Ratings

Ambient temperature under bias (TA) ......................................................... – 40 °C to 125 °C

Storage temperature (T

Voltage on VCC pins with respect to ground (VSS) ....................................... – 0.5 V to 6.5 V

Voltage on any pin with respect to ground (VSS)......................................... – 0.5 V to VCC +0.5 V

Input current on any pin during overload condition..................................... – 10 mA to 10 mA

Absolute sum of all input currents during overload condition ..................... I 100 mA I

Power dissipation........................................................................................ TBD

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (
Voltage on

V

absolute maximum ratings.

) .......................................................................... – 65 °C to 150 °C

stg

V

>

V

IN

pins with respect to ground (

CC

V

) must not exceed the values defined by the

SS

CC

or

V

<

V

SS

) the

IN

Semiconductor Group 58 1997-12-01

C505 / C505C

C505A / C505CA

DC Characteristics

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB- versions

CC

T

= – 40 to 85 °C for the SAF- versions

A

T

= – 40 to 110 °C for the SAH- versions

A

T

= – 40 to 125 °C for the SAK- versions

A

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltages
all except EA, RESET
EA pin
RESET pin

Input high voltages
all except XTAL1, RESET
XTAL1 pin
RESET pin

Output low voltages
Ports 1, 2, 3, 4
Port 0, ALE, PSEN

Output high voltages
Ports 1, 2, 3, 4

Port 0 in external bus mode,
ALE, PSEN

Logic 0 input current
Ports 1, 2, 3, 4 I

Logical 0-to-1 transition current
Ports 1, 2, 3, 4

V

IL

V

IL1

V

IL2

V

IH

V

IH1

V

IH2

V

OL

V

OL1

V

OH

V

OH2

IL

I

TL

– 0.5
– 0.5
– 0.5

0.2 VCC + 0.9

0.7 V

CC

0.6 V

CC

–
–

2.4

0.9 V

CC

2.4

0.9 V

CC

0.2 VCC - 0.1

0.2 VCC - 0.3

0.2 VCC + 0.1

V

+ 0.5

CC

V

+ 0.5

CC

V

+ 0.5

CC

0.45

0.45

–
–
–
–

V
V
V

V
V
V

V
V

V
V
V
V

–
–
–

–
–
–

I

= 1.6 mA

OL

I

= 3.2 mA

OL

I

= – 80 µA

OH

I

= – 10 µA

OH

I

= – 800 µA

OH

I

= – 80 µA

OH

– 10 – 70 µA VIN = 0.45 V
– 65 – 650 µA VIN = 2 V

1)

1)

)

2)

Input leakage current
Port 0, AN0-7 (Port 1), EA

Pin capacitance C

Overload current I
Programming voltage V

Supply current at EA/V

CC

I

LI

IO

OV

PP

– ± 1 µA 0.45 < VIN < V
–10pFfc 1 MHz,

T

= 25 °C

A

– ± 5mA

10.9 12.1
30

V

mA

3) 4)

11.5 V ± 5%

5) 6)

5)

CC

Notes see next but one page 61

Semiconductor Group 59 1997-12-01

Power Supply Currents

Parameter Symbol Limit Values Unit Test Condition

C505 /

Active Mode 12 MHz

C505C

Idle Mode 12 MHz

Active Mode with
slow-down enabled

Idle Mode with
slow-down enabled

Power down current I

C505A

Active Mode 12 MHz

C505CA

Idle Mode 12 MHz

Active Mode with
slow-down enabled

Idle Mode with
slow-down enabled

Power down current I

20 MHz

20 MHz

12 MHz

20 MHz

12 MHz

20 MHz

20 MHz

20 MHz

12 MHz

20 MHz

12 MHz

20 MHz

C505 / C505C

C505A / C505CA

12)

typ.

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

PD

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

PD

19.7
32

11.7

17.8

4.4

4.9

3.6

4.0
7 TBD µA VCC = 2..5.5 V

18.2

28.8

9.4

14.1

3.5

4.2

3.0

3.4
40 TBD µA VCC = 2..5.5 V

max.

TBD
TBD

TBD
TBD

TBD
TBD

TBD
TBD

TBD
TBD

TBD
TBD

TBD
TBD

TBD
TBD

13)

mA

mA

mA

mA

mA

mA

mA

mA

7)

8)

9)

10)

11)

7)

8)

9)

10)

11)

Notes see next page 61

Semiconductor Group 60 1997-12-01

C505 / C505C

C505A / C505CA

Notes:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the

V

0.9

specification when the address lines are stabilizing.

CC

V

on ALE and PSEN to momentarily fall below the

OH

3) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin

V

exceeds the specified range (i.e.

> VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must

OV

remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

4) Not 100% tested, guaranteed by design characterization.

5) Only valid for C505A and C505CA.

6) Only valid for C505A and C505CA in programming mode.

I

(active mode) is measured with:

7)

CC

XTAL1 driven with

= Port 0 = RESET = VCC ; all other pins are disconnected.

EA

t

, tF = 5 ns, 50% duty cycle , VIL = VSS + 0.5 V, VIH =

R

V

– 0.5 V; XTAL2 = N.C.;

CC

8) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled;

t

XTAL1 driven with
RESET = EA

= VSS ; Port0 = VCC ; all other pins are disconnected;

, tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;

R

9) ICC (active mode with slow-down mode) is measured : TBD

10) ICC (idle mode with slow-down mode) is measured : TBD

11) IPD (power-down mode) is measured under following conditions:

= Port 0 = VCC ; RESET =VSS ; XTAL2 = N.C.; XTAL1 = VSS ; V

EA

AGND

= VSS ; V

AREF

= VCC ;

all other pins are disconnected.

12) The typical

values are periodically measured at T

CC

= + 25 °C but not 100% tested.

A

I

13) The maximum ICC values are measured under worst case conditions (T

= 0 °C or – 40 °C and V

A

= 5.5 V)

CC

Semiconductor Group 61 1997-12-01

C505 / C505C

C505A / C505CA

30

mA

Ι

Ι

CC

25

CC max

Ι

CC typ

20

15

10

5

0

0

4 8 12 18

Figure 29
ICC Diagram of C505 and C505C

TBD

MCD03640

MHz 20

f

OSC

C505/C505C: Power Supply Current Calculation Formulas
Parameter Symbol Formula

Active mode I

Idle mode I

Active mode with
slow-down enabled

Idle mode with
slow-down enabled

Note:

f

is the oscillator frequency in MHz.

osc

CC typ

I

CC max

CC typ

I

CC max

I

CC typ

I

CC max

I

CC typ

I

CC max

TBD
TBD

TBD
TBD

TBD
TBD

TBD
TBD

I

values are given in mA.

CC

Semiconductor Group 62 1997-12-01

C505 / C505C

C505A / C505CA

30

MCD03641

mA

Ι

Ι

CC

25

CC max

Ι

CC typ

20

TBD

15

10

5

0

0

4 8 12 18

MHz 20

f

OSC

Figure 30
ICC Diagram of C505A and C505CA

C505A : Power Supply Current Calculation Formulas
Parameter Symbol Formula

Active mode I

Idle mode I

Active mode with
slow-down enabled

Idle mode with
slow-down enabled

Note:

f

is the oscillator frequency in MHz.

osc

CC typ

I

CC max

CC typ

I

CC max

I

CC typ

I

CC max

I

CC typ

I

CC max

TBD
TBD

TBD
TBD

TBD
TBD

TBD
TBD

I

values are given in mA.

CC

Semiconductor Group 63 1997-12-01

A/D Converter Characteristics of C505 and C505C

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB- versions

CC

T

= – 40 to 85 °C for the SAF- versions

A

T

= – 40 to 110 °C for the SAH- versions

A

T

= – 40 to 125 °C for the SAK- versions

A

C505 / C505C

C505A / C505CA

4 V ≤ V

≤ VCC + 0.1 V; V

AREF

– 0.1 V ≤ V

SS

≤ VSS + 0.2 V

AGND

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog input voltage V

Sample time t

Conversion cycle time t

Total unadjusted error T

Internal resistance of

R

reference voltage source
Internal resistance of

R

analog source
ADC input capacitance C

AIN

S

ADCC

UE

AREF

ASRC

AIN

V

-

V

+

AGND

0.2

AREF

0.2

– 64 × t

32 × t
16 × t
8 × t

– 320 × t

160 × t

V

ns Prescaler ÷ 32

IN
IN
IN
IN

ns Prescaler ÷ 32

IN
IN

80 × tIN

40 × t

– ± 2 LSB VSS + 0.5 V ≤ V

– t

ADC

- 1

– tS / 500

- 1

–50pF

IN

/ 500

kΩ

kΩ

1)

Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4

Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4

4)

t

in [ns]

ADC

t

in [ns]

S

6)

5) 6)

2) 6)

2)

3)

≤ VCC – 0.5 V

AIN

Notes see next page.

Clock calculation table:
Clock Prescaler

ADCL1, 0 t

tS t

ADC

ADCC

Ratio

÷ 32 1 1 32 ×

t

64 × tIN 320 × tIN

IN

÷ 16 1 0 16 × tIN 32 × tIN 160 × tIN
÷ 8 0 1 8 × tIN 16 × tIN 80 × tIN
÷ 4 0 0 4 × tIN 8 × tIN 40 × tIN

Further timing conditions :

t

min = 800 ns

ADC

t

= 1 / f

IN

OSC

= t

CLP

Semiconductor Group 64 1997-12-01

C505 / C505C

C505A / C505CA

Notes:

V

1)

2) During the sample time the input capacitance C

3) This parameter includes the sample time

4) TUE (max.) is tested at – 40 ≤ TA ≤ 125 °C; VCC ≤ 5.5 V; V

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

may exeed V

AIN

these cases will be 00

internal resistance of the analog source must allow the capacitance to reach their final voltage level within
After the end of the sample time
result.

conversion clock

guaranteed by design characterization for all other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

t

ADC

or V

AGND

or FFH, respectively.

H

depend on programming and can be taken from the table on the previous page.

up to the absolute maximum ratings. However, the conversion result in

AREF

must be charged/discharged by the external source. The

AIN

t

, changes of the analog input voltage have no effect on the conversion

S

t

, the time for determining the digital result. Values for the

S

≤ VCC + 0.1 V and VSS ≤ V

AREF

AGND

t

. It is

S

.

6) Not 100% tested, but guaranteed by design characterization.

Semiconductor Group 65 1997-12-01

A/D Converter Characteristics of C505A and C505CA

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB- versions

CC

T

= – 40 to 85 °C for the SAF- versions

A

T

= – 40 to 110 °C for the SAH- versions

A

T

= – 40 to 125 °C for the SAK- versions

A

C505 / C505C

C505A / C505CA

4 V ≤ V

≤ VCC + 0.1 V; V

AREF

– 0.1 V ≤ V

SS

≤ VSS + 0.2 V

AGND

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog input voltage V
Sample time t

Conversion cycle time t

Total unadjusted error T

Internal resistance of

R

reference voltage source
Internal resistance of

R

analog source
ADC input capacitance C

AIN

S

ADCC

UE

AREF

ASRC

AIN

V

AGND

– 64 × t

– 384 × t

V

AREF

32 × t
16 × t
8 × t

192 × t

V
ns Prescaler ÷ 32

IN
IN
IN
IN

ns Prescaler ÷ 32

IN
IN

96 × tIN

48 × t

– ± 2 LSB VSS + 0.5 V ≤ V

– ± 4 LSB VSS < V

– t

ADC

- 0.25

– tS / 500

- 0.25

–50pF

IN

/ 250

kΩ

kΩ

1)

Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4

Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4

4)

< VCC + 0.5 V

t

t

6)

V

ADC

S

AIN

- 0.5 V < V

CC

in [ns]

in [ns]

5) 6)

2) 6)

2)

3)

≤ VCC-0.5 V

AIN

< VCC

AIN

4)

Notes see next page.

Clock calculation table:
Clock Prescaler

ADCL1, 0 t

tS t

ADC

ADCC

Ratio

÷ 32 1 1 32 × tIN 64 × tIN 384 × tIN
÷ 16 1 0 16 × tIN 32 × tIN 192 × tIN
÷ 8 0 1 8 x tIN 16 × tIN 96 × tIN
÷ 4 0 0 4 x tIN 8 × tIN 48 × tIN

Further timing conditions :

t

min = 500 ns

ADC

t

= 1 / f

IN

OSC

= t

CLP

Semiconductor Group 66 1997-12-01

C505 / C505C

C505A / C505CA

Notes:

V

1)

2) During the sample time the input capacitance C

3) This parameter includes the sample time

may exeed V

AIN

these cases will be X000

internal resistance of the analog source must allow the capacitance to reach their final voltage level within
After the end of the sample time
result.

calibration. Values for the conversion clock
the previous page.

AGND

or V

or X3FFH, respectively.

H

up to the absolute maximum ratings. However, the conversion result in

AREF

t

, changes of the analog input voltage have no effect on the conversion

S

t

, the time for determining the digital result and the time for the

S

t

ADC

must be charged/discharged by the external source. The

AIN

depend on programming and can be taken from the table on

t

.

S

4) T

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

6) Not 100% tested, but guaranteed by design characterization.

is tested at V

UE

other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

AREF

= 5.0 V, V

= 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all

AGND

Semiconductor Group 67 1997-12-01

C505 / C505C

C505A / C505CA

AC Characteristics (12 MHz, 0.5 Duty Cycle)

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB- versions

CC

T

= – 40 to 85 °C for the SAF- versions

A

T

= – 40 to 110 °C for the SAH- versions

A

T

= – 40 to 125 °C for the SAK- versions

A

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics
Parameter Symbol Limit Values Unit

ALE pulse width t
Address setup to ALE t
Address hold after ALE t
ALE to valid instruction in t
ALE to PSEN t
PSEN pulse width t

PSEN to valid instruction in t

Input instruction hold after PSEN t
Input instruction float after PSEN t
Address valid after PSEN t
Address to valid instruction in t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

12 MHz clock

0.5 Duty Cycle

Variable Clock

1/CLP = 2 MHz to 12 MHz

min. max. min. max.

43 – CLP - 40 – ns
17 – CLP/2 - 25 – ns
17 – CLP/2 - 25 – ns
– 80 – 2 CLP - 87 ns
22 – CLP/2 - 20 – ns
95 – 3/2 CLP

–ns

- 30

– 60 – 3/2 CLP

ns

- 65

0–0–ns

*)

– 32 – CLP/2 - 10 ns

*)

37 – CLP/2 - 5 – ns
– 148 – 5/2 CLP

ns

- 60

Address float to PSEN t

*)

Interfacing the C505 to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

AZPL

0–0–ns

Semiconductor Group 68 1997-12-01

C505 / C505C

C505A / C505CA

AC Characteristics (12 MHz, 0.5 Duty Cycle, cont’d)

External Data Memory Characteristics
Parameter Symbol Limit Values Unit

RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

12 MHz clock

0.5 Duty Cycle

Variable Clock

1/CLP = 2 MHz to 12 MHz

min. max. min. max.

180 – 3 CLP - 70 – ns
180 – 3 CLP - 70 – ns
56 – CLP - 27 – ns
– 118 – 5/2 CLP- 90 ns
0–0–ns
– 63 – CLP - 20 ns
– 200 – 4 CLP - 133 ns
– 220 – 9/2 CLP - 155 ns
75 175 3/2 CLP - 50 3/2 CLP + 50 ns
70 – 2 CLP - 97 – ns
17 67 CLP/2 - 25 CLP/2 + 25 ns
5 – CLP/2 - 37 – ns
170 – 7/2 CLP - 122 – ns
15 – CLP/2 - 27 – ns
–0–0ns

External Clock Drive Characteristics
Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 2 MHz to 12 MHz

min. max.

Oscillator period CLP 83.3 500 ns
High time TCL
Low time TCL
Rise time t
Fall time t

R
F

20 CLP-TCLL ns

H

20 CLP-TCLH ns

L

–12ns
–12ns

Oscillator duty cycle DC 0.5 0.5 –

Semiconductor Group 69 1997-12-01

C505 / C505C

C505A / C505CA

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle)

V

= 5 V +10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB- versions

CC

T

= 40 to 85 °C for the SAF- versions

A

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics
Parameter Symbol Limit Values Unit

ALE pulse width t
Address setup to ALE t
Address hold after ALE t
ALE to valid instruction in t
ALE to PSEN t
PSEN pulse width t

PSEN to valid instruction in t

Input instruction hold after PSEN t
Input instruction float after PSEN t
Address valid after PSEN t
Address to valid instruction in t

Address float to PSEN t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

AZPL

16-MHz clock

Duty Cycle

Variable Clock

1/CLP= 2 MHz to 16 MHz

0.4 to 0.6

min. max. min. max.

48 – CLP - 15 – ns
10 – TCL
10 – TCL

-15 – ns

Hmin

-15 – ns

Hmin

– 75 – 2 CLP - 50 ns
10 – TCL
73 – CLP+

TCL

– 38 – CLP+

-15 – ns

Lmin

–ns

-15

Hmin

TCL

Hmin

ns

- 50

0–0–ns

*)

– 15 – TCL

*)

20 – TCL

- 5 – ns

Lmin

– 95 – 2 CLP +

TCL

Lmin

Hmin

-10 ns

ns

-55

-5 – -5 – ns

*)

Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

Semiconductor Group 70 1997-12-01

C505 / C505C

C505A / C505CA

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d)

External Data Memory Characteristics
Parameter Symbol Limit Values Unit

RD pulse width
WR pulse width

Address hold after ALE
RD to valid data in

Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in

ALE to WR or RD

Address valid to WR
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR

Data hold after WR
Address float after RD

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

16-MHz clock

Duty Cycle

Variable Clock

1/CLP= 2 MHz to 16 MHz

0.4 to 0.6

min. max. min. max.

158

– 3 CLP - 30 – ns

158 – 3 CLP - 30 – ns
48 – CLP - 15 – ns
– 100 – 2 CLP+

TCL

Hmin

- 50

ns

0–0 – ns
– 51 – CLP - 12 ns
– 200 – 4 CLP - 50 ns
– 200 – 4 CLP +

TCL

Hmin

73 103 CLP +

TCL

Lmin

- 15

CLP+
TCL

Lmin

-75

+ 15

ns

ns

95 – 2 CLP - 30 – ns
10 40 TCL
5 – TCL
163 – 3 CLP +

TCL

5 – TCL

- 15 TCL

Hmin

- 20 – ns

Lmin

Hmin

+ 15 ns

–ns

- 50

Lmin

- 20 – ns

Hmin

–0– 0 ns

Semiconductor Group 71 1997-12-01

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d)

External Clock Drive Characteristics

C505 / C505C

C505A / C505CA

Parameter Symbol CPU Clock = 16 MHz

Duty Cycle 0.4 to 0.6

Variable CPU Clock

1/CLP = 2 to 16 MHz

Unit

min. max. min. max.

Oscillator period CLP 62.5 62.5 62.5 500 ns
High time TCL
Low time TCL
Rise time t
Fall time t

R

F

H

L

25 – 25 CLP - TCL
25 – 25 CLP - TCL

ns

L

ns

H

– 10 – 10 ns

– 10 – 10 ns
Oscillator duty cycle DC 0.4 0.6 25 / CLP 1 - 25 / CLP –
Clock cycle TCL 25 37.5 CLP * DC

min

CLP * DC

max

ns

Note: The 16 MHz values in the tables are given as an example for a typical duty cycle variation

of the oscillator clock from 0.4 to 0.6.

Semiconductor Group 72 1997-12-01

C505 / C505C

C505A / C505CA

AC Characteristics (20 MHz, 0.5 Duty Cycle)

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB- versions

CC

T

= – 40 to 85 °C for the SAF- versions

A

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics
Parameter Symbol Limit Values Unit

ALE pulse width t
Address setup to ALE t
Address hold after ALE t
ALE to valid instruction in t
ALE to PSEN t
PSEN pulse width t

PSEN to valid instruction in t

Input instruction hold after PSEN t
Input instruction float after PSEN t
Address valid after PSEN t
Address to valid instruction in t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

20 MHz clock

0.5 Duty Cycle

Variable Clock

1/CLP = 2 MHz to 20 MHz

min. max. min. max.

35 – CLP - 15 – ns
10 – CLP/2 - 15 – ns
10 – CLP/2 - 15 – ns
– 55 – 2 CLP - 45 ns
10 – CLP/2 - 15 – ns
60 – 3/2 CLP

–ns

- 15

– 25 – 3/2 CLP

ns

- 50

0–0–ns

*)

– 20 – CLP/2 - 5 ns

*)

20 – CLP/2 - 5 – ns
– 65 – 5/2 CLP

ns

- 60

Address float to PSEN t

*)

Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

AZPL

- 5 – - 5 – ns

Semiconductor Group 73 1997-12-01

C505 / C505C

C505A / C505CA

AC Characteristics (20 MHz, 0.5 Duty Cycle, cont’d)

External Data Memory Characteristics
Parameter Symbol Limit Values Unit

RD pulse width
WR pulse width

Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

20 MHz clock

0.5 Duty Cycle

Variable Clock

1/CLP = 2 MHz to 20 MHz

min. max. min. max.

120

– 3 CLP - 30 – ns

120 – 3 CLP - 30 – ns
35 – CLP - 15 – ns
– 75 – 5/2 CLP- 50 ns
0–0–ns
– 38 – CLP - 12 ns
– 150 – 4 CLP - 50 ns
– 150 – 9/2 CLP - 75 ns
60 90 3/2 CLP - 15 3/2 CLP + 15 ns
70 – 2 CLP - 30 – ns
10 40 CLP/2 - 15 CLP/2 + 15 ns
5 – CLP/2 - 20 – ns
125 – 7/2 CLP - 50 – ns
5 – CLP/2 - 20 – ns
–0–0ns

External Clock Drive Characteristics
Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 2 MHz to 20 MHz

min. max.

Oscillator period CLP 50 500 ns
High time TCL
Low time TCL
Rise time t
Fall time t

R
F

15 CLP-TCL

H

15 CLP-TCL

L

L
H

ns

ns
–10ns
–10ns

Oscillator duty cycle DC 0.5 0.5 –

Semiconductor Group 74 1997-12-01

ALE

t

C505 / C505C

C505A / C505CA

LHLL

PSEN

Port 0

Port 2

t

AVLL

A0 - A7

t

PLPH

t

LLPL

t

LLIV

t

PLIV

t

t

AVIV

t

LLAX

AZPL

t

Instr.IN

t

PXAV

t

PXIZ

PXIX

A0 - A7

A8 - A15 A8 - A15

Figure 31
Program Memory Read Cycle

MCT00096

Semiconductor Group 75 1997-12-01

ALE

PSEN

RD

t

LLWL

t

LLDV

t

RLDV

t

RLRH

t

WHLH

C505 / C505C

C505A / C505CA

t

AVLL

Port 0

A0 - A7 from

Ri or DPL from PCL

t

AVWL

Port 2

Figure 32
Data Memory Read Cycle

t

LLAX2

t

AVDV

t

RLAZ

Data IN

t

RHDZ

t

RHDX

A0 - A7 Instr.

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

IN

MCT00097

Semiconductor Group 76 1997-12-01

ALE

PSEN

t

WHLH

C505 / C505C

C505A / C505CA

WR

t

AVLL

Port 0

A0 - A7 from

Ri or DPL from PCL

t

AVWL

Port 2

Figure 33
Data Memory Write Cycle

t

LLAX2

t

LLWL

t

QVWX

t

WLWH

t

QVWH

Data OUT

t

WHQX

A0 - A7

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

Instr.IN

MCT00098

XTAL1

TCL

H

TCL

L

CLP

t

R

t

F

0.7

V

CC

0.2

- 0.1

V

CC

MCT03310

Figure 34
External Clock Drive on XTAL1

Semiconductor Group 77 1997-12-01

C505 / C505C

C505A / C505CA

AC Characteristics of Programming Mode (C505A and C505CA only)

V

= 5 V ± 10 %; VPP = 11.5 V ± 5 %; TA = 25 °C ± 10 °C

CC

Parameter Symbol Limit Values Unit

min. max.

ALE pulse width t
PMSEL setup to ALE rising edge t
Address setup to ALE, PROG, or PRD falling

edge
Address hold after ALE, PROG, or PRD

falling edge
Address, data setup to PROG or PRD t
Address, data hold after PROG or PRD t
PMSEL setup to PROG or PRD t
PMSEL hold after PROG or PRD t
PROG pulse width t
PRD pulse width t
Address to valid data out t
PRD to valid data out t
Data hold after PRD t
Data float after PRD t
PROG high between two consecutive PROG

low pulses

PAW

PMS

t

PAS

t

PAH

PCS

PCH

PMS

PMH

PWW

PRW

PAD

PRD

PDH

PDF

t

PWH1

35 – ns
10 –
10 – ns

10 – ns

100 – ns
0–ns
10 – ns
10 – ns
100 – µs
100 – ns
–75ns
–20ns
0–ns
–20ns
1–µs

PRD high between two consecutive PRD low

t

PWH2

100 ns

pulses
XTAL clock period t

CLKP

83.3 500 ns

Semiconductor Group 78 1997-12-01

PALE

t

PAW

t

C505 / C505C

C505A / C505CA

PMS

PMSEL1,0

t

PAH

Port 2

t

PAS

A8-A14 A0-A7

Port 0

PROG

t

PCS

Notes: PRD must be high during a programming write cycle.

Figure 35
Programming Code Byte - Write Cycle Timing

H, H

t

D0-D7

PWW

t

PCH

t

PWH

MCT03642

Semiconductor Group 79 1997-12-01

PALE

t

PAW

t

C505 / C505C

C505A / C505CA

PMS

PMSEL1,0

t

PAH

t

PAD

Port 2

t

PAS

A8-A14 A0-A7

Port 0

PRD

t

PCS

PROG must be high during a programming read cycle.Notes:

Figure 36
Verify Code Byte - Read Cycle Timing

H, H

t

PDH

D0-D7

t

t

PRW

t

t

PDFPRD

PCH

t

PWH

MCT03643

Semiconductor Group 80 1997-12-01

C505 / C505C

C505A / C505CA

PMSEL1,0

Port 0

t

PMS

PROG

PRD

PALE should be low during a lock bit read / write cycle.Note:

Figure 37
Lock Bit Access Timing

H, L H, L

D0, D1 D0, D1

t

PCS

t

PWW

t

PCH

t

PMH

t

PMStPRD

t

PRW

t

PDH

t

PDF

t

PMH

MCT03644

PMSEL1,0

Port 2

Port 0

PRD

PROG must be high during a programming read cycle.Note:

t

t

PMS

PCS

L, H

e. g. FD

D0-7

t

PRD

t

PRW

H

t

PCH

t

PDH

t

PDF

t

PMH

MCT03645

Figure 38
Version Byte Read Timing

Semiconductor Group 81 1997-12-01

C505 / C505C

C505A / C505CA

ROM/OTP Verification Characteristics for C505
ROM Verification Mode 1 (C505-2R and C505C-2R only)
Parameter Symbol Limit Values Unit

min. max.

Address to valid data

P1.0 - P1.7
P2.0 - P2.6

Port 0
Address: P1.0 - P1.7 = A0 - A7

Data: P0.0 - P0.7 = D0 - D7

Figure 39
ROM Verification Mode 1

t

AVQV

P2.0 - P2.5 = A8 - A14

–

Address

t

AVQV

Data OUT

Inputs: P2.6, P2.7, PSEN =

ALE, EA =
RESET =

V

IH

V

IH2

5 CLP ns

V

SS

MCT03693

Semiconductor Group 82 1997-12-01

C505 / C505C

C505A / C505CA

ROM/OTP Verification Characteristics for C505 (cont’d)
ROM/OTP Verification Mode 2
Parameter Symbol Limit Values Unit

min. typ max.

ALE pulse width
ALE period

Data valid after ALE
Data stable after ALE
P3.5 setup to ALE low

t

AWD

t

ACY

t

DVA

t

DSA

t

AS

–

CLP

–

ns

– 6 CLP – ns
– – 2 CLP ns
4 CLP – – ns
– t

CL

–ns

Oscillator frequency 1/ CLP 4–6MHz

t

ACY

t

AWD

ALE

t

DSA

t

DVA

Port 0

t

AS

Data Valid

P3.5

MCT02613

Figure 40
ROM/OTP Verification Mode 2

Semiconductor Group 83 1997-12-01

C505 / C505C

C505A / C505CA

V

-0.5 V

CC

0.45 V

AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at V

IHmin

Figure 41
AC Testing: Input, Output Waveforms

+0.90.2

V

CC

Test Points

V

0.2 -0.1

CC

for a logic ’1’ and V

for a logic ’0’.

ILmax

MCT00039

-0.1 V

V

OH

+0.1 V

V

OL

MCT00038

V

Load

V

V

Load

Load

+0.1 V

Timing Reference

Points

-0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.

I

OL/IOH

≥ ± 20 mA

Figure 42
AC Testing : Float Waveforms

Crystal Oscillator Mode Driving from External Source

C

XTAL2

N.C.

XTAL2

2 - 20

MHz

External Oscillator
Signal

C

XTAL1

XTAL1

Crystal Mode: C = 20 pF 10 pF (incl. stray capacitance)

MCS03311

Figure 43
Recommended Oscillator Circuits for Crystal Oscillator

Semiconductor Group 84 1997-12-01

P-MQFP-44-1 (SMD)

(Plastic Metric Quad Flat Package)

C505 / C505C

C505A / C505CA

Figure 44
P-MQFP-44 Package Outline

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”

SMD = Surface Mounted Device

GPM05622

Dimensions in mm

Semiconductor Group 85 1997-12-01