Siemens C505 Technical data

Microcomputer Components

8-Bit CMOS Microcontroller

C505 C505C/C505A C505CA

Data Sheet 12.97

Edition 12.97 Published by Siemens AG,

Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Siemens AG 1997.

©

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer.

Packing

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Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

2

with the express

written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

8-Bit CMOS Microcontroller

Advance Information

• Fully compatible to standard 8051 microcontroller

• Superset of the 8051 architecture with 8 datapointers

• Up to 20 MHz operating frequency – 375 ns instruction cycle time @16 MHz – 300 ns instruction cycle time @20 MHz (50 % duty cycle)

• On-chip program memory (with optional memory protection) – C505-2R/C505C-2R : 16k byte on-chip ROM – C505A-4E/C505CA-4E: 32k byte on-chip OTP – alternatively up to 64k byte external program memory

• 256 byte on-chip RAM

• On-chip XRAM – C505/C505C : 256 byte – C505A/C505CA : 1K byte

• 32 + 2 digital I/O lines – Four 8-bit digital I/O ports – One 2-bit digital I/O port (port 4) – Port 1 with mixed analog/digital I/O capability

C505 C505C C505A

C505CA

(more features on next page)

Oscillator Watchdog

A / D Converter

C505 / C505C: 8-Bit

C505A / C505CA: 10-Bit

Timer 2

Support Module

On-Chip Emulation

Full-CAN Controller

C505C / C505CA only

Watchdog Timer

Figure 1 C505 Functional Units

XRAM

C505 / C505C: 256 Byte

C505A / C505CA: 1 KByte

Timer

0

Timer

1

C500

Core

8 Datapointers

Program Memory

C505 / C505C: 16 k ROM

C505A / C505CA: 32 k OTP

USART

RAM

256 Byte

8-Bit

Port 0

Port 1 Port 2 Port 3 Port 4

I / O 8 Analog Inputs /

8 Digit. I / O I / O

I / O I / O (2-Bit I / O Port)

MCB03628

Semiconductor Group 3 1997-12-01

✓

C505A / C505CA

Features (cont’d):

• Three 16-bit timers/counters – Timer 0 / 1 (C501 compatible) – Timer 2 with 4 channels for 16-bit capture/compare operation

• Full duplex serial interface with programmable baudrate generator (USART)

• Full CAN Module, version 2.0 B compliant (C505C and C505CA only) – 256 register/data bytes located in external data memory area – 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz – internal CAN clock prescaler when input frequency is over 10 MHz

• On-chip A/D Converter – up to 8 analog inputs – C505/C505C : 8-bit resolution – C505A/C505CA: 10-bit resolution

• Twelve interrupt sources with four priority levels

• On-chip emulation support logic (Enhanced Hooks Technology

• Programmable 15-bit watchdog timer

• Oscillator watchdog

• Fast power on reset

• Power Saving Modes – Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake up capability through P3.2/INT0

• P-MQFP-44 package

• Pin configuration is compatible to C501, C504, C511/C513-family

• Temperature ranges:

SAB-C505 versions SAF-C505 versions SAH-C505 versions SAK-C505 versions

= 0 to 70 ° C

T

A

T

= – 40 to 85 ° C

A

T

= – 40 to 110 ° C (max. operating frequency: TBD)

A

T

= – 40 to 125 ° C (max. operating frequency: 12 MHz

A

with 50% duty cycle)

TM

1)

)

or P4.1/RXDC pin

C505 / C505C

Table 1 Differences in Functionality of the C505 MCUs

Device Internal Program Memory XRAM Size A/D Converter

Resolution

8 Bit 8 Bit

C505-2RM C505-LM

C505C-2RM C505C-LM

ROM OTP

16 KB –

– –

256 B 256 B

CAN Controller

– –

✓ ✓

C505A-4EM – 32 KB 1 KB 10 Bit – C505CA-4EM – 32 KB 1 KB 10 Bit

1)

“Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group 4 1997-12-01

°

Table 2 Ordering Information

Type Ordering Code Package Description

(8-Bit CMOS microcontroller)

C505 / C505C

C505A / C505CA

SAB-C505-2RM SAB-C505-LM

SAF-C505-2RM SAF-C505-LM

SAB-C505C-2RM SAB-C505C-LM

SAF-C505C-2RM SAF-C505C-LM

SAB-C505A-4EM Q67127-C2060 P-MQFP-44 with OTP memory (32K), 20 MHz

SAF-C505A-4EM Q67127-C2061 P-MQFP-44 SAB-C505CA-4EM Q67127-C1082 P-MQFP-44 with OTP memory (32K) and CAN, 20 MHz

SAB-C505CA-4EM Q67127-C2058 P-MQFP-44

Q67127-DXXXX Q67127-C2057

Q67127-DXXXX Q67127-C2056

Q67127-DXXXX Q67127-C2029

Q67127-DXXXX Q67127-C2030

P-MQFP-44 P-MQFP-44

with mask-programmable ROM (16K), 20 MHz for external memory (20 MHz)

Extended temperature. – 40 ° C to 85 ° C : with mask-programmable ROM (16K), 20 MHz for external memory (20 MHz)

with mask-progr. ROM (16K) and CAN, 20 MHz for external memory, with CAN (20 MHz)

Extended temperature. – 40 with mask-progr. ROM (16K) and CAN, 20 MHz for external memory, with CAN (20 MHz)

Extended temperature. – 40 with OTP memory (32K), 20 MHz

Extended temperature. – 40 with OTP memory (32K) and CAN, 20 MHz

C to 85 ° C :

Note: The ordering number of the ROM types (DXXXX extension) is defined after program release

(verification) of the customer. Versions for the extended temperature range – 40 125

°

C (SAK-C505) are available on request.

°

C to 110

°

C (SAH-C505) and – 40

°

C to

Semiconductor Group 5 1997-12-01

C505 / C505C

C505A / C505CA

V

AREF

V

AGND

XTAL1 XTAL2

RESET EA

ALE PSEN

V

CC

C505 C505C C505A

C505CA

V

SS

Port

0

8-Bit Digital I / O Port

1 8-Bit Digital I / O / 8-Bit Analog Inputs

Port

2 8-Bit Digital I / O

Port

3 8-Bit Digital I / O

Port4Port 2-Bit Digital I / O

MCL03629

Figure 2 Logic Symbol

Additional Literature

For further information about the C505/C505C/C505A/C505CA the following literature is available:

Title Ordering Number

C505 8-Bit CMOS Microcontroller User’s Manual B158-H7116-X-X-7600 C500 Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600

Semiconductor Group 6 1997-12-01

P0.6 / AD6

P0.7 / AD7

P0.5 / AD5

P0.4 / AD4

P4.1 / RXDCP4.0 / TXDC

EA

ALE

P2.6 / A14

PSEN

P2.7 / A15

C505 / C505C

C505A / C505CA

P2.5 / A13

P0.3 / AD3 P0.2 / AD2

P0.1 / AD1

P0.0 / AD0

V

AREF

V

AGND

P1.0 / AN0 / INT3 / CC0

P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3

P1.4 / AN4

This pin functionality is not available in the C505 and C505A.

33 31 30 29 34 35 36 37 38 39 40 41 42 43 44

2345 78 109

RESET

P1.7 / AN7 / T2

P1.5 / AN5 / T2EX

P1.6 / AN6 / CLKOUT

282726 25

C505 C505C C505A

C505CA

P3.1 / TxD

P3.0 / RxD

2332

24

22

20 19 18 17 16 15 14 13 12

1116

P3.4 / T0

P3.5 / / T1

P3.3 / INT1

P3.2 / INT0

21

P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8

V

CC

V

SS

XTAL1 XTAL2 P3.7 / RD P3.6 / WR

MCP03630

Figure 3 C505 Pin Configuration P-MQFP-44 Package (top view)

Semiconductor Group 7 1997-12-01

Table 3 Pin Deﬁnitions and Functions

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

P1.0-P1.7 40-44,1-3

40

41

42

43

44 1

2

3

I/O

Function

Port 1

is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins can be used for digital input/output or as analog inputs of the A/D converter. Port 1 pins that have 1’s written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current ( pullup transistors. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. As secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). The secondary functions are assigned to the pins of port 1 as follows:

P1.0 / AN0 / INT3

P1.1 / AN1 / INT4 / CC1 Analog input channel 1/

P1.2 / AN2 / INT5 / CC2 Analog input channel 2 /

P1.3 / AN3 / INT6 / CC3 Analog input channel 3

P1.4 / AN4 Analog input channel 4 P1.5 / AN5 / T2EX Analog input channel 5 / Timer 2

P1.6 / AN6 / CLKOUT Analog input channel 6 /

P1.7 / AN7 / T2 Analog input channel 7 /

Port 1 is used for the low-order address byte during program verification of the C505-2R and C505C-2R.

, in the DC characteristics) because of the internal

I

IL

/ CC0 Analog input channel 0

interrupt 3 input / capture/compare channel 0 I/O

interrupt 4 input / capture/compare channel 1 I/O

interrupt 5 input / capture/compare channel 2 I/O

interrupt 6 input / capture/compare channel 4 I/O

external reload / trigger input

system clock output

counter 2 input

*) I = Input

O= Output

Semiconductor Group 8 1997-12-01

Table 3 Pin Deﬁnitions and Functions (cont’d)

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

RESET 4 I

P3.0-P3.7 5, 7-13

5

7

8

9

10 11 12

13

I/O

Function

RESET

A high level on this pin for one machine cycle while the oscillator is running resets the device. An internal diffused resistor to external capacitor to

Port 3

is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current ( characteristics) because of the internal pullup transistors. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data

P3.1 / TxD Transmitter data output (asynch.) or

P3.2 / INT0 External interrupt 0 input / timer 0 gate

P3.3 / INT1 External interrupt 1 input / timer 1 gate

P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR

P3.7 / RD RD control output; enables the external

permits power-on reset using only an

V

SS

.

V

CC

, in the DC

I

IL

). The secondary functions are

input/output (synch.) of serial interface

clock output (synch.) of serial interface

control input

WR control output; latches the data byte from port 0 into the external data memory

data memory

*) I = Input

O= Output

Semiconductor Group 9 1997-12-01

Table 3 Pin Deﬁnitions and Functions (cont’d)

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

P4.0 P4.1

XTAL2 14 O

XTAL1 15 I

6 28

I/O I/O

Function

Port 4

is a 2-bit quasi-bidirectional port with internal pull-up arrangement. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current ( characteristics) because of the internal pullup transistors. The output latch corresponding to the secondary function RXDC must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows (C505C and C505CA only) : P4.0 / TXDC Transmitter output of CAN controller P4.1 / RXDC Receiver input of CAN controller

XTAL2

Output of the inverting oscillator amplifier.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of the etxernal clock signal of 50 % should be maintained. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics must be observed.

, in the DC

I

IL

*) I = Input

O = Output

Semiconductor Group 10 1997-12-01

Table 3 Pin Deﬁnitions and Functions (cont’d)

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

P2.0-P2.7 18-25 I/O

PSEN

26 O The Program Store

Function

Port 2

is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors.

Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation.

, in the DC characteristics)

I

IL

ALE 27 O The Address Latch Enable

output is used for latching the low-byte of the address into external memory during normal operation. It is activated every three oscillator periods except during an external data memory access. When instructions are executed from internal ROM or OTP (EA disabled by bit EALE in SFR SYSCON. ALE should not be driven during reset operation.

*) I = Input

O= Output

=1) the ALE generation can be

Semiconductor Group 11 1997-12-01

Table 3 Pin Deﬁnitions and Functions (cont’d)

C505 / C505C

C505A / C505CA

Symbol Pin Number I/O

*)

EA

P0.0-P0.7 37-30 I/O

29 I

Function

External Access Enable

When held at high level, instructions are fetched from the internal ROM or OTP memory when the PC is less than 4000H (C505 and C505C) or less than 8000H (C505A and C505CA). When held at low level, the C505 fetches all instructions from external program memory. EA be driven during reset operation. For the C505-L and the C505C-L this pin must be tied low.

Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1’s. Port 0 also outputs the code bytes during program verification in the C505-2R/C505C-2R. External pullup resistors are required during program verification.

should not

V

AREF

V

AGND

V

SS

V

CC

*) I = Input

O= Output

38 – Reference voltage for the A/D converter. 39 – Reference ground for the A/D converter. 16 – Ground (0 V) 17 – Power Supply (+ 5 V)

Semiconductor Group 12 1997-12-01

V

CC

V

SS

XTAL1 XTAL2

Oscillator

Watchdog

OSC & Timing

XRAM

1)

256 Byte

1 KByte

RAM

256 Byte

C505 / C505C

C505A / C505CA

ROM OTP

1)

16 K /

32 KByte

RESET ALE PSEN EA

CPU

8 Datapointers

Programmable

Watchdog Timer

Timer 0

Timer 1

Timer 2

USART

Baudrate Generator

Full-CAN

Controller

256 Byte

Reg. / Data

Port 0

Port 1

Port 2

Port 3

Port 4

Port 0 8-Bit Digit. I / O

Port 1 8-Bit Digit. I / O / 8-Bit Analog In

Port 2 8-Bit Digit. I / O

Port 3 8-Bit Digit. I / O

Port 4 2-Bit Digit. I / O

Interrupt Unit

V

AREF

V

AGND

A / D Converter

8- / 10-Bit

1)

Emulation

Support

S & H

C505C / C505CA only.

MUX

Logic

1) C505 / C505C: 256B XRAM / 16KB ROM / 8-Bit ADC C505A / C505CA: 1KB XRAM / 32KB OTP / 10-Bit ADC

MCB03631

25.11.1997

26.09.1997

-

Figure 4 Block Diagram of the C505/C505C/C505A/C505CA

Semiconductor Group 13 1997-12-01

C505 / C505C

C505A / C505CA

CPU

The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% threebyte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns.

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

H

D7

CY AC

H

D6

H

D5

F0

H

D4

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations. F0 General Purpose Flag RS1

RS0

Register Bank Select Control Bits

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F

H

D3

H

D2

H

D1

H

D0

H

PSW

H H H H

OV Overflow Flag

Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

Semiconductor Group 14 1997-12-01

Memory Organization

The C505 CPU manipulates operands in the following four address spaces:

– On-chip program memory : 16 Kbyte ROM (C505-2R/C505C-2R) or

32 Kbyte OTP (C505A-4E/C505CA-4E) – Totally up to 64 Kbyte internal/external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – Internal XRAM data memory : 256 byte (C505/C505C)

1k byte (C505A/C505CA)

– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C505 versions.

Alternatively

C505 / C505C

C505A / C505CA

FFFF

H

Ext.

4000 /

H

8000

H

3FFF / 7FFF

Int.

(EA = 1)

Ext.

(EA = 0)

0000

"Code Space" "Data Space" "Internal Data Space"

"Data Space" F700 to FFFF :

Device

C505 C505C C505A

C505CA

HH

CAN Area

F700 F7FF

HH

F700 F7FF

HH

Unused Area

F700 FEFF F800 FEFF F700 FBFF F800 FBFF

Ext.

Data

Memory

H H

Ext.

Data

Memory

H

XRAM Area

HH HH H H

FF00 FFFF FF00 FFFF

FC00 FFFF

H

FC00 FFFF

H

FFFF

Internal

XRAM

Unused

Area

Int. CAN

H

See table below for detailed Data Memory partitioning

Contr.

(256 Byte)

F6FF

H

F700

H

Indirect

Addr.

Internal

RAM

0000

H

HH HH HH HH

FF

H

80

H

Internal

RAM

Direct

Addr.

Special

Function

Regs.

7F

H

00

H

MCB03632

FF

80

H

Figure 5 C505 Memory Map Memory Map

Semiconductor Group 15 1997-12-01

C505 / C505C

C505A / C505CA

Reset and System Clock

The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the RESET pin to VCC via a capacitor. Figure 6 shows the possible reset circuitries.

V

CC

a)

C505

+

C505C C505A

C505CA

RESET RESET

V

CC

V

CC

c)

C505

+

C505C C505A

C505CA

RESET

&

b)

C505 C505C C505A

C505CA

MCS03633

Figure 6 Reset Circuitries

Semiconductor Group 16 1997-12-01

C505 / C505C

C505A / C505CA

Figure 7 shows the recommended oscillator circuits for crystal and external clock operation.

C

XTAL2

C505

2 - 20 MHz

C

C = 20 pF 10 pF for crystal operation

C505C C505A

C505CA

XTAL1

External Clock Signal

Figure 7 Recommended Oscillator Circuitries

V

CC

N.C.

XTAL2

C505 C505C C505A

C505CA

XTAL1

MCS03634

Semiconductor Group 17 1997-12-01

C505 / C505C

C505A / C505CA

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function regsiter DPSEL. Figure 8 illustrates the datapointer addressing mechanism.

Datapointer

DPTR 0000

.0.1.2

DPTR7

DPTR0

DPH(83 ) DPL(82 )

HH

-----

DPSEL(92 )

DPSEL Selected

.2 .1 .0

0 0 1 DPTR 1 0 1 0 DPTR 2 0 1 1 DPTR 3 1 0 0 DPTR 4 1 0 1 DPTR 5 1 1 0 DPTR 6 1 1 1 DPTR 7

H

Figure 8 External Data Memory Addressing using Multiple Datapointers

External Data Memory

MCD00779

Semiconductor Group 18 1997-12-01

C505 / C505C

C505A / C505CA

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical.

1)

The Enhanced Hooks Technology together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.

TM

, which requires embedded logic in the C500 allows the C500

to Emulation Hardware

SYSCON

PCON TCON

RESET

EA

ALE

PSEN

RSYSCON

RPCON RTCON

C500

MCU Interface Circuit

Optional

I/O Ports

Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration

Port 3 Port 1

Port 0 Port 2

Target System Interface

ICE-System Interface

EH-IC

Enhanced Hooks

RPort 0RPort 2

TEA TALE TPSEN

MCS02647

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.

1)

“Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group 19 1997-12-01

C505 / C505C

C505A / C505CA

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and the mapped special function register area. Five special function register of the C505 (PCON1,P1ANA, VR0, VR1, VR2) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0“).

The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data memory area at addresses F700H to F7FFH..

Special Function Register SYSCON (Address B1H) Reset Value : XX100X01

(C505CA only) Reset Value : XX100001

Bit No. MSB LSB

76543210

B1

H

Bit Function

RMAP Special function register map bit

As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software.

––

The functions of the shaded bits are not described here.

1) This bit is only available in the C505CA.

RMAP = 0 : The access to the non-mapped (standard) special function

RMAP = 1 : The access to the mapped special function register area is

EALE RMAP CMOD

register area is enabled.

enabled.

CSWO

1)

XMAP1

XMAP0

SYSCON

B B

All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.

The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505 are listed in table 4 and table 5. In table 4 they are organized in groups which refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C and C505CA only) are also included in table 4. Table 5 illustrates the contents of the SFRs in numeric order of their addresses. Table 6 list the CAN-SFRs in numeric order of their addresses. .

Semiconductor Group 20 1997-12-01

C505 / C505C

C505A / C505CA

Table 4 Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B DPH DPL DPSEL PSW SP SYSCON

VR0 VR1

VR2

A/DConverter

ADCON0 ADCON1 ADDAT ADST ADDATH

4)

Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer

2)

System Control Register

Version Register 0 Version Register 1

Version Register 2

2)

A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Reg. (C505/C505C) A/D Converter Start Reg. (C505/C505C) A/D Converter High Byte Data Register (C505A/C505CA)

ADDATL

A/D Converter Low Byte Data Register (C505A/C505CA)

P1ANA

Interrupt System

IEN0 IEN1 IP0 IP1 TCON T2CON SCON IRCON

XRAM XPAGE

2) 4)

Port 1 Analog Input Selection Register

2)

Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1

2)

Timer Control Register

2)

Timer 2 Control Register

2)

Serial Channel Control Register Interrupt Request Control Register

Page Address Register for Extended on-chip XRAM and CAN Controller

SYSCON

1)

Bit-addressable special function registers

2)

This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3)

“X“ means that the value is undefined and the location is reserved

4)

This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

5)

The content of this SFR varies with the actual step of the C505 (eg. 01H for the first step)

6)

C505 / C505A only

7)

C505C / C505CA only

2)

System Control Register

E0 F0

83 82 92

D0

81 B1

FC FD FD FE

D8

DC D9 DA D9

DA

90 A8

B8

A9 B9

88 C8 98 C0

91

B1

H

H H H

H

H H H

H

H H

H

1)

00

H

00

H

00

H

00

H

XXXXX000 00

H

07

H

XX100X01 XX100001 C5

H

6)

05

H

7)

85

H

5)

00X00000 01XXX000 00

H

3)

XX

H

00

H

00XXXXXX

FF

H

00

H

00

H

00

H

XX000000 00

H

00X00000 00

H

00

H

00

H

XX100X01 XX100001

B

3) 7)

B

3)

3) 7)

3)

3) 6)

3)

3) 6)

Semiconductor Group 21 1997-12-01

C505 / C505C

C505A / C505CA

Table 4 Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Ports P0

P1 P1ANA P2 P3 P4

Serial Channel

ADCON0 PCON

2)

SBUF SCON SRELL SRELH

Timer 0/ Timer 1

TCON TH0 TH1 TL0 TL1 TMOD

Compare/ Capture Unit / Timer 2

CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON

2)

IEN0

2)

IEN1

Watchdog WDTREL

2)

IEN0

2)

IEN1

2)

IP0

Pow. Save Modes

1)

Bit-addressable special function registers

2)

This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3)

“X” means that the value is undefined and the location is reserved

4)

SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

PCON PCON1

2)

Port 0 Port 1

2) 4)

Port 1 Analog Input Selection Register Port 2 Port 3 Port 4

2)

A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte

Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register

Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Reload Register High Byte Reload Register Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Interrupt Enable Register 0 Interrupt Enable Register 1

Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0

Power Control Register

4)

Power Control Register 1

80

H

90

H

90

H

A0

H

B0

H

E8H D8

H

87

H

99

H

98

H

AA

H

BA

H

88

H

8C

H

8D

H

8A

H

8B

H

89

H

C1

H

C3

H

C5

H

C7

H

C2

H

C4

H

C6

H

CB

H

CA

H

CD

H

CC

H

C8

H

A8

H

B8

H

86

H

A8

H

B8

H

A9

H

87

H

88

H

1)

FF

H

FF

H

FF

H

FF

H

FF

1)

H

XXXXXX11 00X00000

00

H

3)

XX

H

00

H

D9

H

XXXXXX11 00

H

00

H

00

H

00

H

00

H

00

H

3)

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00X00000 00

H

00

H

00

H

00

H

00

H

00

H

00

H

0XX0XXXX

B

3)

B

3)

B

Semiconductor Group 22 1997-12-01

C505 / C505C

C505A / C505CA

Table 4 Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

H H

H

01

H

3)

XX

H

3)

XX

H

3)

UU

H

0UUUUUUU

3)

UU

H

UUU11111

3)

UU

H

3)

UU

H

3)

UU

H

UUUUU000

3)

UU

H

3)

UU

H

3)

UU

H

UUUUU000

B

CAN Controller

(C505C/ C505CA only)

CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1

Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High

F700 F701 F702 F704 F705 F706 F707 F708 F709 F70A F70B F70C F70D F70E F70F

H H H H H H H H H

H

Message Object Registers : MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0n DB1n DB2n DB3n DB4n DB5n DB6n DB7n

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X” means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X”) after a power-on reset operation

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

5) The notation “n” (n= 1 to F) in the message object address definition defines the number of the related message object.

Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7

F7n0 F7n1 F7n2 F7n3 F7n4 F7n5 F7n6 F7n7 F7n8 F7n9 F7nA F7nB F7nC F7nD F7nE

H H H H H H H H H H

H H

H

H H

5)

3)

UU

H

3)

UU

H

3)

UU

H

3)

UU

H

3)

UU

H

UUUUU000 UUUUUU00

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

B

3)

Semiconductor Group 23 1997-12-01

Table 5 Contents of the SFRs, SFRs in numeric order of their addresses

C505 / C505C

C505A / C505CA

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H H H H

H

1)

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 WDT

.6 .5 .4 .3 .2 .1 .0

80 81 82 83 86

2)

P0 FF

H

SP 07

H

DPL 00

H

DPH 00

H

WDTREL 00

H

Reset

PSEL 87 88 88

89 8A 8B 8C 8D 90

PCON 00

H

2)

TCON 00

H

3)

PCON1 0XX0-

H

TMOD 00

H

TL0 00

H

TL1 00

H

TH0 00

H

TH1 00

H

2)

P1 FF

H

H H

XXXX

H H H H H

H

SMOD PDS IDLS SD GF1 GF0 PDE IDLE

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

EWPD – – WS – – – –

B

GATE C/T M1 M0 GATE C/T M1 M0

.7 .6 .5 .4 .3 .2 .1 .0

T2 CLK-

T2EX .4 .3 INT5 INT4 .0

OUT

3)

90 91 92

98 99 A0 A8 A9 AA

1)

2)

3)

P1ANA FF

H

XPAGE 00

H

DPSEL XXXX-

H

X000

2)

SCON 00

H

SBUF XX

H

2)

P2 FF

H

2)

IEN0 00

H

IP0 00

H

SRELL D9

H

X means that the value is undefined and the location is reserved Bit-addressable special function registers SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

H

H H H

H

EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0 .7 .6 .5 .4 .3 .2 .1 .0 –––––.2.1.0

B

SM0 SM1 SM2 REN TB8 RB8 TI RI .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 EA WDT ET2 ES ET1 EX1 ET0 EX0 OWDS WDTS .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 24 1997-12-01

C505A / C505CA

Table 5 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C505 / C505C

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H H

H H H H H H

H H H H H

H

1)

RD WR T1 T0 INT1 INT0 TxD RxD – – EALE RMAP CMOD – XMAP1 XMAP0

B

– – EALE RMAP CMOD CSWO XMAP1 XMAP0

B

EXEN2 SWDT EX6 EX5 EX4 EX3 0 EADC EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC – – .5.4.3.2.1.0

B

––––––.1.0

B

EXF2 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC COCAH3COCAL3COCAH2COCAL2COCAH1COCAL1COCAH0COCAL

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 T2PS I3FR – T2R1 T2R0 T2CM T2I1 T2I0

B

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 CY AC F0 RS1 RS0 OV F1 P BD CLK – BSY ADM MX2 MX1 MX0

B

.7 .6 .5 .4 .3 .2 .1 .0

Reset

2)

B0 B1

P3 FF

H

SYSCON4)XX10-

H

0X01

B1

SYSCON4)XX10-

H

0001 B8 B8 B9

H H H

2)

3)

IEN1 IEN1

00

4)

00

IP1 XX00-

0000 BA

SRELH XXXX-

H

XX11

2)

C0 C1

C2 C3 C4 C5 C6 C7 C8

IRCON 00

H

CCEN 00

H

CCL1 00

H

CCH1 00

H

CCL2 00

H

CCH2 00

H

CCL3 00

H

CCH3 00

H

2)

T2CON 00X0-

H

0000 CA CB CC CD D0 D8

CRCL 00

H

CRCH 00

H

TL2 00

H

TH2 00

H

2)

PSW 00

H

2)

ADCON0 00X0-

H

0000 D9

1)

2)

3)

4)

ADDAT 3)00

H

X means that the value is undefined and the location is reserved Bit-addressable special function registers C505 / C505A only C505C / C505CA only

0

Semiconductor Group 25 1997-12-01

C505A / C505CA

Table 5 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C505 / C505C

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H

H H H

H

1)

.9 .8 .7 .6 .5 .4 .3 .2

––––––––

B

.1.0––––––

B

ADCL1 ADCL0 – – – MX2 MX1 MX0

B

.7 .6 .5 .4 .3 .2 .1 .0 – – – – – – RXDC TXDC

B

.7 .6 .5 .4 .3 .2 .1 .0 110001ß1 00000101

5) 6)

.7 .6 .5 .4 .3 .2 .1 .0

5) 7)

Reset

D9

DA

ADDATH

H

7)

ADST 6)XXXX-

H

00

XXXX

DA

DC

ADDATL

H

7)

ADCON1 01XX-

H

00XXXXXX

X000

2)

E0 E8

ACC 00

H

2)

P4 XXXX-

H

XX11

2)

F0 FC FD FE

B 00

H

3)4)

VR0 C5

H

3)4)

VR1 05

H

3)4)

VR2 01

H

11

1)

X means that the value is undefined and the location is reserved

2)

Bit-addressable special function registers

3)

SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

4)

These are read-only registers

5)

The content of this SFR varies with the actual of the step C505 (eg. 01H or 11H for the first step)

6)

C505 / C505C only

7)

C505A / C505CA only

Semiconductor Group 26 1997-12-01