Siemens BTS 771 G Technical data
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TrilithIC |
BTS 771 G |
Overview
Features
• Quad switch driver
• Free configurable as bridge or quad-switch
•Optimized for DC motor management applications
•Ultra low RDS ON @ 25 °C:
High-side switch: typ. 85 mΩ, |
P-DSO-28-9 |
Low-side switch: typ. 40 mΩ |
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•Very high peak current capability
•Very low quiescent current
•Spaceand thermal optimized power P-DSO-Package
•Load and GND-short-circuit-protected
•Operates up to 40 V
•Status flag diagnosis
•Overtemperature shut down with hysteresis
•Short-circuit detection and diagnosis
•Open-load detection and diagnosis
•C-MOS compatible inputs
•Internal clamp diodes
•Isolated sources for external current sensing
•Overand under-voltage detection with hysteresis
Type |
Ordering Code |
Package |
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BTS 771 G |
Q67007-A9274 |
P-DSO-28-9 |
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Description
The BTS 771 G is a TrilithIC contains one double high-side switch and two low-side switches in one P-DSO-28-9 -Package.
“Silicon instead of heatsink” becomes true
The ultra low RDS ON of this device avoids powerdissipation. It saves costs in mechanical construction and mounting and increases the efficiency.
The high-side switches are produced in the SIEMENS SMART SIPMOS® technology. It is fully protected and contains the signal conditioning circuitry for diagnosis. (The comparable standard high-side product is the BTS 621L1.)
Semiconductor Group |
1 |
1999-01-07 |
BTS 771 G
For minimized the two low-side switches are produced in the SIEMENS Millifet logic level technology (The comparable standard product is the BUZ 103AL).
Each drain of these three chips is mounted on separated leadframes (see P-DSO-28-9 pin configuration). The sources of all four power transistors are connected to separate pins.
So the BTS 771 G can be used in H-Bridge configuration as well as in any other switch configuration.
Moreover, it is possible to add current sense resistors.
All these features open a broad range of automotive and industrial applications.
Semiconductor Group |
2 |
1999-01-07 |
BTS 771 G
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DL1 |
DL1 |
1 |
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28 |
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GL1 |
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SL1 |
2 |
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27 |
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DL1 |
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SL1 |
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3 |
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LS-Lead Frame 1 |
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26 |
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N.C. |
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DL1 |
4 |
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25 |
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DHVS |
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DHVS |
5 |
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24 |
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GND |
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SH1 |
6 |
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23 |
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GH1 |
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SH1 |
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7 |
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22 |
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ST |
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HS-Lead Frame |
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SH2 |
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8 |
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21 |
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GH2 |
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SH2 |
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9 |
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20 |
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DHVS |
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DHVS |
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10 |
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19 |
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N.C. |
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DL2 |
11 |
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18 |
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DL2 |
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LS-Lead Frame 2 |
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SL2 |
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12 |
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17 |
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GL2 |
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SL2 |
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13 |
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16 |
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DL2 |
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DL2 |
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14 |
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15 |
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AEP02071 |
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Figure 1 Pin Configuration (top view)
Semiconductor Group |
3 |
1999-01-07 |
BTS 771 G
Pin Definitions and Functions
Pin No. |
Symbol |
Function |
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1, 3, 25, 28 |
DL1 |
Drain of low-side switch1 |
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Leadframe 1 1) |
2 |
GL1 |
Gate of low-side switch1 |
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4 |
N.C. |
not connected |
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5, 10, 19, 24 |
DHVS |
Drain of high-side switches and power supply voltage |
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Leadframe 2 1) |
6 |
GND |
Ground |
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7 |
GH1 |
Gate of high-side switch1 |
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8 |
ST |
Status of high-side switches; open Drain output |
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9 |
GH2 |
Gate of high-side switch2 |
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11 |
N.C. |
not connected |
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12, 14, 15, 18 |
DL2 |
Drain of low-side switch2 |
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Leadframe 3 1) |
13 |
GL2 |
Gate of low-side switch2 |
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16, 17 |
SL2 |
Source of low-side switch2 |
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20, 21 |
SH2 |
Source of high-side switch2 |
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22, 23 |
SH1 |
Source of high-side switch1 |
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26, 27 |
SL1 |
Source of low-side switch1 |
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1) To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe.
Bold type: Pin needs power wiring
Semiconductor Group |
4 |
1999-01-07 |
BTS 771 G
DHVS
5, 10, 19, 24
8
ST
DST |
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Diagnosis |
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Biasing and Protection |
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C6V1 |
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R I1 |
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Driver |
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GH1 |
7 |
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IN |
OUT |
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3.5 kΩ |
1 |
2 |
1 |
2 |
R O1 |
R O2 |
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DI1 |
0 |
0 |
L |
L |
20, 21 |
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C6V1 |
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SH2 |
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R I2 |
0 |
1 |
L |
H |
10 kΩ |
10 kΩ |
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GH2 |
9 |
1 |
0 |
H |
L |
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3.5 kΩ |
1 |
1 |
H |
H |
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12, 14, 15, 18 |
DL2 |
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DI2 |
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C6V1 |
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22, 23 |
SH1 |
GND |
6 |
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1, 3, 25, 28 |
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DL1 |
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GL1 |
2 |
GL2 |
13 |
26, 27 |
16, 17 |
SL1 |
SL2 |
AEB02072
Figure 2 Block Diagram
Semiconductor Group |
5 |
1999-01-07 |
BTS 771 G
Circuit Description
Input Circuit
The control inputs GH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages.
The inputs GH1 and GH2 are connected to a standard N-channel logic level power-MOS gate.
Output Stages
The output stages consist of an ultra low RDS ON make the outputs short circuit proof to ground negative voltage spikes, which occur when integrated power clamp diodes.
Power-MOS H-Bridge. Protective circuits and load short circuit proof. Positive and driving inductive loads, are limited by
Short Circuit Protection (valid only for the high-side switches)
The outputs are protected against
–output short circuit to ground, and
–overload (load short circuit).
An internal OP-Amp controls the Drain-Source-Voltage of the HS-Switches by comparing the DS-Voltage-Drop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage.
In the case of overloaded high-side switches the status output is set to low.
If the HS-Switches are in OFF-state-Condition internal resistors RO1,2 from SH1,2 to GND pull the voltage at SH1,2 to low values. On each output pin SH1 and SH2 an output
examiner circuit compares the output voltages with the internal reference voltage VEO. This results in switching the status output to low. In H-Bridge condition this feature can be used to protect the low-side switches against short circuit during the OFF-period.
Overtemperature Protection (valid only for the high-side-switches)
The chip also incorporates an overtemperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low.
Undervoltage-Lockout (UVLO)
When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis. The High-Side output transistors are switched off if the supply voltage VS drops below the switch off value VUVOFF.
Semiconductor Group |
6 |
1999-01-07 |
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