Sharp CDXC-8850 Service manual

CDX-C8850/C9500

SERVICE MANUAL

Photo: CDX-C9500

SPECIFICATIONS

AUDIO POWER SPECIFICATIONS (US Model)

POWER OUTPUT AND TOTAL HARMONIC DISTORTION
19 watts per channel minimum continuous average power into
4 ohms, 4 channels driven from 20 Hz to 20 kHz with no more
than 1% total harmonic distortion.

US Model

CDX-C8850

E Model

CDX-C9500

Model Name Using Similar Mechanism CDX-C880
CD Drive Mechanism Type MG-363S-121
Optical Pick-up Name KSS-521A

Other Specifications
CD player section

System Compact disc digital audio

system
Signal-to-noise ratio 98 dB
Frequency response 10 – 20,000 Hz
Wow and flutter Below measurable limit
Laser Diode Properties
Material GaAlAs
Wavelength 780 nm
Emission Duration Continuous
Laser output power Less than 44.6 µW*
* This output is the value measured at a distance

of 200 mm from the objective lens surface on
the Optical Pick-up Block.

Tuner section

FM

Tuning range CDX-C8850:

87.5 – 107.9 MHz

CDX-C9500:

FM tuning interval:

50 kHz/200 kHz switchable

87.5 – 108.0 MHz

(at 50 kHz step)

87.5 – 107.9 MHz

(at 200 kHz step)
Antenna terminal External antenna connector
Intermediate frequency 10.7 MHz
Usable sensitivity 8 dBf
Selectivity 75 dB at 400 kHz

50 dB at 200 kHz
Signal-to-noise ratio 65 dB (stereo),

68 dB (mono)
Harmonic distortion at 1 kHz

0.7% (stereo),

0.4% (mono)
Separation 35 dB at 1 kHz
Frequency response 30 – 15,000 Hz

AM

Tuning range CDX-C8850:

530 – 1,710 kHz
CDX-C9500:
AM tuning interval:
9 kHz/10 kHz switchable
531 – 1,602 kHz
(at 9 kHz step)
530 – 1,710 kHz

(at 10 kHz step)
Antenna terminal External antenna connector
Intermediate frequency 10.71 MHz/450 kHz
Sensitivity 30 µV

Power amplifier section

Outputs Speaker outputs

(sure seal connectors)
Speaker impedance 4 – 8 ohms
Maximum power output 45 W × 4 (at 4 ohms)

– Continued on next page –

FM/AM COMPACT DISC PLAYER

MICROFILM

1

SECTION 4

DIAGRAMS

4-1. IC PIN DESCRIPTIONS

• IC501 CXD2548R (DIGITAL SERVO, DIGITAL SIGNAL PROCESSOR) (SERVO BOARD)

Pin No. Pin Name I/O Pin Description

1 SYSM I System mute input (Not used.)
2 RMUT1 O R-ch, “0” detection output. (“H” : ON, “L” : OFF) (Not used.)
3 LMUT2 O L-ch, “0” detection output. (“H” : ON, “L” : OFF) (Not used.)
4 CKOUT O Master clock frequency division output (Not used.)
5 VDD0 — Digital power supply
6 SBSO O Serial output of sub-P to W.
7 EXCK I Clock input for SBSO read output.
8 SQCK I Clock input for SQSO read output.

9 SQSO O SubQ 80 bit, PCM peak and level data 16 bit output.
10 SENS O SENS output. Output to CPU.
11 SCLK I Clock input for SENS real data read.
12 DATA I Serial data input from CPU.
13 XLAT I Latch input from CPU. Latch serial data at the falling edge.
14 CLOK I Serial data transfer clock input from CPU.
15 XRST I System reset (“L” : Reset)
16 ACDT O Not used.
17 PWM1 I External control input of spindle motor.
18 XLON O Microcomputer extension interface (Output) (Not used.)
19 SPOA I Microcomputer extension interface (Input A) (Not used.)
20 WFCK O WFCK (Write Flame Clock) output
21 GTOP O GTOP output
22 XUGF O XUGF output (Not used.)
23 XPCK O XPLCK output (Not used.)
24 GFS O GFS output
25 RFCK O RFCK output
26 C2PO O C2PO output (Not used.)
27 XROF O XROF output
28 SCOR O “H” output at either detection, sub code sync S0 or S1.
29 MNT0 O MNT0 output (Not used.)
30 MNT1 O MNT1 output (Not used.)
31 MNT3 O MNT3 output (Not used.)
32 VSS1 — Digital GND
33 DOUT O Digital-Out output
34 ATSK I For anti-shock.
35 MIRR O Mirror signal output (Not used.)
36 DFCT O Diffect signal output (Not used.)
37 FOK O Focus OK signal output
38 VDD1 — Digital power supply
39 VPCO1 O Charge pump output for wideband EFM PLL.
40 VPCO2 O VCO2 charge pump output for wideband EFM PLL.
41 VCK.I I VCO2 oscillator input for wideband EFM PLL.
42 V16M O VCO2 oscillator output for wideband EFM PLL.
43 VCTL I VCO2 control input for wideband EFM PLL.
44 PCO O Charge pump output for master PLL.
45 FILO O Filter output for master PLL (slave = digital PLL).
46 FILI I Filter input for master PLL.
47 AVSS4 — Analog GND
48 CLTV I VCO control voltage input for master.
49 AVDD4 — Analog power supply
50 RFAC I EFM signal input
51 BIAS I Asymmetry circuit constant current input

23

Pin No. Pin Name I/O Pin Description

52 ASY.I I Asymmetry comparate voltage input
53 ASY.O O EFM full-swing output (“L” : VSS, “H” : VDD)
54 VC I Center voltage input
55 FE I Focus error signal input
56 SE I Sled error signal input
57 TE I Tracking error signal input
58 CE I Center error signal input
59 RFDC I RF signal input
60 RFC I Condenser connection pin for LPF time constant of RF signal.
61 ADIO O OP amplifier output (Not used.)
62 AVSS3 — Analog GND
63 IGEN I Current source reference resistor connection for OP amplifier.
64 AVDD3 — Analog power supply

65, 66 TES2, 3 I TEST pin (Fixed at “L”.)

67 VSS2 — Digital GND
68 TEST I TEST pin (Fixed at “L”.)
69 SFDR O Sled drive output
70 SRDR O Sled drive output
71 TFDR O Tracking drive output
72 TRDR O Tracking drive output
73 FFDR O Focus drive output
74 FRDR O Focus drive output
75 VDD2 — Digital power supply
76 COUT O Track number count signal output (Not used.)
77 LOCK O Not used.
78 MDS O Servo control output of spindle motor. (Not used.)
79 MDP O Servo control output of spindle motor.
80 SSTP I Disc most inner track detection signal input
81 FSTO O 2/3 frequency division output of pins 103 and 104.
82 FSTI I Reference clock input for digital servo.
83 XTSL I X’tal select input (“L” : 16.9344 MHz)
84 C4M O 4.2336 MHz output
85 WDCK O D/A interface. Word clock f = 2Fs
86 VDD3 — Digital power supply
87 LRCK O D/A interface. LR clock f = Fs
88 LRCKI I LR clock input to DAC. (48 bit slot) (Connect to GND.)
89 PCMD O D/A interface. Serial data (2’s COMP, MSB first)
90 PCMDI I Audio data input to DAC. (48 bit slot) (Connect to GND.)
91 BCK O D/A interface. Bit clock
92 BCKI I Bit clock input to DAC. (48 bit slot) (Connect to GND.)
93 EMPH O Not used.
94 EMPHI I De-emphasis ON/OFF of DAC. (“H” : ON, “L” : OFF) (Connect to GND.)
95 VSS3 — Digital GND
96 AVSS1 — L-ch, Analog GND.
97 AVDD1 — L-ch, Analog power supply.
98 AOUT1 O L-ch, Analog output. (Not used.)

99 AIN1 I L-ch, OP amplifier input. (Connect to GND.)
100 LOUT1 O L-ch, LINE output. (Not used.)
101 A VSS1 — L-ch, Analog GND.
102 XVDD — Analog power supply for master clock.
103 XTAI I X’tal oscillator input of master clock (16.9344 MHz).
104 XTAO O X’tal oscillator output of master clock. (Not used.)
105 XVSS — Analog GND for master clock. (Connect to GND.)

24

Pin No. Pin Name I/O Pin Description

106 A VSS2 — R-ch, Analog GND.
107 ROUT2 O R-ch, LINE output. (Not used.)
108 AIN2 I R-ch, OP amplifier input. (Connect to GND.)
109 AOUT2 O R-ch, Analog output. (Not used.)
110 AVDD2 — R-ch, Analog power supply.
111 A VSS2 — R-ch, Analog GND.
112 VSS0 — Digital GND

25

• IC5 CXP84640-050Q (CD SYSTEM CONTROL) (SERVO BOARD)

Pin No. Pin Name I/O Pin Description

1 – 5 NCO — Not used in this set.

6 FP OPEN I Front panel open detection input
7 FP CLOSE O Front panel close control output
8 LINKOFF I Bus interface link input (Not used in this set.)
9 DRV OE O Focus/tracking coil/sled motor control output

10 D SW I Down switch input (SW4)

11 – 13 NCO — Not used in this set.

14 LM EJ O Loading motor control output

15 LM LOD O Loading motor control output

16 EMPH O O De-emphasis ON/OFF control output

17 CDMON O CD mechanism deck power control output

18 CD ON O CD power control output

19 A MUT O System attenuate control output

20 LD ON O Laser power ON/OFF control output

21 CD RST O CD system reset output

22 – 24 — — Not used in this set.

25 PH3 I Not used in this set.

26 TSTIN0 I Not used in this set.

27 TSTIN1 I Not used in this set.

28 TST CLV I Not used in this set.

29 NCO — Not used in this set.

30 RESET I System reset input (“L” = Reset)

31 X IN I X’tal oscillator input of system clock. (10 MHz)

32 X OUT O X’tal oscillator output of system clock. (10 MHz)

33 GND — Analog GND

34 XT OUT O Not used in this set.

35 XT IN I Not used in this set.

36 AVSS — A/D converter GND

37 AVREF I A/D converter reference voltage input

38 TEP L I Not used in this set.

39 TEP H I Not used in this set.

40 NCO — Not used in this set.

41 PH2 I Not used in this set.

42 SCLK O CD-TEXT data read clock output

43 ESPXQOK O XQOK signal output to DRAM controller.

44 ESPSDT I Serial data input from DRAM controller.

45 GRSRST O Reset signal output to DRAM controller.

46 GRSCOR I Sub-cord sync input from DRAM controller.

47 CD XLAT O CD signal process serial latch output

48 TX CLK O EEPROM serial clock output

49 TX DATA O EEPROM serial data output

50 UNISO O Not used in this set.

51 BUS CLK I/O Bus system serial clock input/output

52 BUS SI I Bus system serial interface input

53 BUS SO O Bus system serial interface output

54 F OK I Focus OK signal input

55 GFS I GFS signal detection input

56 SCOR O Sub-cord sync output

57 SENS I SENS signal input

58 — I Fixed at “H” in this set.

59 CD CKO O CD signal process serial clock output

26

Pin No. Pin Name I/O Pin Description

60 BU.IN I Back-up power detection input
61 BUSON I Bus on control input
62 IN SW I Disc in switch input (SW1)
63 SELF SW I Self switch input (SW2)
64 TX CE O EEPROM chip enable output
65 SCK2 O Sub Q read clock output
66 SI2 I Sub Q 80 bit, PCM peak and level data 16 bit input
67 CD DATA O CD signal process serial data output
68 ESPXWRE O Write signal output to DRAM controller.
69 ESPXRDE O Read signal output to DRAM controller.
70 ESPXLT O Serial data latch output to DRAM controller.
71 ESPXSOE O XSOE signal output to DRAM controller.
72 VDD — Power supply
73 HIN I Fixed at “H” in this set.
74 TEXT.ON/OFF I Fixed at “H” in this set.
75 PH1 I Not used in this set.
76 FBTBSEL I Not used in this set.
77 CDOSEL I Not used in this set.

78 – 80 — — Not used in this set.

27

• IC300 CXD2727Q (DIGITAL SIGNAL PROCESSOR) (MAIN BOARD)

Pin No. Pin Name I/O Pin Description

1 VSS1 — Digital ground

2 – 15 TD0 – 13 I Test pin (Normally, fixed at “L”.)
16 – 21 TST0 – 5 I Test pin (Normally, fixed at “L”.)
22 – 24 JPE1 – 3 I External condition jump input (“H” : condition jump) (Fixed at “L” in this set.)

25 VDD1 — Digital power supply pin (+3.3 V)
26 AVS3 — Analog ground (for D/A converter 1)
27 FL-OUT O Analog signal output for front (L-ch) output.
28 AVD3 — Analog power supply pin (+3.3 V) (for D/A converter 1)
29 RL-OUT O Analog signal output for rear (L-ch) output.
30 AVD5 — Analog power supply pin (+3.3 V) (for D/A converter 1)
31 AVS5 — Analog ground (for D/A converter 1)
32 AVD1 — Analog power supply pin (+3.3 V) (for A/D converter L-ch)
33 AVS1 — Analog ground (for A/D converter L-ch)
34 LREF O Pass control connection pin for A/D converter. (for L-ch)
35 LIN I Tuner and bus audio in signal input (for L-ch)
36 AVS7 — Analog ground (for D/A converter 2)
37 AVD7 — Analog power supply pin (+3.3 V) (for D/A converter 2)
38 NCO — Not used. (Open)
39 AVDX — Analog power supply pin (+3.3 V) (for master clock)
40 XTLO38 O System clock output (16.9344 MHz)
41 XTLI38 I System clock input (16.9344 MHz)
42 AVSX — Analog ground (for master clock)
43 SUB-OUT O Analog signal output for sub woofer output.
44 AVD8 — Analog power supply pin (+3.3 V) (for D/A converter 2)
45 AVS8 — Analog ground (for D/A converter 2)
46 RIN I Tuner and bus audio in signal input (for R-ch)
47 RREF O Pass control connection pin for A/D converter. (for R-ch)
48 AVS2 — Analog ground (for A/D converter R-ch)
49 AVD2 — Analog power supply pin (+3.3 V) (for A/D converter R-ch)
50 AVS6 — Analog ground (for D/A converter 3)
51 AVD6 — Analog power supply pin (+3.3 V) (for D/A converter 3)
52 RR-OUT O Analog signal output for rear (R-ch) output.
53 AVD4 — Analog power supply pin (+3.3 V) (for D/A converter 3)
54 FR-OUT O Analog signal output for front (R-ch) output.
55 AVS4 — Analog ground (for D/A converter 3)
56 VSS2 — Digital ground
57 RST I System reset signal input from system control (IC500). (“L” : reset)
58 BFOT O Master clock output for CD.
59 SCK I Clock signal input for serial data transfer from system control (IC500).

60 REDY O

61 TRDT O Serial data output to system control (IC500).
62 LAT I Serial data latch pulse input from system control (IC500).
63 RVDT I Serial data input from system control (IC500).

64 XS24 I

65 VDD2 — Digital power supply pin (+3.3 V)
66 VSS3 — Digital ground

67 – 69 SO1 – 3 O Serial data output (Not used in this set.)

70 SOUT O Serial data output (Not used in this set.)
71 SI1 I Serial data input

72, 73 SI2, 3 I Serial data input (Fixed at “L” in this set.)

Micon interface transfer permission signal output to system control (IC500).
(“L” : transfer prohibit)

Serial data 24/32 bit slot select signal input from system control (IC500).
(“L” : 24 bit slot, “H” : 32 bit slot) (Valid at slave mode.)

28

Pin No. Pin Name I/O Pin Description

74 SIN I Serial data input (Fixed at “L” in this set.)
75 BCK I Clock signal input for serial bit transfer of serial input/output data.
76 LRCK I Sampling frequency clock signal input of serial input/output data.

77 XMST I

78 VDD3 — Digital power supply pin (+3.3 V)
79 AVSP — PLL system ground
80 PLLEN I PLL enable signal input (Normally, fixed at “L”.)
81 PLCLK O PLL clock signal output (Not used in this set.)
82 CKSTP I PLL clock output control signal input from system control (IC500).
83 AVDP — PLL system power supply pin (+3.3 V)
84 VSS4 — Digital ground

85 – 94 TD14 – 23 I Test pin (Normally, fixed at “L”.)

95 VDD4 — Digital power supply pin (+3.3 V)
96 AVSD — Ground (for D-RAM)
97 SCLI I Not used. (Normally, fixed at “L”.)
98 BIM I Not used. (Normally, fixed at “L”.)
99 SDRAM I Not used. (Normally, fixed at “L”.)

100 AVDD — Power supply pin (+3.3 V) (for D-RAM)

Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode select
signal input from system control (IC500). (“L” : master mode, “H” : slave mode)

29

• IC701 HD6432355A08F (DISPLAY CONTROL) (MAIN BOARD)

Pin No. Pin Name I/O Pin Description

1, 2 PG3, 4 O Not used. (Open)

3 VSS — Ground
4 NC — Not used. (Open)
5 VCC — Power supply pin (+5 V)

6 – 9 PC0 – 3 O Not used. (Open)

10 VSS — Ground
11 – 14 PC4 – 7 O Not used. (Open)
15 – 18 PB0 – 3 O Not used. (Open)

19 VSS — Ground
20 – 23 PB4 – 7 O Not used. (Open)
24 – 27 PA0 – 3 O Not used. (Open)

28 VSS — Ground

29 PA4/IRQ4 O Not used. (Open)

30 PA5/IRQ5 O Not used. (Open)

31 PA6/IRQ6 O Not used. (Open)

32 PA7/IRQ7 O Not used. (Open)

33 SP-LAT I Digital signal processor spectrum analyzer data latch input

34 P66/IRQ2 O Not used. (Open)

35, 36 VSS — Ground

37 P65/IRQ1 O Not used. (Open)

38 BUS-ON I SONY BUS ON input

39 VCC — Power supply pin (+5 V)

40 CD/MD I CD/MD mechanism deck setting input (“L” : CD mechanism deck)
41 – 43 PE1 – 3 O Not used. (Open)

44 VSS — Ground

45 TIR IND O TIR indicator LED drive output

46, 47 PE5, 6 O Not used. (Open)

48 MD LOCK I MD lock signal input (“L” : unlock)

49 BU-IN I Back-up power supply detection input

50 LINK-OFF O LINK OFF output (Not used in this set.)

51 PD2 O Not used. (Open)

52 ILL-ON O Illumination power supply control output

53 VSS — Ground

54 DOOR SW I DOOR switch input (“L” : close, “H” : open)

55 NCO — Not used. (Open)

56 PD6 O Not used. (Open)

57 BOOT I FLASH write mode detection input

58 VCC — Power supply pin (+5 V)

59 NC — Not used. (Open)

60 TX/FL-SO/LCDDATA O LCD driver serial data/FLASH rewriting serial data output

61 SP-SI I Digital signal processor spectrum analyzer data input

62 RX I FLASH rewriting serial data input

63 SP-SCK I Digital signal processor spectrum analyzer data serial clock input

64 LCDCLK O LCD driver/serial clock output

65 VSS — Ground

66 LCDINH O LCD driver inhibit control output

67, 68 VSS — Ground

69 LCDCE0 O LCD chip enable output

70 LCDCE1 O LCD chip enable output

71 P63 O Not used. (Open)
72 – 78 P27 – 21 O Not used. (Open)

79 FL W O FLASH write control output

30