SGS Thomson Microelectronics M48T5Y-70PC1, M48T5V-70PC1, M48T59V-70MH6TR, M48T59V-70MH6, M48T59V-70MH1TR Datasheet

1/21

PRELIMINARY DATA

October 1999

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M48T59

M48T59Y/M48T59V

64 Kbit (8Kb x8) TIMEKEEPER® SRAM

■ INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY

■ FREQUENCY TEST OUTPUT for REAL TIME

CLOCK SOFTWARE CALIBRATION

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

(V

PFD

= Power-fail Deselect Voltage):

– M48T59: 4.5V ≤ V

PFD

≤ 4.75V

– M48T59Y: 4.2V ≤ V

PFD

≤ 4.5V

– M48T59V: 2.7V ≤ V

PFD

≤ 3.0V

■ SELF-CONTAINED BATTERY and CRYSTA L

in the CAPHAT DIP PACKAGE

■ PACKAGING INCLUDES a 28-LEAD SOIC and

SNAPHAT

®

TOP

(to be Ordered Separately)

■ SOIC PACKAGE PROVIDES D IREC T

CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL

■ MICROPROCESSOR POWER-ON RESET

(Valid even during battery back-up mode)

■ PROGRAMM ABLE A L A R M O U TPUT ACTIVE

in the BATTERY BACK-UP MODE

■ BATTERY LOW FLAG

Figure 1. Logic Diagram

AI01380E

13

A0-A12

W

DQ0-DQ7

V

CC

M48T59
M48T59Y
M48T59V

G

V

SS

8

E

RST

IRQ/FT

Table 1. Signal Names

A0-A12 Address Inputs
DQ0-DQ7 Data Inputs / Outputs

IRQ

/FT

Interrupt / Frequency Test
Output (Open Drain)

RST

Power Fail Reset Output
(Open Drain)

E

Chip Enable

G

Output Enable

W

Write Enable

V

CC

Supply Voltage

V

SS

Ground

28

1

28

1

SOH28 (MH)

SNAPHAT (SH)

Battery/Crytstal

PCDIP28 (PC)
Battery/Crystal

CAPHAT

M48T59, M48T59Y, M48T59V

2/21

Figure 2A. DIP Connections

A1
A0

DQ0

A7

A4
A3
A2

A6
A5

IRQ/FT

A10

A8
A9

DQ7

W

A11
G

E

DQ5DQ1

DQ2

DQ3V

SS

DQ4

DQ6

A12

RST V

CC

AI01381D

M48T59

M48T59Y

8

1
2
3
4
5
6
7

9
10
11
12
13
14

16
15

28
27
26
25
24
23
22
21
20
19
18
17

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional opera tion of the devi ce at these or any other conditions above those i ndi cated in th e operational section
of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct
reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowe d on any pin while i n the Batter y Back-up mod e.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Table 3. Operating Modes

(1)

Note: 1. X = VIH or VIL; VSO = Battery Back-up Swit ch ov er Volta ge.

2. See T able 7 for deta ils.

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature

Grade 1 0 to 70

°C

Grade 6 –40 to 85

T

STG

Storage Temperature (VCC Off, Oscillator Off)

–40 to 85 °C

T

SLD

(2)

Lead Solder Temperature for 10 seconds 260 °C

V

IO

Input or Output Voltages –0.3 to 7 V

V

CC

Supply Voltage

M48T59/M48T59Y –0.3 to 7

V

M48T59V –0.3 to 4.6

I

O

Output Current 20 mA

P

D

Power Dissipation 1 W

Mode

V

CC

E G W DQ7-DQ0 Power

Deselect

4.75V to 5.5V
or

4.5V to 5.5V
or

3.0V to 3.6V

V

IH

X X High Z Standby

Write

V

IL

X

V

IL

D

IN

Active

Read

V

IL

V

IL

V

IH

D

OUT

Active

Read

V

IL

V

IH

V

IH

High Z Active

Deselect

V

SO

to V

PFD

(min)

(2)

X X X High Z CMOS Standby

Deselect

≤ V

SO

X X X High Z Battery Back-up Mode

Figure 2B. SOIC Connections

AI01382E

8

2
3
4
5
6
7

9
10
11
12
13
14

22
21
20
19
18
17
16
15

28
27
26
25
24
23

1

A1
A0

DQ0

A7

A4
A3
A2

A6
A5

IRQ/FT

A10

A8
A9

DQ7

W

A11
G

E

DQ5DQ1

DQ2

DQ3V

SS

DQ4

DQ6

A12

RST V

CC

M48T59Y
M48T59V

3/21

M48T59, M48T59Y, M48T59V

DESCRIPTION

The M48T59/59Y/59V TIMEKEEPER

®

RAM is an
8Kb x8 non-volatile static RAM and real time clock.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory and real time clock solution.

The M48T59/59Y/59V is a non-volatile pin and
function equivalent to any JEDEC standard 8Kb x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number o f writes
that can be performed.

The 28 pin 600mil DIP CAPHAT™ houses the
M48T59/ 5 9Y /59V silic o n with a quartz c ry st al and
a long life lithium button cell in a single package.

The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con­nection to a separate SNAPHAT housing cont ain­ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser­tion of the SNAPHAT housing after reflow pre­vents potential battery and c rystal dam age due to
the high temperatures required for device surface­mounting. The SNAPHAT housing is keyed to pre­vent reverse insertion.

Table 4. AC Measurement Conditions

Note that Output Hi-Z is defined as the point where data is no longer
driven.

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Figure 3. Block Diagram

AI01383D

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

V

PFD

RSTV

CC

V

SS

32,768 Hz
CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

16 x 8 BiPORT

SRAM ARRAY

8176 x 8

SRAM ARRAY

A0-A12

DQ0-DQ7

E
W
G

POWER

IRQ/FT

Figure 4. AC Testing Load Circuit

Note: Excluding open-drain output pins.

AI02325

CL = 100pF

CL includes JIG capacitance

645Ω

DEVICE
UNDER

TEST

1.75V

M48T59, M48T59Y, M48T59V

4/21

Table 5. Capacitance

(1, 2)

(T

A

= 25 °C)

Note: 1. Effective capacitance measured with power suppl y at 5V.

2. Sampled only, not 100% tested.

3. Outputs desele ct ed.

Table 6. DC Characteristics

(T

A

= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)

Note: 1. Outputs deselected.

2. Negativ e s p i k e s of –1V allo wed for up to 10ns onc e pe r cycle .

3. The I RQ

/FT and RS T pi ns are Open Drain.

Table 7. Power Down/Up Trip Points DC Characteristics

(1)

(TA = 0 to 70 °C or –40 to 85 °C)

Note: 1. All voltages referenced to VSS.

2. Usi ng larger M4T 32-BR12SH6 SNAPHA T top (recomm ended for I ndustrial Te m perature Range - grade 6 device).

Symbol Parameter Test Condition Min Max Unit

C

IN

Input Capacitance

V

IN

= 0V

10 pF

C

IO

(3)

Input / Output Capacitance

V

OUT

= 0V

10 pF

Symbol Parameter Test Condition

M48T59/Y M48T59V

Unit

Min Max Min Max

I

LI

(1)

Input Leakage Current

0V ≤ V

IN

≤ V

CC

±1 ±1 µA

I

LO

(1)

Output Leakage Current

0V ≤ V

OUT

≤ V

CC

±1 ±1 µA

I

CC

Supply Current Outputs open 50 30 mA

I

CC1

Supply Current (Standby)
TTL

E

= V

IH

32mA

I

CC2

Supply Current (Standby)
CMOS

E

= VCC – 0.2V

31mA

V

IL

(2)

Input Low Voltage –0.3 0.8 –0.3 0.8 V

V

IH

Input High Voltage 2.2

V

CC

+ 0.3

2

VCC + 0.3

V

V

OL

Output Low Voltage

I

OL

= 2.1mA

0.4 0.4 V

Output Low Voltage (IRQ

/FT

and RST

)

(3)

IOL = 10mA

0.4 0.4 V

V

OH

Output High Voltage

I

OH

= –1mA

2.4 2.4 V

Symbol Parameter Min Typ Max Unit

V

PFD

Power-fail Deselect Voltage

M48T59 4.5 4.6 4.75 V
M48T59Y 4.2 4.35 4.5 V
M48T59V 2.7 2.9 3.0 V

V

SO

Battery Back-up Switchover Voltage

M48T59/Y 3.0 V

M48T59V

V

PFD

–100mV

V

t

DR

Expected Data Retention Time (at 25 °C)

Grade 1

7

YEARS

Grade 6

10

(2)

YEARS

5/21

M48T59, M48T59Y, M48T59V

Table 8. Power Down/Up AC Characteristics

(T

A

= 0 to 70 °C or –40 to 85 °C)

Note: 1. V

PFD

(max) to V

PFD

(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-

es V

PFD

(min).

2. V

PFD

(min) to VSS fall time of less than tFB may cause corruption of RAM data.

3. t

REC

(min) = 20ms for industrial temperature grade 6 device.

Symbol Parameter Min Max Unit

t

PD

E or W at VIH before Power Down

0 µs

t

F

(1)

V

PFD

(max) to V

PFD

(min) VCC Fall Time

300 µs

t

FB

(2)

V

PFD

(min) to VSS VCC Fall Time

M48T59/Y 10 µs

M48T59V 150 µs

t

R

V

PFD

(min) to V

PFD

(max) VCC Rise Time

10 µs

t

RB

VSS to V

PFD

(min) VCC Rise Time

1µs

t

REC

(3)

V

PFD

(max) to RST High

40 200 ms

Figure 5. Power Down/Up Mode AC Waveforms

AI03258

V

CC

INPUTS

RST

OUTPUTS

DON'T CARE

HIGH-Z

tF

tFB

tR

tREC

tRB

tDR

VALID VALID

V

PFD

(max)

V

PFD

(min)

VSO

tPD

RECOGNIZED RECOGNIZED

(PER CONTROL INPUT) (PER CONTROL INPUT)

The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For t he 2 8 le ad S OIC , t he ba t­tery/crystal package (i.e. SNAPHAT) part number

is "M4T28-BR12SH" or “M4T32-BR12SH”.
Caution: Do not place the SNAPHAT battery/crys-

tal top in conductive foam, as this will drain the lith­ium button-cell battery.

As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T59/59Y/59V are integrated on one silicon
chip.

The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the by tes with
addresses 1FF8h-1FFFh. The clock locations
contain the century, year, m ont h, d ate, day , hour,
minute, and second in 24 hour BCD format (except
for the century). Corrections for 28, 29 (leap year),
30, and 31 day months are made a utomatically.
Byte 1FF8h is the clock control register. This b yte
controls user access to the clock information and
also stores the clock calibration setting.

M48T59, M48T59Y, M48T59V

6/21

Table 9. Read Mode AC Characteristics

(T

A

= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)

Note: 1. CL = 100pF (see Fig 4).

2. C

L

= 5pF (see Fig 4).

Symbol Parameter

M48T59/M48T5 9Y/M 48T5 9V

Unit-70

Min Max

t

AVAV

Read Cycle Time 70 ns

t

AVQV

(1)

Address Valid to Output Valid 70 ns

t

ELQV

(1)

Chip Enable Low to Output Valid 70 ns

t

GLQV

(1)

Output Enable Low to Output Valid 35 ns

t

ELQX

(2)

Chip Enable Low to Output Transition 5 ns

t

GLQX

(2)

Output Enable Low to Output Transition 5 ns

t

EHQZ

(2)

Chip Enable High to Output Hi-Z 25 ns

t

GHQZ

(2)

Output Enable High to Output Hi-Z 25 ns

t

AXQX

(1)

Address Transition to Output Transition 10 ns

Figure 6. Read Mode AC Waveforms.

Note: Write Enable (W

) = High.

AI01385

tAVAV

tAVQV tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A12

E

G

DQ0-DQ7

VALID

7/21

M48T59, M48T59Y, M48T59V

Table 10. Write Mode AC Characteristics

(T

A

= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)

Note: 1. CL = 5pF (see Fig 4).

2. If E

goes low simultaneously with W going l ow, the output s remain in the h i gh i m pedance state.

Symbol Parameter

M48T59/M48T 59Y/M 48T59V

Unit-70

Min Max

t

AVAV

Write Cycle Time 70 ns

t

AVWL

Address Valid to Write Enable Low 0 ns

t

AVEL

Address Valid to Chip Enable Low 0 ns

t

WLWH

Write Enable Pulse Width 50 ns

t

ELEH

Chip Enable Low to Chip Enable High 55 ns

t

WHAX

Write Enable High to Address Transition 0 ns

t

EHAX

Chip Enable High to Address Transition 0 ns

t

DVWH

Input Valid to Write Enable High 30 ns

t

DVEH

Input Valid to Chip Enable High 30 ns

t

WHDX

Write Enable High to Input Transition 5 ns

t

EHDX

Chip Enable High to Input Transition 5 ns

t

WLQZ

(1, 2)

Write Enable Low to Output Hi-Z 25 ns

t

AVWH

Address Valid to Write Enable High 60 ns

t

AVE1H

Address Valid to Chip Enable High 60 ns

t

WHQX

(1, 2)

Write Enable High to Output Transition 5 ns

The eight clock bytes are not the actual clock
counters themselves; they are memory locat ions
consisting of BiPORT™ read/ write memory cells.
The M48T59/59Y/59V includes a clock control cir­cuit which updates the clock bytes with current in­formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.

The M48T59/59Y/59V also ha s its own P ower-fail
Detect circuit. The control circuitry constantly mon­itors the single 5V supply for an out of tolerance
condition. When V

CC

is out of tolerance, the circuit
write protects the S RAM, p roviding a high degree
of data security in the midst of unpredictable s ys­tem operation brought on by low V

CC

. As VCC falls
below approximately 3V, the control circuitry con­nects the battery which maintains data and clock
operation until valid power returns.

READ MODE

The M48T59/59Y/59V is in the Read Mode when­ever W

(Write Enable) is high and E (Chip Enable)
is low. The unique address specified by the 13 Ad­dress Inputs defines which one of the 8,192 bytes
of data is to be acces sed. Valid data will be avail­able at the Data I/O pi ns within Address Access
time (t

AVQV

) after the last address input s ignal is

stable, providing that the E

and G access times

are also satisfied. If the E

and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access time (t

ELQV

) or Output

Enable Access time (t

GLQV

).

The state of the eight t hree-s tate Da ta I/O s i gnals
is controlled by E

and G. If the outputs are activat-

ed before t

AVQV

, the data lines will be driven to an

indeterminate state until t

AVQV

. If the Ad dres s In-

puts are changed while E

and G remain active,
output dat a will rem ain v alid for Outp ut Dat a Hold
time (t

AXQX

) but will go indeterminate until the next

Addr e ss Access.