SANYO LC662316A, LC662306A, LC662304A, LC662312A, LC662308A Datasheet

CMOS LSI

No. 5483

LC662304A, 662306A, 662308A, 662312A, 662316A

Four-Bit Single-Chip Microcontrollers

with 4, 6, 8, 12, and 16 KB of On-Chip ROM

Preliminary

Overview

The LC662304A, LC662306A, LC662308A, LC662312A, and LC662316A are 4-bit CMOS microcontrollers that integrate on a single chip all the functions required in a special-purpose telephone controller, including ROM, RAM, I/O ports, a serial interface, a DTMF generator, timers, and interrupt functions. These microcontrollers are available in a 42-pin package.

Features and Functions

• On-chip ROM capacities of 4, 6, 8, 12, and 16 kilobytes,

and an on-chip RAM capacity of 512 × 4 bits.

• Fully supports the LC66000 Series common instruction set (128 instructions).

• I/O ports: 36 pins

• DTMF generator This microcontroller incorporates a circuit that can generate two sine wave outputs, DTMF output, or a melody output for software applications.

• 8-bit serial interface: one circuit

• Instruction cycle time: 0.95 to 10 µs (at 3.0 to 5.5 V)

• Powerful timer functions and prescalers — Time limit timer, event counter, pulse width

measurement, and square wave output using a 12-bit timer.

— Time limit timer, event counter, PWM output, and

square wave output using an 8-bit timer.

— Time base function using a 12-bit prescaler.

• Powerful interrupt system with 10 interrupt factors and 7 interrupt vector locations. — External interrupts: 3 factors/3 vector locations — Internal interrupts: 4 factors/4 vector locations

(Waveform output internal interrupts: 3 factors and 1 vector; shared with external expansion interrupts)

• Flexible I/O functions Selectable options include 20-mA drive outputs, inverter circuits, pull-up and open drain circuits.

• Optional runaway detection function (watchdog timer)

• 8-bit I/O functions

• Power saving functions using halt and hold modes.

• Packages: DIP42S, QIP48E (QFP48E)

• Evaluation LSIs: LC66599 (evaluation chip) + EVA800/850-TB662YXX2 LC66E2316(on-chip EPROM microcontroller)

Package Dimensions

unit: mm

3025B-DIP42S

[LC662304A/662306A/662308A/662312A/662316A]

37.9

0.95 0.48

unit: mm

3156-QFP48E

[LC662304A/662306A/662308A/662312A/662316A]

1.0

1.5 36

1.614.0 37

1.5

17.2

1.0

1.5

112

3.0max

0.8

0.35

17.2

14.0

15.6

1.78

1.5 25

1.6

13.8

15.24

5.1

max

4.25

3.8

0.51

min

1.15

SANYO: DIP42S

0.15

0.1

2.70

(STAND OFF)

SANYO: QFP48E

0.25

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

22897HA (OT) No. 5483-1/25

Series Organization

LC662304A, 662306A, 662308A, 662312A, 662316A

Type No.

LC66304A/306A/308A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66404A/406A/408A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66506B/508B/512B/516B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64A LC66354A/356A/358A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66354S/356S/358S 42 4 K/6 K/8 KB 512 W QFP44M LC66556A/558A/562A/566A 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E LC66354B/356B/358B 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66556B/558B/562B/566B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E LC66354C/356C/358C 42 4 K/6 K/8 KB 512 W DIP42S QFP48E 2.5 to 5.5 V/0.92 µs LC662104A/06A/08A 30 4 K/6 K/8 KB 384 W DIP30SD MFP30S LC662304A/06A/08A/12A/16A 42 LC662508A/12A/16A 64 8 K/12 K/16 KB 512 W DIP64S QFP64E

LC665304A/06A/08A/12A/16A 48

LC66E308 42 EPROM 8 KB 512 W LC66P308 42 OTPROM 8 KB 512 W DIP42S QFP48E

LC66E408 42 EPROM 8 KB 512 W LC66P408 42 OTPROM 8 KB 512 W DIP42S QFP48E

LC66E516 64 EPROM 16 KB 512 W LC66P516 64 OTPROM 16 KB 512 W DIP64S QFP64E

LC66E2108* 30 EPROM 8 KB 384 W LC66E2316 42 EPROM 16 KB 512 W

LC66E2516 64 EPROM 16 KB 512 W

LC66E5316 52/48 EPROM 16 KB 512 W LC66P2108* 30 OTPROM 8 KB 384 W DIP30SD MFP30S

LC66P2316* 42 OTPROM 16 KB 512 W DIP42S QFP48E LC66P2516 64 OTPROM 16 KB 512 W DIP64S QFP64E LC66P5316 48 OTPROM 16 KB 512 W DIP48S QFP48E

Note: * Under development

No. of

pins capacity

ROM capacity

4 K/6 K/8 K/12 K/16 KB

RAM

512 W DIP42S QFP48E

512 W DIP48S QFP48E

DIC42S QFC48 with window with window

DIC64S QFC64 with window with window

DIC42S QFC48 with window with window

DIC64S QFC64 with window with window

DIC52S QFC48 with window with window

Package Features

Normal versions

4.0 to 6.0 V/0.92 µs

Low-voltage versions

2.2 to 5.5 V/3.92 µs

Low-voltage high-speed versions

3.0 to 5.5 V/0.92 µs

On-chip DTMF generator versions

3.0 to 5.5 V/0.95 µs

Dual oscillator support

3.0 to 5.5 V/0.95 µs

Window and OTP evaluation versions

4.5 to 5.5 V/0.92 µs

Window evaluation versions

4.5 to 5.5 V/0.92 µs

OTP

4.0 to 5.5 V/0.95 µs

No. 5483-2/25

Pin Assignments

LC662304A, 662306A, 662308A, 662312A, 662316A

DIP42S

P20/SI0

1 2P21/SO0 3P22/SCK0 4P23/INT0 5P30/INT1 6P31/POUT0 7P32/POUT1 8V

9OSC1 10OSC2 11V 12RES 13PE0 14PE1 15TEST 16P33/HOLD 17P40/INV01 18P41/INV00 19P42/INV11 20P43/INV10 21P50

LC662304A

2306A 2308A 2312A 2316A

42 P13 41 P12 40 P11 39 P10 38 P03 37 P02 36 P01 35 P00 34 PD3/INV30 33 PD2/INV31 32 PD1/INV20 31 PD0/INV21 30 PC3 29 PC2 28 P63/PIN1 27 P62/DT 26 P61 25 P60/ML 24 P53/INT2 23 P52 22 P51

QFP48E

P02

P01

P00

PD3/INV3O

PD2/INV3I

PD1/INV2O

PD0/INV2I

PC3

PC2

P63/PIN

P62/DT

25 37P03 38P10 23 P60/ML 39P11 22 P53/INT2 40P12 21 P52 41P13 20 P51 42NC 19 NC 43NC 18 NC 44P20/SI0 17 P50 45P21/SO0 16 P43/INV1O 46P22/SCK0 15 P42/INV1I 47P23/INT0 14 P41/INV0O 48P30/INT1 13 P40/INV0I

P31/POUT0

LC662304A

OSC1

OSC2

P32/POUT1

2306A 2308A 2312A 2316A

PE0

RES

PE1

24 P61

TEST

P33/HOLD

Top view

We recommend the use of reflow-soldering techniques to solder-mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques).

No. 5483-3/25

System Block Diagram

LC662304A, 662306A, 662308A, 662312A, 662316A

RAM STACK

RES

TEST OSC1 OSC2 HOLD

ML DT

SYSTEM

CONTROL

DTMF

GEN.

(512W)

FLAG

SP E A

M R

PRESCALER

MPX TIMER0 SERIAL I/O 0

MPX

INTERRUPT

CONTROL

MPX

ALU

TIMER1

P0 P1 P2 P3 P4 P5 P6

Differences between the LC663XX Series and the LC6623XX Series

ROM

4K/6K/8K/12K/16KB

xO INVxI

INV

POUT0 SI0 SO0 SCK0

INT0

INT1, INT2

PIN1, POUT1

(x=0 to 3)

Item

System differences

• Hardware wait time (number of

cycles) when hold mode is cleared

• Value of timer 0 after a reset

(Including the value after hold mode Set to FF0. Set to FFC. Set to FFC. is cleared)

• DTMF generator

• Inverter array

• SIO1 Yes Yes None

• Three-value inputs/comparator

inputs

• Three-state output from P31

and P32

• Using P0 to clear halt mode In 4-bit groups In 4-bit groups Can be specified for each bit.

• External extended interrupts (Tools are handled with external None for INT3, INT4, and INT5.

• Other P53 functions (Tools are handled with external Shared with INT2 Shared with INT2

Differences in main characteristics

• Operating power-supply voltage

and operating speed (cycle time)

• Pull-up resistors P0, P1, P4, and P5: about 3 to 10 kΩ P0, P1, P4, and P5: about 3 to 10 kΩ P0, P1, P4, and P5: about 100 kΩ

• Port voltage handling • P0, P1, PD, PE: Normal voltage • P0, P1, PD, PE: Normal voltage handling Others: normal voltage

(Including the LC66599 evaluation chip)

65536 cycles 16384 cycles 16384 cycles About 64 ms at 4 MHz (Tcyc = 1 µs) About 16 ms at 4 MHz (Tcyc = 1 µs) About 16 ms at 4 MHz (Tcyc = 1 µs)

None (Tools are handled with external devices.)

Yes Yes None

None None Yes

None for INT3, INT4, and INT5.

devices.) Shared with INT2

devices.)

• LC66304A/306A/308A • 3.0 to 5.5 V/0.92 to 10 µs

• LC66E308/P308 2.2 to 5.5 V/3.92 to 10 µs

• P2 to P6 and PC: 15-V handling • P2 to P6 and PC: 15-V handling P2, P3, P61, and P63: 12-V voltage

LC6630X Series

4.0 to 6.0 V/0.92 t 10 µs • LC6635XA

4.5 to 5.5 V/0.92 to 10 µs 3.0 to 5.5 V/1.96 to 10 µs

handling handling handling

LC6635XB Series LC6623XX Series

None Yes

INT3, INT4, and INT5 can be used with the internal functions.

3.0 to 5.5 V/0.95 to 10 µs

No. 5483-4/25

Pin Function Overview

LC662304A, 662306A, 662308A, 662312A, 662316A

Pin I/O Overview Output driver type Options

P00 P01 P02 P03

P10 P11 P12 P13

P20/SI0

P21/SO0

P22/SCK0

P23/INT0

P30/INT1 P31/POUT0 P32/POUT1

I/O ports P00 to P03

• Input or output in 4-bit or 1-bit units

• P00 to P03 support the halt mode

I/O

control function (This function can be specified in bit units.)

I/O ports P10 to P13

I/O

Input or output in 4-bit or 1-bit units

I/O ports P20 to P23

• Input or output in 4-bit or 1-bit units

• P20 is also used as the serial input SI0 pin.

• P21 is also used as the serial output SO0 pin.

I/O

• P22 is also used as the serial clock SCK0 pin.

• P23 is also used as the INT0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input.

I/O ports P30 to P32

• Input or output in 3-bit or 1-bit units

• P30 is also used as the INT1 interrupt request.

• P31 is also used for the square wave

I/O

output from timer 0.

• P32 is also used for the square wave and PWM output from timer 1.

• P31 and P32 also support 3-state outputs.

• Pch: Pull-up MOS type

• Nch: Intermediate sink current type

• Pch: Pull-up MOS type

• Nch: Intermediate sink current type

• Pch: CMOS type

• Nch: Intermediate sink current type

• Nch: +12-V handling when OD option selected

• Pch: CMOS type

• Nch: Intermediate sink current type

• Nch: +12-V handling when OD option selected

• Pull-up MOS or Nch OD output

• Output level on reset

• Pull-up MOS or Nch OD output

• Output level on reset

CMOS or Nch OD output

State after a Standby mode

reset operation

Hold mode:

High or low (option)

Output off

Halt mode: Output retained

Hold mode: Output off

Halt mode: Output retained

Hold mode: Output off

Halt mode: Output retained

Hold mode: Output off

Halt mode: Output retained

P33/HOLD

P40/INV0I

P41/INV0O

P42/INV1I

P43/INV1O

Hold mode control input

• Hold mode is set up by the HOLD instruction when HOLD is low.

• In hold mode, the CPU is restarted by setting HOLD to the high level.

• This pin can be used as input port P33

along with P30 to P32.

• When the P33/HOLD pin is at the low level, the CPU will not be reset by a low level on the RES pin. Therefore, applications must not set P33/HOLD low when power is first applied.

I/O ports P40 to P43

• Input or output in 4-bit or 1-bit units

• Input or output in 8-bit units when used in conjunction with P50 to P53.

I/O

• Can be used for output of 8-bit ROM data when used in conjunction with P50 to P53.

• Dedicated inverter circuit (option)

• Pch: Pull-up MOS type

• CMOS type when the inverter circuit option is selected

• Nch: Intermediate sink current type

• Pull-up MOS or Nch OD output

• Output level on reset

• Inverter circuit

Hold mode: Port output off, inverter

High or low or inverter I/O (option)

output off

Halt mode: Port output retained, inverter output continues

Continued on next page.

No. 5483-5/25

Continued from preceding page.

LC662304A, 662306A, 662308A, 662312A, 662316A

Pin I/O Overview Output driver type Options

I/O ports P50 to P53

• Input or output in 4-bit or 1-bit units

P50 P51 P52

P53/INT2

P60/ML

P61

P62/DT

P63/PIN1

PC2 PC3

• Input or output in 8-bit units when used in conjunction with P40 to P43.

I/O

• Can be used for output of 8-bit ROM data when used in conjunction with P40 to P43.

• P53 is also used as the INT2 interrupt request.

I/O ports P60 to P63

• Input or output in 4-bit or 1-bit units

• P60 is also used as the melody output ML pin.

I/O

• P62 is also used as the tone output DT pin.

• P63 is also used for the event count input to timer 1.

I/O ports PC2 to PC3

I/O

Output in 2-bit or 1-bit units

• Pch: Pull-up MOS type

• Nch: Intermediate sink current type

• Pch: CMOS type

• Nch: Intermediate sink current type

• Nch: +12-V handling when OD option selected (P61 and P63 only)

• Pch: CMOS type

• Nch: Intermediate sink current type

• Pull-up MOS or Nch OD output

• Output level on reset

CMOS or Nch OD output

State after a Standby mode

reset operation

Hold mode: Output off

High or low (option)

Halt mode: Output retained

Hold mode: Output off

Halt mode: Output retained

Hold mode: Port output off

Halt mode: Port output retained

PD0/INV2I

PD1/INV2O

PD2/INV3I

PD3/INV4O

PE0 PE1

OSC1

OSC2

RES

TEST

Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD.

CMOS output: Complementary output. OD output: Open-drain output.

Dedicated input ports PD0 to PD3

Dedicated inverter circuits (option)

Dedicated input ports

System clock oscillator connections When an external clock is used, leave

OSC2 open and connect the clock signal to OSC1.

System reset input When the P33/HOLD pin is at the high

level, a low level input to the RES pin will initialize the CPU.

CPU test pin

This pin must be connected to V during normal operation.

Power supply pins

• When the inverter circuit option is selected.

• Pch: CMOS type

• Nch: Intermediate sink current type

Inverter circuits

Ceramic oscillator or external clock selection

Normal input or inverter I/O (option)

Normal input

Option selection

Inverter

• Hold mode: output off

• Halt mode: output continues

Hold mode: Oscillator stops

Halt mode: Oscillator continues

No. 5483-6/25

LC662304A, 662306A, 662308A, 662312A, 662316A

User Options

1. Port 0, 1, 4, and 5 output level at reset option The output levels at reset for I/O ports 0, 1, 4, and 5 in independent 4-bit groups, can be selected from the following two options.

Option Conditions and notes

1. Output high at reset The four bits of ports 0, 1, 4, or 5 are set in a group

2. Output low at reset The four bits of ports 0, 1, 4, or 5 are set in a group

2. Oscillator circuit options

• Main clock

Option Circuit Conditions and notes

1. External clock

2. Ceramic oscillator

Note: There is no RC oscillator option.

OSC1

Ceramic oscillator

The input has Schmitt characteristics

OSC1

OSC2

3. Watchdog timer option A runaway detection function (watchdog timer) can be selected as an option.

4. Port output type options

• The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be

selected individually from the following two options.

Option Circuit Conditions and notes

Output data

1. Open-drain output

2. Output with built-in pull-up resistor

DSB

 

Input data

Output data

Input data

The port P2, P3, P5, and P6 inputs have Schmitt characteristics.

The CMOS outputs (ports P2, P3, P6, and PC) and the pull-up MOS outputs (P0, P1, P4, and P5) are distinguished by the drive capacity of the p-channel transistor.

No. 5483-7/25

LC662304A, 662306A, 662308A, 662312A, 662316A



5. Inverter array circuit option One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PD0/PD1, and PD2/PD3. (PDs do not use option 1 because they are dedicated to input.)

Option Circuit Conditions and notes

Output data 

1. Normal port I/O circuit

Input

DSB



Input data

Output data

Input data

Output data high

Input data

When the open-drain output type is selected

When the built-in pull-up resistor output type is selected

2. Inverter I/O circuit

Output

DSB

Output data high

Input data

If this option is selected, The I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected.

No. 5483-8/25

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