Samsung KT8557BN, KT8557BJ, KT8554BN, KT8554BJ, KT8554BD Datasheet
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KT8554B/7B 1 CHIP CODECS
INTRODUCTION
The KT8554B/7B are single-chip PCM encoders and decoders
(PCM CODECs) and PCM line filters. These devices provide
all the functions required to interface a full-duplex voice
telephone circuit with a time-division-multiplex (TDM)
system.
These devices are designed to perform the transmit encoding
and receive decoding as well as the transmit and receive filtering functions in PCM system. They are intended to be used
at the analog termination of a PCM line or trunk.
These devices provide the bandpass filtering of the analog
signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and
call progress tones as well as the signalling and supervision
information.
FEATURES
• Complete CODEC and filtering system
• Meets or exceeds AT&T D3/D4 and CCITT
specifications
µ-Law : KT8554B, A-Law : KT8557B
• On-chip auto zero, sample and hold, and precision
voltage references
• Low power dissipation : 60mW (operating)
3mW (standby)
• ± 5V operation
• TTL or CMOS compatible
• Automatic power down
PIN CONFIGURATION
Fig. 1
Device Package Operating Temperature
KT8554BJ
KT8557BJ
16-CERDIP
- 25 ~ 125°C
KT8557BN
KT8554BN
16-DIP-300A
- 25 ~ 70°C
KT8554BD
KT8557BD
16-SOP-BD300
-SG
- 25 ~ 70°C
VFXI
+
VFXI
-
GS
X
TS
X
FSXS
D
X
BCLK
X
MCLK
X
V
BB
GNDA
VFRO
V
CC
FS
R
D
R
BCLKR/CLKSEL
MCLKR/PDN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
KT8554B/7B
ORDERING INFORMATION
16-CERDIP
16-DIP-
16-SOP-BD300
-SG
KT8554B/7B 1 CHIP CODECS
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS (Ta = 25
o
C)
Pin No Symbol Description
1 V
BB
VBB = - 5V ±5%.
2 GNDA Analog ground.
3 VFRO Analog output of the receive power Amp.
4 V
CC
V
CC
= +5V ± 5%.
5 FS
R
Receive frame sync pulse. 8KHz pulse train.
6 D
R
PCM data input.
7
Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master
clock in normal operation and BCLKX is used for both TX and RX directions.
Alternately direct clock input available, very from 64KHz to 2.048MHz.
8
When MCLKR is connected continuously high, the device is powered down.
Normally connected continusously low, MCLKX is selected for all DAC timing.
Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available.
9 MCLK
X
Must be1.536MHz/1.544MHz or 2.048MHz.
May be vary from 64KHz to 2.048MHz but BCLKX is externally tied with MCLK
X
in normal operation.
11 D
X
PCM data output.
12 FS
X
TX frame sync pulse. 8KHz pulse train.
13 TS
X
Changed from high to low during the encoder timeslot. Open drain output.
Analog output of the TX input amplifier.
Used to set gain through external resistor.
15 VFXI
-
Inverting input stage of the TX analog signal.
16 VFXI
+
Non-inverting input stage of the TX analog signal.
Characteristic Symbol Value Unit
Positive Supply Voltage
V
CC
7 V
Negative Supply Voltage V
BB
- 7 V
Voltage at Any Analog Input or Output V
I (A)
V
CC
+ 0.3 to V
BB
- 0.3 V
Voltage at Any Digital Input or Output Vl
(D)
V
CC
+ 0.3 to GNDA - 0.3 V
Operating Temperature Range Ta - 25 to + 125
o
C
Storage Temperature Range T
STG
- 65 to + 150
o
C
Lead Temperature (Soldering, 10 secs) T
LEAD
300
o
C
10
BCLK
X
BCLKR /
CLKSEL
MCLKR /
PDN
GS
X
14
KT8554B/7B 1 CHIP CODECS
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, VCC = 5.0V ±5%, VBB = - 5.0V ±5%, GNDA = 0V, Ta = 0 oC to 70 oC ; typical characteristics
specified at V
CC
= 5.0V, V
BB
= - 5.0V, Ta = 25 oC ; all signals referenced to GNDA).
Characteristic Symbol Test Conditions Min Typ Max Unit
Power Dissipation
Power-Down Current I
CC (DOWN)
No Load 0.5 1.5 mA
Power-Down Current I
BB (DOWN)
No Load 0.05 0.3 mA
Active Current I
CC (A)
No Load 6.0 9.0 mA
Active Current I
BB (A)
No Load 6.0 9.0 mA
Digital Interface
Input Low Voltage V
IL
0.6 V
Input High Voltage V
IH
2.2 V
Input Low Current I
IL
GNDA ≤ VIN≤VIL, all digital inputs
-10 10
µA
Input High Current I
IH
V
IH
≤ V
IN
≤ V
CC
-10 10
µA
Output Low Voltage V
OL
DX,IL = 3.2mA
SIGR, IL = 1.0mA
TSX, IL = 3.2mA,open drain
0.4
0.4
0.4
V
V
V
DX, IH = -3.2mA
SIGR, IH = -1.0 mA
2.4
2.4
V
V
Output Current in High Impedance
State (TRI-STATE)
I
O (HZ)
DX, GNDA ≤ V
O
≤ V
CC
-10 10
µA
Analog Interface with Receive Filter
Output Resistance R
O
Pin VFRO 1 3
Ω
Load Resistance R
L
VFRO = ±2.5V
600
Ω
Load Capacitance C
L
500 pF
Output DC Offset Voltage V
OO (RX)
-200 200 mV
Analog Interface with Transmit input Amplifier
Input Leakage Current I
LKG
-2.5V≤V≤+2.5V, VFXI + or VFXI -
-200 200 nA
Input Resistance R
I
-2.5V≤V≤+2.5V, VFXI + or VFXI -
10
MΩ
Output Resistance R
O
Closed loop, unity gain 1 3
Ω
Load Resistance R
L
GS
X
10
KΩ
Load Capacitance C
L
GS
X
50 pF
Output Dynamic Range V
OD (TX)
GSX, RL≤10KW ±2.8
V
Voltage Gain G
V
VFXI + to GS
X
5,000 V/V
Unity Gain Bandwidth BW 1 2 MHz
Offset Voltage V
IO (TX)
-20 20 mV
Common-Mode Voltage V
CM (TX)
CMRRXA > 60dB -2.5 2.5 V
Common-Mode Rejection Ratio CMRR DC Test 60 dB
Power Supply Rejection Ratio PSRR DC Test 60 dB
Output High Voltage
V
OH
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