Samsung KT3170N Datasheet

KT3170 LOW POWER DTMF RECEIVER

ORDERING INFORMATION

INTRODUCTION

18-DIP-300A

The KT3170 is a complete Dual Tone Multiple Frequency
(DTMF) receiver that is fabricated by low power CMOS
and the Switched-Capacitor Filter technology.
This LSI consists of band split filters, which seperates
counting section which verifies the frequency and
duration of the received tones before passing the cor­responding code to the output bus. It decodes all 16
DTMF tone pairs into a 4bits digital code.
The externally required components are minimized by
on chip provision of a differential input AMP, clock
oscillator and latched three state interface. The on chip
clock generator requires only a low cost TV cystal as
an external component.

FEATURES

• Detects all 16 standard tones.

• Low power consumption : 15mW (Typ)

• Single power supply : 5V

• Uses inexpensive 3.58MHz crystal

• Three state outputs for microprocessor interface

• Good quality and performance for using in

exchange system

Device Package Operating

KT3170N 18-DIP-300A

• Power down mode/input inhibit

APPLICATIONS PIN CONFIGURATION

• PABX

• Central Office

• Paging Systems

• Remote Control

• Credit Card Systems

• Key Phone System

• Answering Phone

• Home Automation System

• Mobile Radio

• Remote Data Entry

IN+

1

2

IN-

GS

3

V

4

REF

I

5

IN

6

PDN

7

OSC1

OSC2

8

GND

9 10

KT3170

V

DD

18

17

SI/GTO

ESO

16

DSO

15

Q4

14

13

Q3

12

Q2

Q1

11

OE

- 25°C ~ + 75°C

Fig. 1

KT3170 LOW POWER DTMF RECEIVER

PIN DESCRIPTION

Pin No Symbol Description

1 IN + Non inverting input of the op amp.

2 IN - Inverting input of the op amp.

3 GS

4 V

5 I

REF

IN

6 PDN

7, 8

OSC1
OSC2

9 GND Ground pin.

10 OE

11 - 14 Q1 - Q4

15 DSO

16 ESO

17 SI/GTO

18 V

DD

Gain Select. The output used for gain adjustment of analog input
signal with a feedback resistor.
Reference Voltage output (VDD/2, Typ) can be used to bias the op amp
input of VDD/2.
Input inhibit. High input states inhibits the detection of tones. This
pin is pulled down internally.
Control input for the stand-by power down mode. Power down occurs
when the signal on this input is in high states. This pin is pulled down
internally.
Clock input/output. A inexpensive 3.579545MHz crystal connected
between these pins completes internal oscillator. Also, external clock
can be used.

Output Enable input. Outputs Q1-Q4 are CMOS push pull when OE is
High and open circuited (High impedance) when disabled by pulling OE
low. Internal pull up resistor built in.
Three state data output. When enabled by OE, these digital outputs
provide the hexadecimal code corresponding to the last valid tone
pair received.
Delayed Steering Output. Indicates that valid frequencies have been
present for the required guard time, thus constituting a valid signal.
Presents a logic high when a received tone pair has been registered
and the output latch is updated. Returns to logic low when the
voltage on SI/GTO falls below VTH.
Early Steering Outputs. Indicates detection of valid tone output a
logic high immediately when the digital algorithm detects a
recognizable tone pair. Any momentary loss of signal condition will
cause ESO to return to low.
Steering Input/Guard Time Output. A voltage greater the V

TS

detected at SI causes the device to register the detected tone pair
and update the output latch. A voltage less than VTS frees the device
to accept a new tone pair. The GTO output acts to reset the external
steering time constant, and its state is a function of ESO and the
voltage on SI

Power Supply (+5V, Typ)

KT3170 LOW POWER DTMF RECEIVER

ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit

Power Supper Voltage
Analog Input Voltage Range
Digital Input Voltage Range
Output Voltage Range
Current On Any Pin
Operating Temperature
Storage Temperature

ELECTRICAL CHARACTERISTICS (V

V

DD

V

I (A)

V

I (D)

V

O

I

I

T

OPR

T

STG

= 5V, Ta = 25°C, unless otherwise noted)

DD

6

- 0.3 ~ VDD + 0.3

- 0.3 ~ VDD + 0.3

- 0.3 ~ VDD + 0.3
10

- 40 ~ + 85

-60 ~ + 150

V
V
V
V

mA

°C
°C

Characteristic Symbol Test Conditions Min Typ Max Unit

Operating Voltage V
Operating Current I
Power Dissipation P
Input Voltage Low V
Input Voltage High V
Input Leakage Current I
Pull Up Current On OE Pin I

DD

DD

D

IL

IH

I (LKG)

PU

Analog Input Impedance R
Steering Input Threshold Voltage V
Output Voltage Low V

- V
Output Current I
Output Current I
V

Output Voltage V

REF

V

Output Resistance R

REF

Analog Input Offset Voltage V

TH

OL

OH

O (SINK)

O (SOURCE)VOH

O (REF)

O (REF)

IO

Power Supply Rejection Ratio PSRR

VIN = GND or V
OE = GND - 7.5 15
fIN = 1KHz 8 10 -

I

No Load - - 0.03 V
No Load 4.97 - V
VOL = 0.4V 1 2.5 - mA

Gain Setting Amp
at 1KHz

- 4.75 - 5.25 V

- - 3.0 9.0 mA

- - 15 45 mW

- - - 1.5 V

- 3.5 - - V

DD

- 0.1 -

- 2.2 - 2.5 V

= 4.6V 0.4 0.8 - mA

- 2.4 - 2.8 V

- - 10 -

- - 25 - mV

-

60

-

Common Mode Rejection Ratio CMRR - 3.0V < VIN < 3.0V - 60 - dB
Open Loop Voltage Gain G

Gain Setting Amp at 1KHz - 65 - dB

V

Open Loop Unit Gain Bandwidth BW - - 1.5 - MHz
Analog Output Voltage Swing V
Acceptable Capacitive Load C

Acceptable Resistive Load R
Analog Input Common Mode

Voltage Range

O (P-P)

V

CM

RL = 100K - 4.5 - V
GS - 100 - pF

L

GS - 50 -

L

No Load

-

3.0

-

µA
µA

MΩ

KΩ

dB

KΩ
V

P-P

P-P