Samsung KS88P6232, KS88C6224, KS88C6216, KS88C6232 Datasheet

KS88C6216/C6224/C6232/P6232 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

SAM8 PRODUCT FAMILY

Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are:

— Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function

The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to specific interrupt levels.

KS88C6216/C6224/C6232/P6232 MICROCONTROLLERS

KS88C6216/C6224/C6232/P6232 single-chip 8-bit microcontrollers are based on the powerful SAM8 CPU architecture. The internal register file is logically expanded to increase the on-chip register space. KS88C6216/C6224/C6232/P6232 contain 16/32 K bytes of on-chip program ROM.

In line with Samsung's modular design approach, the following peripherals are integrated with the SAM8 core:

— Four programmable I/O ports (total 27 pins) — One 8-bit basic timer for oscillation stabilization

and watchdog functions

— One 8-bit general-purpose timer/counter with

selectable clock sources

— One 12-bit counter with selectable clock sources,

including Hsync or Csync input — One interval timer — PWM block with seven 8-bit PWM circuits — Sync processor block (for Vsync and Hsync I/O,

Csync input, and Clamp signal output) — DDC and normal Multi-master IIC-bus — 4-channel A/D converter (8-bit resolution)

KS88C6216/C6224/C6232/P6232 are a versatile microcontrollers which are ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, PWM, sync signal processing, A/D converter, and multi-master IIC-bus support with DDC. They are available in a 42pin SDIP or a 44-pin QFP package.

OTP

KS88C6216/C6224/C6232 microcontrollers are also available in OTP (One Time Programmable) version named, KS88P6232. KS88P6232 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of masked ROM. KS88P6232 is comparable to KS88C6216/C6224/C6232, both in function and pin configuration except its ROM size.

1-1

PRODUCT OVERVIEW KS88C6216/C6224/C6232/P6232

FEATURES

CPU

• SAM8 CPU core

Memory

• 16/24/32-Kbyte internal program memory (ROM)

• 464-byte general-purpose register area

Instruction Set

• 78 instructions

• IDLE and STOP instructions added for power-down modes

Instruction Execution Time

• Minimum 500 ns (with 12 MHz CPU clock)

Interrupts

• Ten interrupt sources

• Ten interrupt vectors

• Seven interrupt level

• Fast interrupt feature

Pulse Width Modulator (PWM)

• 8-bit PWM: 7-CH

Sync-Processor Block

• Vsync-I, Hsync-I, Csync-I input and Vsync-O, Hsync-O, Clamp-O output pins

• Pseudo sync signal output

• Auto SOG detection

• Auto Hsync polarity detection

DDC Multi-Master IIC-Bus 1-Ch

• Serial Peripheral Interface

• Support for Display Data Channel

(DDC1/DDC2B/DDC2Bi/DDC2B+)

Normal Multi-Master IIC-Bus 1-Ch

• Serial Peripheral Interface

A/D Converter

• 4-channel; 8-bit resolution

General I/O

• Four I/O Ports (total 27pins)

8-Bit Basic Timer

• Programmable timer for oscillation stabilization interval control or watchdog timer function

• Three selective internal clock frequencies

Timer/Counters

• One 8-bit Timer/Counter with several clock sources (Capture mode)

• One 12-bit Counter with H-sync and several clock sources

• One Interval Timer

Oscillator Frequency

• 8 MHz to 12 MHz crystal operation

• Internal Max. 12 MHz CPU clock

Operating Temperature Range

• – 40 °C to + 85 °C

Operating Voltage Range

• 4.0 V to 5.5 V

Package Types

• 42-pin SDIP, 44-pin QFP

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KS88C6216/C6224/C6232/P6232 PRODUCT OVERVIEW

BLOCK DIAGRAM

OUT

PWM0

•

PWM6

Vsync-I Hsync-I Csync-I

Vsync-O

Hsync-O

Clamp-O

MT0CAP

INT0-INT2

RESET

MAIN

OSC

8-BIT PWM

(7-CH)

Sync-

Processor

8-Bit

Counter

(Timer M0)

P0.0−P0.7/INT0−INT2

PORT 0

INTERNAL BUS

I/O PORT and INTERRUPT

CONTROL

SAM8 CPU

16/24/32-

Kbyte

ROM

P2.0−P2.7

PORT 2

464-Byte

VDD, AVREF V

, V

SS1

TEST

PORT 1

PORT3

ADC

Multi

Master

IIC-Bus

SS2

P1.0–P1.2

P3.0–P3.7

AD0−AD3

SCL1 SDA1

12-Blt

Counter

(Timer M1)

MT1CK

Interval

Timer

(Timer M2)

Multi Master IIC-Bus

and DDC1/2B/2Bi/2B+

SCL0 SDA0

Figure 1-1. Block Diagram

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PRODUCT OVERVIEW KS88C6216/C6224/C6232/P6232

PIN ASSIGNMENTS

P0.0/INT0 P0.1/INT1 P0.2/INT2

P0.3

P0.4/TM0CAP

P0.5/TM1CK

P0.6 P0.7

P1.0/SDA1

P1.1/SCL1

SS1

OUT

TEST

SDA0

SCL0

RESET

P1.2 P2.0/PWM0 P2.1/PWM1

1 2 3 4 5 6 7 8 9

KS88C6216

/C6224/C6232

11 12 13 14

15 16 17 18 19 20 21

42-SDIP

(Top View)

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

P3.7 P3.6 P3.5 P3.4 P3.3/AD3 P3.2/AD2 P3.1/AD1 P3.0/AD0 AVREF V

SS2

P2.7/Csync-I Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O P2.6/PWM6 P2.5/PWM5 P2.4/PWM4 P2.3/PWM3 P2.2/PWM2

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Figure 1-2. KS88C6216/C6224/C6232 42-SDIP Pin Assignment

KS88C6216/C6224/C6232/P6232 PRODUCT OVERVIEW

P0.4/TM0CAP

P0.3

P0.2/INT2

P0.5/TM1CK

P0.6 P0.7

P1.0/SDA1

P1.1/SCL1

VSS1

XOUT

XIN TEST SDA0

P0.1/INT1NCP0.0/INT0

4443424140393837363534

1 2 3

KS88C6216/C6224

4 5 6 7 8 9 10 11

/C6232/P6232

44-QFP

(Top View)

1213141516171819202122

P3.7

P3.6

P3.5

P3.4

P3.3/AD3

33 32 31 30 29 28 27 26 25 24 23

P3.2/AD2 P3.1/AD1 P3.0/AD0 AVREF VSS2 P2.7/Csync-I Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O

SCL0

RESET

P1.2

P2.0/PWM0

P2.1/PWM1

P2.2/PWM2

P2.3/PWM3

P2.4/PWM4

P2.5/PWM5

P2.6/PWM6

Figure 1-3. KS88C6224/C6232 44-QFP Pin Assignment

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PRODUCT OVERVIEW KS88C6216/C6224/C6232/P6232

PIN DESCRIPTIONS

Table 1-1. KS88C6216/C6224/C6232/P6232 Pin Descriptions

Names

P0.0 P0.1 P0.2 P0.3 P0.4

Type

Description

I/O General-purpose, 8-bit I/O port. Shared

functions include three external interrupt inputs and I/O for timer M0 and M1. Selective configuration of port 0 pins to

input or output mode is supported. P0.5 P0.6 P0.7

P1.0 P1.1 P1.2

I/O General-purpose, 3-bit I/O port. Selective

configuration is available for port 1 pins to

input, push-pull output, n-channel open-

drain mode, or IIC-bus clock and data I/O. P2.0

P2.1 P2.2 P2.3 P2.4

I/O General-purpose, 8-bit I/O port Selective

configuration of port 2 pins to input or

output mode is supported. The port 2 pin

circuits are designed to push-pull PWM

output and Csync signal input. P2.5 P2.6 P2.7

P3.0–P3.3 P3.4–P3.7

I/O General-purpose, 8-bit I/O port Selective

configuration port 3 pins to input or output

mode is supported. Multiplexed for

alternative use as A/D converter inputs

AD0–AD3. Hsync-I

Vsync-I Clamp-O Hsync-O Vsync-O SDA0 SCL0

VDD, V

SS1

AVREF, V

XIN, X

OUT

RESET

SS2

The pins are sync processor signal I/O, IIC-

bus clock, and data I/O.

O O

O I/O I/O

– Power pins

ADC power pins

– System clock I/O pins – 14, 13 –

I System reset pin B 18 –

TEST I Factory test pin input

0V:Normal operation,5V:Factory test mode

Circuit

Type

D-1 D-1 D-1 D-1 D-1 D-1 D-1 D-1

E-1 E-1 E-1

D-1 D-1 D-1 D-1 E-1 E-1 E-1 D-1

D-1

A A A A

A G-3 G-3

– –

SDIP Pin Numbers

1 2 3 4 5 6 7 8

9 10 19

20 21 22 23 24 25 26 32

35–38,

39–42

31 30 27 28 29 16 17

11, 12 34, 33

– 15 –

Shared

Functions

INT0 INT1 INT2

TM0CAP

TM1CK

SDA1 SCL1

PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6

Csync-I

AD0–AD3

–

1-6

KS88C6216/C6224/C6232/P6232 PRODUCT OVERVIEW

PIN CIRCUITS

Data or Other Function

Output

RESET

Data

Output

Figure 1-4. Pin Circuit Type A

280 K

Ω

Noise Filter

Output Disable

Digital Input TTL Input or ADC Input

Figure 1-6. Pin Circuit Type D-1

Figure 1-5. Pin Circuit Type B (RESET)

1-7

PRODUCT OVERVIEW KS88C6216/C6224/C6232/P6232

Typical

47-K

Ω

Pull-up Enable

Data

Output

Open drain

Output Disable

Input

Data

Open drain

Output Disable

Input

Figure 1-7. Pin Circuit Type E

Output

1-8

Figure 1-8. Pin Circuit Type E-1

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