Samsung K4S161622D-TC-L80, K4S161622D-TC-L70, K4S161622D-TC-L60, K4S161622D-TC-L55, K4S161622D-TC-L10 Datasheet

K4S161622D CMOS SDRAM

512K x 16Bit x 2 Banks Synchronous DRAM

GENERAL DESCRIPTIONFEATURES

• 3.3V power supply

• LVTTL compatible with multiplexed address

• Dual banks operation

• MRS cycle with address key programs

-. CAS Latency ( 2 & 3)

-. Burst Length (1, 2, 4, 8 & full page)

-. Burst Type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system
clock

• Burst Read Single-bit Write operation

• DQM for masking

• Auto & self refresh

• 15.6us refresh duty cycle (2K/32ms)

The K4S161622D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG′s high performance CMOS technol­ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem­ory system applications.

ORDERING INFORMATION

Part NO. MAX Freq. Interface Package

K4S161622D-TC/L55 183MHz
K4S161622D-TC/L60 166MHz

K4S161622D-TC/L70 143MHz
K4S161622D-TC/L80 125MHz
K4S161622D-TC/L10 100MHz

LVTTL

50

TSOP(II)

FUNCTIONAL BLOCK DIAGRAM

Bank Select

Refresh Counter

Row Buffer

Address Register

CLK

ADD

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

Data Input Register

Row Decoder Col. Buffer

512K x 16

512K x 16

Column Decoder

Latency & Burst Length

Programming Register

LCAS LWCBR

Timing Register

LWE

LDQM

Sense AMP

Output BufferI/O Control

DQi

CLK CKE CS RAS CAS WE L(U)DQM

Samsung Electronics reserves the right to

*

change products or specification without
notice.

K4S161622D CMOS SDRAM

PIN CONFIGURATION (TOP VIEW)

VDD

LDQM

A10/AP

PIN FUNCTION DESCRIPTION

DQ0
DQ1

VSSQ

DQ2
DQ3

VDDQ

DQ4
DQ5

VSSQ

DQ6
DQ7

VDDQ

WE
CAS
RAS

CS
BA

A0
A1
A2
A3

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
VSS

50PIN TSOP (II)

(400mil x 825mil)

(0.8 mm PIN PITCH)

Pin Name Input Function

CLK System Clock Active on the positive going edge to sample all inputs.
CS Chip Select

CKE Clock Enable

A0 ~ A10/AP Address

BA Bank Select Address

RAS Row Address Strobe

CAS Column Address Strobe

WE Write Enable

L(U)DQM Data Input/Output Mask

DQ0 ~ 15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.

VDDQ/VSSQ Data Output Power/Ground

N.C/RFU

No Connection/
Reserved for Future Use

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.

Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

This pin is recommended to be left No Connection on the device.

K4S161622D CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1 W
Short circuit current IOS 50 mA

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD, VDDQ 3.0 3.3 3.6 V 4
Input logic high votlage VIH 2.0 3.0 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current ILI -10 - 10 uA 3

Note :

:

1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. The VDD condition of K4S161622D-55/60 is 3.135V~3.6V.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Pin Symbol Min Max Unit

Clock CCLK 2 4 pF

RAS, CAS, WE, CS, CKE, L(U)DQM CIN 2 4 pF

Address CADD 2 4 pF

DQ0 ~ DQ15 COUT 3 5 pF

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter Symbol Value Unit

Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF
Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF

Note :

1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.

K4S161622D CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Parameter Symbol Test Condition

Operating Current
(One Bank Active)

Precharge Standby Cur­rent in power-down mode

Precharge Standby Current
in non power-down mode

Active Standby Current
in power-down mode

Active Standby Current
in non power-down mode
(One Bank Active)

Operating Current
(Burst Mode)

CAS

Latency

Burst Length =1

ICC1

ICC2P CKE≤VIL(max), tCC = 15ns 2
ICC2PS CKE & CLK≤VIL(max), tCC = ∞ 2

ICC2N

ICC2NS

ICC3P CKE≤VIL(max), tCC = 15ns 3
ICC3PS CKE & CLK≤VIL(max), tCC = ∞ 3

ICC3N

ICC3NS

ICC4

tRC≥tRC(min)
Io = 0 mA

CKE≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns

CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable

CKE≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns

CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable

Io = 0 mA
Page Burst 2Banks Activated
tCCD = 2CLKs

-55 -60 -70 -80 -10

3 120 115 105 95 85
2 - - 110 95 80

3 155 150 140 130 115

2 - - 125 115 100

Version

Unit Note

mA 2

mA

15

mA

5

mA

25 mA

15 mA

mA 2

Refresh Current ICC5 tRC≥tRC(min)

Self Refresh Current ICC6 CKE≤0.2V

Note :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open. Addresses are changed only one time during tcc(min).

3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).

4. K4S161622D-TC**

5. K4S161622D-TL**

3 105 100 90 90 80

mA 3

2 - - 100 90 80

1 mA 4

250 uA 5

K4S161622D CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V

Parameter Value Unit

Input levels (Vih/Vil) 2.4 / 0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr / tf = 1 / 1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2

3.3V

1200Ω

Output

870Ω

Note :

1. The DC/AC Test Output Load of K4S161622D-55/60/70 is 30pF.

2. The VDD condition of K4S161622D-55/60 is 3.135V~3.6V.

50pF

VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA

*2

*2

, TA = 0 to 70°C)

Output

Z0=50Ω

(Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit

Vtt=1.4V

50Ω

50pF

*1

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter Symbol

CAS Latency CL 3 2 3 2 3 2 3 2 3 2 CLK
CLK cycle time tCC(min) 5.5 - 6 - 7 8.7 8 10 10 12 ns
Row active to row active delay tRRD(min) 2 CLK 1
RAS to CAS delay tRCD(min) 3 - 3 - 3 2 3 2 2 2 CLK 1
Row precharge time tRP(min) 3 - 3 - 3 2 3 2 2 2 CLK 1

Row active time
Row cycle time

Last data in to row precharge tRDL(min) 1 CLK 2, 5
Last data in to new col.address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK
Mode Register Set cycle time tMRS(min) 2 CLK

Number of valid output data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table

CAS Latency=3 2
CAS Latency=2 1

tRAS(min) 7 - 7 - 7 5 6 5 5 4 CLK 1

tRAS(max) 100 us

tRC(min) 10 - 10 - 10 7 9 7 7 6 CLK 1

-55 -60 -70 -80 -10

Version

Unit Note

ea 4

K4S161622D CMOS SDRAM

Parameter Symbol

CLK cycle time tCC(min) 5.5 6 7 8 10 ns
Row active to row active delay tRRD(min) 11 12 14 16 20 ns
RAS to CAS delay tRCD(min) 16.5 18 17.4 20 20 ns
Row precharge time tRP(min) 16.5 18 17.4 20 20 ns

Row active time
Row cycle time tRC(min) 55 60 60.9 70 70 ns

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. Also, supported tRDL=2CLK for - 55/60 part which is distinguished by bucket code "J".
From the next generation, tRDL will be only 2CLK for every clock frequency.

tRAS(min) 38.5 42 43.5 48 48 ns

tRAS(max) 100 us

-55 -60 -70 -80 -10

Version

Unit

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter Symbol

CLK cycle time

CLK to valid
output delay

Output data tOH 2 - 2.5 - 2.5 - 2.5 - 2.5 - ns 2

CLK high pulse width

CLK low pulse width

Input setup time

Input hold time tSH 1 - 1 - 1 - 1 - 1 - ns 3
CLK to output in Low-Z tSLZ 1 - 1 - 1 - 1 - 1 - ns 2

CLK to output
in Hi-Z

CAS Latency=3
CAS Latency=2 - - 8.7 10 12
CAS Latency=3
CAS Latency=2 - - - - - 7.7 - 6 - 8

CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2

CAS Latency=3
CAS Latency=2 - - - - - 7.7 - 6 - 8

tCC

tSAC

tCH

tCL

tSS

tSHZ

-55 -60 -70 -80 -10

Min Max Min Max Min Max Min Max Min Max

5.5
1000

- 5 - 5.5 - 5.5 - 6 - 6

2

- -

2

1.5

- -

- 5 - 5.5 - 5.5 - 6 - 6

6

1000

2.5

-

2.5

-

-

1.5

-

7

1000

- 3 - 3 - 3.5 - ns 3

- 3 - 3 - 3.5 - ns 3

1.75

-

2.5

8

- 2 - 2.5 - ns 3

1000

10

1000 ns 1

Unit Note

ns 1, 2

ns

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

K4S161622D CMOS SDRAM

SIMPLIFIED TRUTH TABLE

COMMAND

Register Mode Register Set H X L L L L X OP CODE 1, 2

Auto Refresh

Refresh

Bank Active & Row Addr. H X L L H H X V Row Address
Read &

Column Address

Write &
Column Address

Burst Stop H X L H H L X X 6

Precharge

Clock Suspend or
Active Power Down

Precharge Power Down Mode

DQM H V X 7

No Operation Command H X

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

Self
Refresh

Auto Precharge Disable
Auto Precharge Enable H 4, 5
Auto Precharge Disable
Auto Precharge Enable H 4, 5

Bank Selection
Both Banks X H

Entry L 3

Exit L H

Entry H L

Exit L H X X X X X

Entry H L

Exit L H

CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~ A0 Note

H

H X L H L H X V

H X L H L L X V

H X L L H L X

H

L L L H X X

L H H H

H X X X 3

H X X X

L V V V

H X X X

L H H H

H X X X

L V V V

X

H X X X

L H H H

X X

X

X

X

X X

V L

Column

L

Address

(A0~A7)

Column

L

Address

(A0~A7)

X

X

X

3

3

4

4

Note :

1. OP Code : Operand Code
A0 ~ A10/AP, BA : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at both banks precharge state.

4. BA : Bank select address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A10/AP is "High" at row precharge, BA is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the assoiated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

K4S161622D CMOS SDRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address
Function

A8 A7 A6 A5 A4 A3 A2 A1 A0 BT = 0

0
0
1
1

A9

0
1

BA

RFU

Test Mode

0
1
0
1

Write Burst Length

A10/AP

RFU

Type

Mode Register Set

Reserved
Reserved
Reserved

Length

Burst

Single Bit

A9

W.B.L

0
0
0
0
1
1
1
1

A8 A7

TM

CAS Latency

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

A6 A5 A4 A3 A2 A1 A0

CAS Latency BT Burst Length

Latency

Reserved

­2
3

Reserved
Reserved
Reserved
Reserved

Burst Type

0

Sequential

1

Interleave

Full Page Length : x4 (1024), x8 (512), x16 (256)

Type

0
0
0
0
1
1
1
1

Burst Length

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

Reserved
Reserved
Reserved
Full Page

POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.

1
2
4
8

BT = 1

1
2
4

8
Reserved
Reserved
Reserved
Reserved

The device is now ready for normal operation.

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

2. RFU (Reserved for future use) should stay "0" during MRS cycle.

K4S161622D CMOS SDRAM

BURST SEQUENCE (BURST LENGTH = 4)

Initial Address

A1 A0

0
0
1
1

0
1
0
1

0
1
2
3

BURST SEQUENCE (BURST LENGTH = 8)

Initial Address

A1 A0A2

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

0

Sequential Interleave

1
2
3
0

Sequential Interleave

2

3

3

4

4

5

5

6

6

7

7

0

0

1

1

2

2
3
0
1

4

5

5

6

6

7

7

0

0

1

1

2

2

3

3

4

3
0
1
2

6

7

7

0

0

1

1

2

2

3

3

4

4

5

5

6

0
1
2
3

0
1
2
3
4
5
6
7

2

1

3

0

0

3

1

2

6

5

7

4

4

7

5

6

1
0
3
2

3
2
1
0
7
6
5
4

2
3
0
1

4

5

5

4

6

7

7

6

0

1

1

0

2

3

3

2

3
2
1
0

6

7

7

6

4

5

5

4

2

3

3

2

0

1

1

0

K4S161622D CMOS SDRAM

DEVICE OPERATIONS

CLOCK (CLK)

The clock input is used as the reference for all SDRAM opera­tions. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and ICC specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro­zen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + tSS" before the high going edge
of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.

ADDRESS INPUTS (A0 ~ A10/AP)

: In case x 4

The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 11 address input pins (A0 ~ A10/
AP). The 11 bit row addresses are latched along with RAS and
BA during bank activate command. The 10 bit column
addresses are latched along with CAS, WE and BA during read
or write command.

: In case x 8

The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 11 address input pins (A0 ~ A10/
AP). The 11 bit row addresses are latched along with RAS and
BA during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA during read or write
command.

: In case x 16

The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A0 ~ A10/
AP). The 11 bit row addresses are latched along with RAS and
BA during bank activate command. The 8 bit column addresses
are latched along with CAS, WE and BA during read or write
command.

BANK ADDRESS (BA)

: In case x 4

This SDRAM is organized as two independent banks of
2,097,152 words x 4 bits memory arrays. The BA input is latched
at the time of assertion of RAS and CAS to select the bank to be
used for the operation. The bank select BA is latched at bank
active, read, write, mode register set and precharge operations.

: In case x 8

This SDRAM is organized as two independent banks of
1,048,576 words x 8 bits memory arrays. The BA input is latched
at the time of assertion of RAS and CAS to select the bank to be
used for the operation. The bank select BA is latched at bank
active, read, write, mode register set and precharge operations.

: In case x 16

This SDRAM is organized as two independent banks of 524,288
words x 16 bits memory arrays. The BA input is latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. The bank select BA is latched at bank active,
read, write, mode register set and precharge operations.

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than sin­gle clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE and all the address inputs are ignored.

POWER-UP

SDRAMs must be powered up and initialized in a pre­defined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM=
"H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition
for a minimum of 200us.

3. Issue precharge commands for both banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode reg­ ister.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

K4S161622D CMOS SDRAM

DEVICE OPERATIONS (Continued)

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A0 ~ A10/AP and BA in the same cycle as CS,
RAS, CAS and WE going low is the data written in the mode
register. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed
using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on the fields of
functions. The burst length field uses A0 ~ A2, burst type uses
A3, CAS latency (read latency from column address) uses A4 ~
A6, vendor specific options or test mode use A7 ~ A8, A10/AP
and BA. The write burst length is programmed using A9. A7 ~ A8,
A10/AP, BA must be set to low for normal SDRAM operation.
Refer to the table for specific codes for various burst length,
burst type and CAS latencies.

BANK ACTIVATE

The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank address, a row access is initiated. The read or write
operation can occur after a time delay of tRCD(min) from the time
of bank activation. tRCD is an internal timing parameter of
SDRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing tRCD(min) with cycle time of the clock and then rounding
off the result to the next higher integer. The SDRAM has two
internal banks in the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of two banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high, requiring some time for
power supplies to recover before the other bank can be sensed
reliably. tRRD(min) specifies the minimum time required between
activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to
tRCD specification. The minimum time required for the bank to be

active to initiate sensing and restoring the complete row of
dynamic cells is determined by tRAS(min). Every SDRAM bank
activate command must satisfy tRAS(min) specification before a
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by tRAS(max). The number of cycles for both tRAS(min) and
tRAS(max) can be calculated similar to tRCD specification.

BURST READ

The burst read command is used to access burst of data on con­secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least tRCD(min) before the burst read com­mand is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read com­mand is determined by the mode register which is already pro­grammed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of out­puts from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid at every page burst length.

BURST WRITE

The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing can be com­pleted yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank tRDL after the
last data input to be written into the active row. See DQM
OPERATION also.

K4S161622D CMOS SDRAM

DEVICE OPERATIONS (Continued)

DQM OPERATION

The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature
of the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst write is
not required. Please refer to DQM timing diagram also.

PRECHARGE

The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A10/AP with valid BA of the
bank to be precharged. The precharge command can be
asserted anytime after tRAS(min) is satisfied from the bank active
command in the desired bank. tRP is defined as the minimum
number of clock cycles required to complete row precharge is
calculated by dividing tRP with clock cycle time and rounding up
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore, each
bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when both banks are in idle state.

AUTO PRECHARGE

The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A10/AP. If
burst read or burst write by asserting high on A10/AP, the bank is
left active until a new command is asserted. Once auto
precahrge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.

BOTH BANKS PRECHARGE

Both banks can be precharged at the same time by using pre­charge all command. Asserting low on CS, RAS, and WE with
high on A10/AP after both banks have satisfied tRAS(min)
requirement, performs precharge on both banks. At the end of
tRP after performing precharge to all the banks, both banks are
in idle state.

AUTO REFRESH

The storage cells of SDRAM need to be refreshed every 32ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,
RAS and CAS with high on CKE and WE. The auto refresh com­mand can only be asserted with both banks being in idle state
and the device is not in power down mode (CKE is high in the
previous cycle). The time required to complete the auto refresh
operation is specified by tRFC(min). The minimum number of
clock cycles required can be calculated by driving tRFC with
clock cycle time and them rounding up to the next higher integer.
The auto refresh command must be followed by NOP's until the
auto refresh operation is completed. Both banks will be in the
idle state at the end of auto refresh operation. The auto refresh
is the preferred refresh mode when the SDRAM is being used
for normal data transactions. The auto refresh cycle can be per­formed once in 15.6us or a burst of 2048 auto refresh cycles
once in 32ms.

SELF REFRESH

The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from both banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's for
a minimum time of tRFC before the SDRAM reaches idle state to
begin normal operation. If the system uses burst auto refresh
during normal operation, it is recommended to use burst 2048
auto refresh cycles immediately after exiting in self refresh
mode.

K4S161622D CMOS SDRAM

BASIC FEATURE AND FUNCTION DESCRIPTIONS

1. CLOCK Suspend

1) Clock Suspended During Write (BL=4)

CLK

CMD

CKE

Internal

CKE

DQ(CL2)
DQ(CL3)

2. DQM Operation

1) Write Mask (BL=4)

CLK

CMD
DQM

WR

Masked by CKE

D0 D1 D2 D3
D0 D1 D2 D3

Not Written

WR

Masked by DQM

2) Clock Suspended During Read (BL=4)

RD

Masked by CKE

D0

Q0 Q1 Q2

Q0 Q1

Suspended Dout

2) Read Mask (BL=4)

RD

Masked by DQM

Q3
Q2 Q3

DQ(CL2)
DQ(CL3)

3) DQM with Clock Suspended (Full Page Read)
CLK

CMD

CKE

DQM

DQ(CL2)
DQ(CL3)

*Note : 1. CKE to CLK disable/enable = 1CLK.

2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"

3. DQM masks both data-in and data-out.

D0 D1 D3
D0 D1 D3

DQM to Data-in Mask = 0 DQM to Data-out Mask = 2

RD

Note 2

Q0 Q4 Q7 Q8Q2

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Q0 Q2 Q3

Hi-Z

Hi-Z

Q3 Q6 Q7Q1

Hi-Z

Q6
Q5

Q1

Q2 Q3