Samsung K4S160822DT-G-FH, K4S160822DT-G-F8, K4S160822DT-G-F7, K4S160822DT-G-F10, K4S160822DT-G-FL Datasheet

K4S160822D CMOS SDRAM

2Mx8 SDRAM

1M x 8bit x 2 Banks

Synchronous DRAM

LVTTL

Revision 1.0

October 1999

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

Revision History

Revision 1.0 (October 1999)

- 2 -

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

1M x 8Bit x 2 Banks Synchronous DRAM

GENERAL DESCRIPTIONFEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Dual banks operation

• MRS cycle with address key programs

-. CAS latency ( 2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system
clock

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 15.6us refresh duty cycle(2K/32ms)

FUNCTIONAL BLOCK DIAGRAM

The K4S160822D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 1,048,576 words by 8 bits,
fabricated with SAMSUNG′s high performance CMOS technol­ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem­ory system applications.

ORDERING INFORMATION

Part No. Max Freq. Interface Package

K4S160822DT-G/F7 143MHz
K4S160822DT-G/F8 125MHz
K4S160822DT-G/FH 100MHz
K4S160822DT-G/FL 100MHz
K4S160822DT-G/F10 100MHz

LVTTL44TSOP(II)

CLK

ADD

Data Input Register

Bank Select

Refresh Counter

Row Buffer

Address Register

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

CLK CKE CS RAS CAS WE DQM

Row Decoder Col. Buffer

Latency & Burst Length

Programming Register

LCAS LWCBR

Timing Register

1M x 8

1M x 8

Column Decoder

LWE

LDQM

Sense AMP

Samsung Electronics reserves the right to

*

change products or specification without
notice.

Output BufferI/O Control

DQi

- 3 -

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

PIN CONFIGURATION (Top view)

VDD

DQ0

VSSQ

DQ1

VDDQ

DQ2

VSSQ

DQ3

VDDQ

N.C
N.C

WE
CAS
RAS

CS
BA

A10/AP

A0
A1
A2
A3

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
N.C/RFU
N.C
DQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
VSS

44Pin TSOP (II)

(400mil x 725mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Pin Name Input Function

CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select

CKE Clock enable

A0 ~ A10/AP Address

BA Bank select address

RAS Row address strobe

CAS Column address strobe

WE Write enable

DQM Data input/output mask

DQ0 ~ 7 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.

VDDQ/VSSQ Data output power/ground

N.C/RFU

No connection
/reserved for future use

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.

Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA8

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

This pin is recommended to be left No Connection on the device.

- 4 -

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1 W
Short circuit current IOS 50 mA

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current (Inputs) ILI -10 - 10 uA 3
input leakage current (I/O pins) ILO -10 - 10 uA 3,4

Notes :

1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

Pin Symbol Min Max Unit

Clock CCLK 2.5 4.0 pF
RAS, CAS, WE, CS, CKE, DQM CIN 2.5 5.0 pF
Address CADD 2.5 5.0 pF
DQ0 ~ DQ7 COUT 4.0 6.5 pF

- 5 -

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Parameter Symbol Test Condition

Operating current
(One bank active)

Precharge standby current in
power-down mode

Precharge standby current in
non power-down mode

Active standby current in
power-down mode

Active standby current in
non power-down mode
(One bank active)

Operating current
(Burst mode)

Refresh current ICC5 tRC ≥ tRC(min) 90 80 mA 2

Self refresh current ICC6 CKE ≤ 0.2V

ICC1

ICC2P CKE ≤ VIL(max), tCC = 15ns 2

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2

ICC2N

ICC2NS

ICC3P CKE ≤ VIL(max), tCC = 15ns 3

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 3

ICC3N

ICC3NS

ICC4

Burst length = 1
tRC ≥ tRC(min)
Io = 0 mA

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable

Io = 0 mA
Page burst
2Banks activated
tCCD = 2CLKs

CAS

Latency

-7 -8 -H -L -10

100 90 85 85 75 mA 1

3 120 110 95 95 95

2 95 85 95 85 85

Version

15

5

25 mA

15 mA

1 mA 3

250 uA 4

Unit Note

mA

mA

mA

mA 1

Notes :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open.

3. Refresh period is 32ms.

4. K4S160822DT-G**

5. K4S160822DT-F**

- 6 -

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter Value Unit

AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2

Output

870Ω

3.3V

1200Ω

50pF

VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA

Output

Z0 = 50Ω

(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit

Vtt = 1.4V

50Ω

50pF

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter Symbol

Row active to row active delay tRRD(min) 14 16 20 20 20 ns 1
RAS to CAS delay tRCD(min) 20 20 20 20 26 ns 1
Row precharge time tRP(min) 20 20 20 20 26 ns 1

Row active time

Row cycle time tRC(min) 68 68 70 70 80 ns 1
Last data in to row precharge tRDL(min) 7 8 10 10 12 ns 2
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3

Number of valid output data

CAS latency=3 2
CAS latency=2 1

tRAS(min) 48 48 50 50 50 ns 1

tRAS(max) 100 us

-7 -8 -H -L -10

Version

Unit Note

ea 4

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

- 7 -

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter Symbol

CLK cycle time

CLK to valid
output delay

Output data
hold time

CLK high pulse width tCH 3 3 3 3 3.5 ns 3
CLK low pulse width tCL 3 3 3 3 3.5 ns 3
Input setup time tSS 2 2 2 2 2.5 ns 3
Input hold time tSH 1 1 1 1 1 ns 3
CLK to output in Low-Z tSLZ 1 1 1 1 1 ns 2

CLK to output
in Hi-Z

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

CAS latency=3
CAS latency=2 10 12 10 12 13
CAS latency=3
CAS latency=2 6 6 6 7 8
CAS latency=3
CAS latency=2 3 3 3 3 3

CAS latency=3
CAS latency=2 6 6 6 7 8

tCC

tSAC

tOH

tSHZ

-7 -8 -H -L -10

Min Max Min Max Min Max Min Max Min Max

7

1000

3 3 3 3 3

8

6 6 6 6 7

6 6 6 6 7

1000

10

1000

10

1000

10

1000 ns 1

Unit Note

ns 1,2

ns 2

ns

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter Symbol Condition Min Typ Max Unit Notes

Output rise time trh

Output fall time tfh

Output rise time trh

Output fall time tfh

Notes :

1. Output rise and fall time must be guaranteed across VDD and process range.

2. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.

3. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.

4. Measured into 50pF only, use these values to characterize to.

5. All measurements done with respect to VSS.

Measure in linear
region : 1.2V ~1.8V

Measure in linear
region : 1.2V ~1.8V

Measure in linear
region : 1.2V ~1.8V

Measure in linear
region : 1.2V ~1.8V

1.37 4.37 Volts/ns 4

1.30 3.8 Volts/ns 4

2.8 3.9 5.6 Volts/ns 1,2,3

2.0 2.9 5.0 Volts/ns 1,2,3

- 8 -

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

IBIS SPECIFICATION

IOH Characteristics (Pull-up)

Voltage

(V) I (mA) I (mA) I (mA)

3.45 -2.4

3.3 -27.3

3.0 0.0 -74.1 -0.7

2.6 -21.1 -129.2 -7.5

2.4 -34.1 -153.3 -13.3

2.0 -58.7 -197.0 -27.5

1.8 -67.3 -226.2 -35.5

1.65 -73.0 -248.0 -41.1

1.5 -77.9 -269.7 -47.9

1.4 -80.8 -284.3 -52.4

1.0 -88.6 -344.5 -72.5

0.0 -93.0 -502.4 -93.0

100MHz

Min

100MHz

Max

66MHz

Min

66MHz and 100MHz Pull-up

0 30.5 1 1.5 2 2.5 3.5

0

-100

-200

-300

mA

-400

-500

-600

Voltage

IOH Min (100MHz)
IOH Min (66MHz)
IOH Max (66 and 100MHz)

IOL Characteristics (Pull-down)

Voltage

(V) I (mA) I (mA) I (mA)

0.0 0.0 0.0 0.0

0.4 27.5 70.2 17.7

0.65 41.8 107.5 26.9

0.85 51.6 133.8 33.3

1.0 58.0 151.2 37.6

1.4 70.7 187.7 46.6

1.5 72.9 194.4 48.0

1.65 75.4 202.5 49.5

1.8 77.0 208.6 50.7

1.95 77.6 212.0 51.5

3.0 80.3 219.6 54.2

3.45 81.4 222.6 54.9

100MHz

Min

100MHz

Max

66MHz

Min

66MHz and 100MHz Pull-down

250

200

150

mA

100

50

0

0 30.5 1 1.5 2 2.5 3.5

Voltage

IOL Min (100MHz)
IOL Min (66MHz)
IOL Max (100MHz)

- 9 -

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

VDD Clamp @ CLK, CKE, CS, DQM & DQ

VDD (V) I (mA)

0.0 0.0

0.2 0.0

0.4 0.0

0.6 0.0

0.7 0.0

0.8 0.0

0.9 0.0

1.0 0.23

1.2 1.34

1.4 3.02

1.6 5.06

1.8 7.35

2.0 9.83

2.2 12.48

2.4 15.30

2.6 18.31

VSS Clamp @ CLK, CKE, CS, DQM & DQ

VSS (V) I (mA)

-2.6 -57.23

-2.4 -45.77

-2.2 -38.26

-2.0 -31.22

-1.8 -24.58

-1.6 -18.37

-1.4 -12.56

-1.2 -7.57

-1.0 -3.37

-0.9 -1.75

-0.8 -0.58

-0.7 -0.05

-0.6 0.0

-0.4 0.0

-0.2 0.0

0.0 0.0

Minimum VDD clamp characteristic

(Referenced to VDD)

20

15

10

mA

5

0

0 31 2

Minimum VSS clamp current

-3 0-2 -1

0

-10

-20

-30

mA

-40

-50

-60

Voltage

I (mA)

- 10

Voltage

I (mA)

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE

K4S160822DT-7

Frequency

143MHz (7.0ns) 3 10 7 3 2 3 1 1 1
125MHz (8.0ns) 3 9 6 3 2 3 1 1 1

100MHz (10.0ns) 2 7 5 2 2 2 1 1 1

83MHz (12.0ns) 2 6 4 2 2 2 1 1 1
75MHz (13.0ns) 2 6 4 2 2 2 1 1 1
66MHz (15.0ns) 2 5 4 2 1 2 1 1 1

CAS

Latency

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

68ns 48ns 20ns 14ns 20ns 7ns 7ns 7ns

(Unit : Number of clock)

K4S160822DT-8

Frequency

125MHz (8.0ns) 3 9 6 3 2 3 1 1 1

100MHz (10.0ns) 3 7 5 2 2 2 1 1 1

83MHz (12.0ns) 2 6 4 2 2 2 1 1 1
75MHz (13.0ns) 2 6 4 2 2 2 1 1 1
66MHz (15.0ns) 2 5 4 2 2 2 1 1 1

CAS

Latency

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

68ns 48ns 20ns 16ns 20ns 8ns 8ns 8ns

K4S160822DT-H

Frequency

100MHz (10.0ns) 2 7 5 2 2 2 1 1 1

83MHz (12.0ns) 2 6 5 2 2 2 1 1 1
75MHz (13.0ns) 2 6 4 2 2 2 1 1 1
66MHz (15.0ns) 2 5 4 2 2 2 1 1 1
60MHz (16.7ns) 2 5 3 2 2 2 1 1 1

CAS

Latency

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns

K4S160822DT-L

Frequency

100MHz (10.0ns) 3 7 5 2 2 2 1 1 1

83MHz (12.0ns) 2 6 5 2 2 2 1 1 1
75MHz (13.0ns) 2 6 4 2 2 2 1 1 1
66MHz (15.0ns) 2 5 4 2 2 2 1 1 1
60MHz (16.7ns) 2 5 3 2 2 2 1 1 1

CAS

Latency

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns

(Unit : Number of clock)

(Unit : Number of clock)

(Unit : Number of clock)

(Unit : Number of clock)

K4S160822DT-10

Frequency

100MHz (10.0ns) 3 8 5 3 2 3 1 1 2

83MHz (12.0ns) 3 7 5 3 2 3 1 1 1
75MHz (13.0ns) 2 7 4 2 2 2 1 1 1
66MHz (15.0ns) 2 6 4 2 2 2 1 1 1
60MHz (16.7ns) 2 5 3 2 2 2 1 1 1

CAS

Latency

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

80ns 50ns 26ns 20ns 26ns 10ns 10ns 12ns

- 11

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

SIMPLIFIED TRUTH TABLE

COMMAND

Register Mode Register Set H X L L L L X OP CODE 1, 2

Auto Refresh

Refresh

Bank Active & Row Addr. H X L L H H X V Row Address
Read &

Column Address

Write &
Column Address

Burst Stop H X L H H L X X 6

Precharge

Clock Suspend or
Active Power Down

Precharge Power Down Mode

DQM H V X 7

No Operation Command H X

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

Self
Refresh

Auto Precharge Disable
Auto Precharge Enable H 4, 5
Auto Precharge Disable
Auto Precharge Enable H 4, 5

Bank Selection
Both Banks X H

Entry L 3

Exit L H

Entry H L

Exit L H X X X X X

Entry H L

Exit L H

CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~ A0 Note

H

H X L H L H X V

H X L H L L X V

H X L L H L X

H

L L L H X X

L H H H
H X X X 3

H X X X
L V V V

H X X X
L H H H
H X X X
L V V V

X

H X X X
L H H H

X X

X

X

X

X X

V L

Column

L

Address

(A0~A8)

Column

L

Address

(A0~A8)

X

X

X

3

3

4

4

Note :

1. OP Code : Operand Code
A0 ~ A10/AP, BA : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at both banks precharge state.

4. BA : Bank select address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A10/AP is "High" at row precharge, BA is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the assoiated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

- 12

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address
Function

BA

RFU

A10/AP

RFU

A9

W.B.L

A8 A7

TM

A6 A5 A4 A3 A2 A1 A0

CAS Latency BT Burst Length

Test Mode

A8 A7 A6 A5 A4 A3 A2 A1 A0 BT = 0

0

0

0

1

1

0

1

1

Write Burst Length

A9

0
1

Type

Mode Register Set

Reserved
Reserved
Reserved

Length

Burst

Single Bit

0
0
0
0
1
1
1
1

CAS Latency

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

Latency

Reserved

­2
3

Reserved
Reserved
Reserved
Reserved

Burst Type

0

Sequential

1

Interleave

Burst Length

Type

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1

1

Full Page Length : x4 (1024), x8 (512), x16 (256)

0
1
0
1

Reserved

0

Reserved

1

Reserved

0

Full Page

1

1
2
4
8

POWER UP SEQUENCE

1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

2. RFU (Reserved for future use) should stay "0" during MRS cycle.

BT = 1

1
2
4

8
Reserved
Reserved
Reserved
Reserved

- 13

Rev. 1.0 (Oct. 1999)

K4S160822D CMOS SDRAM

BURST SEQUENCE (BURST LENGTH = 4)

Initial Address

A1 A0

0
0
1
1

0
1
0
1

0
1
2
3

BURST SEQUENCE (BURST LENGTH = 8)

Initial Address

A1 A0A2

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0

0

1

1

1

2

0

2

3

1

3

4

0

4

5

1

5

6

0

6

7

1

7

0

Sequential Interleave

1
2
3
0

Sequential Interleave

2

3

3

4

4

5

5

6

6

7

7

0

0

1

1

2

2
3
0
1

4

5

5

6

6

7

7

0

0

1

1

2

2

3

3

4

3
0
1
2

6

7

7

0

0

1

1

2

2

3

3

4

4

5

5

6

0
1
2
3

0
1
2
3
4
5
6
7

2

1

3

0

0

3

1

2

6

5

7

4

4

7

5

6

1
0
3
2

3
2
1
0
7
6
5
4

2
3
0
1

4

5

5

4

6

7

7

6

0

1

1

0

2

3

3

2

3
2
1
0

6

7

7

6

4

5

5

4

2

3

3

2

0

1

1

0

- 14

Rev. 1.0 (Oct. 1999)