Philips PCF8582C-2 User Manual

1. Description

PCF8582C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Rev. 04 — 25 October 2004 Product data

The PCF8582C-2 is a ﬂoating gate Electrically Erasable Programmable Read Only Memory (EEPROM) with 2 kbits (256 × 8-bit) non-volatile storage. By using an internal redundant storage code, it is fault tolerant to single bit errors. This feature dramatically increases the reliability compared to conventional EEPROMs. Power consumption is lowdue to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier.

Data bytes are received and transmitted via the serial I2C-bus. Up to eight PCF8582C-2 devices may be connected to the I2C-bus. Chip select is accomplished by three address inputs (A0, A1 and A2).

Timing of the E/W cycle is carried out internally, thus no external components are required. Programming Time Control (PTC), Pin 7, must be connected to either V or left open-circuit. There is an option of using an external clock for timing the length of an E/W cycle.

2. Features

■ Low power CMOS:

◆ 2.0 mA maximum operating current

◆ maximum standby current 10 µA (at 6.0 V), typical 4 µA

■ Non-volatile storage of 2 kbits organized as 256 × 8-bit

■ Single supply with full operation down to 2.5 V

■ On-chip voltage multiplier

■ Serial input/output I2C-bus

■ Write operations:

◆ byte write mode

◆ 8-byte page write mode (minimizes total write time per byte)

■ Read operations:

◆ sequential read

◆ random read

■ Internal timer for writing (no external components)

■ Internal power-on reset

■ 0 kHz to 100 kHz clock frequency

■ High reliability by using a redundant storage code

■ Endurance: 1,000,000 Erase/Write (E/W) cycles at T

■ 10 years non-volatile data retention time

amb

=22°C

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■ Pin and address compatible to: PCF8570, PCF8571, PCF8572, PCA8581 and

PCF85102

■ Pin compatible with a different address to PCF85103

■ ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

■ Offered in DIP8 and SO8 packages.

3. Quick reference data

Table 1: Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

DDR

DDW

DD(stb)

PCF8582C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

supply voltage 2.5 - 6.0 V supply current read f

supply current E/W f

standby supply current VDD= 2.5 V - - 3.5 µA

= 100 kHz

SCL

= 2.5 V - - 60 µA

=6V - - 200 µA

= 100 kHz

SCL

= 2.5 V - - 0.6 mA

= 6 V - - 2.0 mA

=6V - - 10 µA

4. Ordering information

Table 2: Ordering information

Type number Package

PCF8582C-2P/03 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF8582C-2T/03 SO8 plastic small outline package 8 leads (straight);

4.1 Ordering options

Table 3: Ordering options

Type number Topside mark

PCF8582C-2P/03 PCF8582C-2 PCF8582C-2T/03 8582C-2

Name Description Version

SOT96-1

body width 3.9 mm

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xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

PCF8582C-2

SCL

SDA

INPUT

FILTER

C-BUS CONTROL LOGIC

5. Block diagram

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ADDRESS

SWITCH

SHIFT

BYTE

COUNTER

BYTE

LATCH

(8 bytes)

ADDRESS

POINTER

ADDRESS

HIGH

EEPROM

CONTROL

SEQUENCER

DIVIDER

( 128)

256 × 8-bit CMOS EEPROM with I

TEST MODE DECODER

POWER-ON-RESET

TIMER

( 16)

OSCILLATOR

002aaa090

PTC

PCF8582C-2

C-bus interface

Fig 1. Block diagram.

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6. Pinning information

6.1 Pinning

PCF8582C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

PCF8582C-2

Fig 2. Pin conﬁguration.

6.2 Pin description

Table 4: Pin description

Symbol Pin Description

A0 1 address input 0 A1 2 address input 1 A2 3 address input 2 V

SDA 5 serial data input/output (I SCL 6 serial clock input (I PTC 7 programming time control output V

4 negative supply voltage

8 positive supply voltage

MGD928

8 7 6 5

C-bus)

DD PTC SCL

SDA

C-bus)

7. Device addressing

Table 5: Device address code

Selection Device code Chip Enable R/W

Bit b7

[1]

Device 1 0 1 0 A2 A1 A0 R/

[1] The Most Signiﬁcant Bit (MSB) ‘b7’ is sent ﬁrst.

A2, A1, A0 are hardware selectable pins. A system could have up to eight PCF8582C-2 devices on the same I2C-bus,

equivalent to a 16 kbit EEPROM or 8 pages of 256 bytes of memory. The eight addresses are deﬁned by the state of the A0, A1, A2 inputs (logic level ‘1’

when connected to VDD, logic level ‘0’ when connected to GND). Figure 3 shows the various address combinations.

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b6 b5 b4 b3 b2 b1 b0

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I2C-BUS

PCF8582C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

PCF8582C-2 DEVICE 1

256-BYTE PAGE

PCF8582C-2 DEVICE 2

256-BYTE PAGE

PCF8582C-2 DEVICE 3

256-BYTE PAGE

PCF8582C-2 DEVICE 4

256-BYTE PAGE

PCF8582C-2 DEVICE 5

256-BYTE PAGE

Fig 3. Device addressing.

PCF8582C-2 DEVICE 6

256-BYTE PAGE

PCF8582C-2 DEVICE 7

256-BYTE PAGE

PCF8582C-2 DEVICE 8

256-BYTE PAGE

002aaa246

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8. Functional description

8.1 I2C-bus protocol

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The serial bus consists of two bidirectional lines; one for data signals (SDA), and one for clock signals (SCL).

Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been deﬁned:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is

HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals.

8.1.1 Bus conditions

The following bus conditions have been deﬁned:

PCF8582C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

Bus not busy — Both data and clock lines remain HIGH. Start data transfer — A change in the state of the data line, from HIGH-to-LOW,

while the clock is HIGH, deﬁnes the START condition. Stop data transfer — A change in the state of the data line, from LOW-to-HIGH,

while the clock is HIGH, deﬁnes the STOP condition. Data valid — The state of the data line represents valid data when, after a START

condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.

8.1.2 Data transfer

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes, transferred between the START and STOP conditions is limited to 7 bytes in the E/W mode and 8 bytes in the Page E/W mode.

Data transfer is unlimited in the read mode. The information is transmitted in bytes and each receiver acknowledges with a ninth bit.

Within the I2C-bus speciﬁcations, a standard-speed mode (100 kHz clock rate) and a fast speed mode (400 kHz clock rate) are deﬁned. The PCF8582C-2 operates in only the standard-speed mode.

By deﬁnition, a device that sends a signal is called a ‘transmitter’, and the device which receives the signal is called a ‘receiver’. The device which controls the signal is called the ‘master’. The devices that are controlled by the master are called ‘slaves’.

Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put on the bus by the transmitter. The master generates an extra acknowledge related clock pulse. The slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte.

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The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse.

Set-up and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master generation of the STOP condition.

8.1.3 Device addressing

Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCF8582C-2 is shown in Figure 4. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable pins and they must be connected to either VDD or VSS.

PCF8582C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

1010A2A1A0R/W

Fig 4. Slave address.

The last bit of the slave address deﬁnes the operation to be performed. When set to logic 1, a read operation is selected, while a logic 0 selects a write operation.

8.1.4 Write operations

Byte/word write: For a write operation, the PCF8582C-2 requires a second address

ﬁeld. This address ﬁeld is a word address providing access to the 256 words of memory. Upon receipt of the word address, the PCF8582C-2 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. Word address is automatically incremented. The master can now terminate the transfer by generating a STOP condition or transmit up to six more bytes of data and then terminate by generating a STOP condition.

After this STOP condition, the E/W cycle starts and the bus is free for another transmission. Its duration is 10 ms per byte.

During the E/W cycle the slave receiver does not send an acknowledge bit if addressed via the I2C-bus.

FIXED

HARDWARE

SELECTABLE

002aaa173

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