Philips PCF8579H-F1, PCF8579U, PCF8579U-10, PCF8579U-12, PCF8579U-2-F1 Datasheet

DATA SH EET

Product speciﬁcation Supersedes data of 1996 Oct 25 File under Integrated Circuits, IC12

1997 Apr 01

INTEGRATED CIRCUITS

PCF8579

LCD column driver for dot matrix graphic displays

1997 Apr 01 2

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

CONTENTS

1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION

7.1 Multiplexed LCD bias generation

7.2 Power-on reset

7.3 Timing generator

7.4 Column drivers

7.5 Display RAM

7.6 Data pointer

7.7 Subaddress counter

7.8 I2C-bus controller

7.9 Input filters

7.10 RAM access

7.11 Display control

7.12 TEST pin 8I

2

C-BUS PROTOCOL

8.1 Command decoder 9 CHARACTERISTICS OF THE I2C-BUS

9.1 Bit transfer

9.2 Start and stop conditions

9.3 System configuration

9.4 Acknowledge

10 LIMITING VALUES 11 HANDLING 12 DC CHARACTERISTICS 13 AC CHARACTERISTICS 14 APPLICATION INFORMATION 15 CHIP DIMENSIONS AND BONDING PAD

LOCATIONS 16 CHIP-ON GLASS INFORMATION 17 PACKAGE OUTLINES 18 SOLDERING

18.1 Introduction

18.2 Reflow soldering

18.3 Wave soldering

18.3.1 LQFP

18.3.2 VSO

18.3.3 Method (LQFP and VSO)

18.4 Repairing soldered joints 19 DEFINITIONS 20 LIFE SUPPORT APPLICATIONS 21 PURCHASE OF PHILIPS I2C COMPONENTS

1997 Apr 01 3

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

1 FEATURES

• LCD column driver

• Used in conjunction with the PCF8578, this device forms

part of a chip set capable of driving up to 40960 dots

• 40 column outputs

• Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32

• Externally selectable bias configuration, 5 or 6 levels

• Easily cascadable for large applications (up to

32 devices)

• 1280-bit RAM for display data storage

• Display memory bank switching

• Auto-incremented data loading across hardware

subaddress boundaries (with PCF8578)

• Power-on reset blanks display

• Logic voltage supply range 2.5 to 6 V

• Maximum LCD supply voltage 9 V

• Low power consumption

• I

2

C-bus interface

• TTL/CMOS compatible

• Compatible with most microcontrollers

• Optimized pinning for single plane wiring in multiple

device applications (with PCF8578)

• Space saving 56-lead plastic mini-pack and 64-pin plastic low profile quad flat package

• Compatible with chip-on-glass technology

• I2C-bus address: 011110 SA0.

2 APPLICATIONS

• Automotive information systems

• Telecommunication systems

• Point-of-sale terminals

• Computer terminals

• Instrumentation.

3 GENERAL DESCRIPTION

The PCF8579 is a low power CMOS LCD column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device has 40 outputs and can drive 32 × 40 dots in a 32 row multiplexed LCD. Up to 16 PCF8579s can be cascaded and up to 32 devices may be used on the same I

2

C-bus (using the two slave addresses). The device is optimized for use with the PCF8578 LCD row/column driver. Together these two devices form a general purpose LCD dot matrix driver chip set, capable of driving displays of up to 40960 dots. The PCF8579 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). To allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to VDD. Communication overheads are minimized by a display RAM with auto-incremented addressing and display bank switching.

4 ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF8579T VSO56 plastic very small outline package; 56 leads SOT190 PCF8579U7 − chip with bumps on tape − PCF8579H LQFP64 plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2

1997 Apr 01 4

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

5 BLOCK DIAGRAM

Fig.1 Block diagram.

C39 - C0

17 - 56 (30 to 33, 35 to 64, 1 to 6)

MSA919

V

DD

PCF8579

V

LCD

V

3

V

4

12 (20) 14 (22) 15 (23) 16 (24)

6 (12)

OUTPUT

CONTROLLER

COLUMN DRIVERS

(1)

Y DECODER

AND SENSING

AMPLIFIERS

32 x 40 BIT

DISPLAY RAM

X DECODER

DISPLAY

DECODER

RAM DATA POINTER

SUBADDRESS

COUNTER

TIMING

GENERATOR

I C-BUS

CONTROLLER

2

INPUT

FILTERS

COMMAND

DECODER

POWER-ON

RESET

TEST

2 (8) 1 (7)

SCL

SDA

n.c.

SA0

(15, 19, 21, 25 to 29, 34) 13

7 (13)

(10) 4

(9) 3

CLK

SYNC

YX

8 (14) 9 (16)

10 (17) 11 (18)

A3 A2 A1 A0

5 (11)

V

SS

(1) Operates at LCD voltage levels, all other blocks operate at logic levels. The pin numbers given in parenthesis refer to the LQFP64 package.

1997 Apr 01 5

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

6 PINNING

Note

1. Do not connect, this pin is reserved.

SYMBOL

PINS

DESCRIPTION

VSO56 LQFP64

SDA 1 7 I

2

C-bus serial data input/output

SCL 2 8 I

2

C-bus serial clock input SYNC 3 9 cascade synchronization input CLK 4 10 external clock input V

SS

5 11 ground (logic)

TEST 6 12 test pin (connect to V

SS

)

SA0 7 13 I

2

C-bus slave address input (bit 0) A3 to A0 8 to 11 14, 16 to 18 I

2

C-bus subaddress inputs V

DD

12 20 supply voltage

n.c. 13

(1)

15, 19, 21,25 to 29, 34 not connected

V

3

, V

4

14 and 15 22 and 23 LCD bias voltage inputs

V

LCD

16 24 LCD supply voltage

C39 to C0 17 to 56 30 to 33, 35 to 64 and 1 to 6 LCD column driver outputs

1997 Apr 01 6

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

Fig.2 Pin configuration (VSO56).

1 2 3 4 5 6 7 8

9 10 11 12

13

44 43 42

41 40 39

38 37 36 35

34 33 32 31

14 15 16 17 18 19 20

22

23 24 25 26

21

46 45

47

48

49

50

51

52

53

54

55

56

27 28

30

29

MSA918

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

C0

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

n.c.

A0

SA0

TEST

SS

CLK

SYNC

SCL

SDA

V

PCF8579

V

LCD

V

4

V

3

V

DD

A1

A2

A3

1997 Apr 01 7

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

Fig.3 Pin configuration (LQFP64).

handbook, full pagewidth

PCF8579

MBH590

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

SDA

SCL

A2

A3

SA0

TEST

CLK

SYNC

V

SS

n.c.

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35

C36

C37

C38

C39

n.c.

A0

A1

V4V

3

V

DD

V

LCD

n.c.

1997 Apr 01 8

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

7 FUNCTIONAL DESCRIPTION

The PCF8579 column driver is designed for use with the PCF8578. Together they form a general purpose LCD dot matrix chip set.

Typically up to 16 PCF8579s may be used with one PCF8578. Each of the PCF8579s is identified by a unique 4-bit hardware subaddress, set by pins A0 to A3. The PCF8578 can operate with up to 32 PCF8579s when using two I2C-bus slave addresses. The two slave addresses are set by the logic level on input SA0.

7.1 Multiplexed LCD bias generation

The bias levels required to produce maximum contrast depend on the multiplex rate and the LCD threshold voltage (V

th

). Vth is typically defined as the RMS voltage at which the LCD exhibits 10% contrast. Table 1 shows the optimum voltage bias levels for the PCF8578/PCF8579 chip set as functions of Vop(Vop=VDD− V

LCD

), together with the discrimination ratios (D) for the different multiplex rates. A practical value for Vop is obtained by equating V

off(rms)

with Vth. Figure 4 shows the first 4 rows of Table 1

as graphs.

Table 1 Optimum LCD bias voltages

PARAMETER

MULTIPLEX RATE

1:8 1:16 1:24 1:32

0.739 0.800 0.830 0.850

0.522 0.600 0.661 0.700

0.478 0.400 0.339 0.300

0.261 0.200 0.170 0.150

0.297 0.245 0.214 0.193

0.430 0.316 0.263 0.230

1.447 1.291 1.230 1.196

3.370 4.080 4.680 5.190

V

2

V

op

---------

V

3

V

op

---------

V

4

V

op

---------

V

5

V

op

---------

V

off rms()

V

op

-----------------------

V

on rms()

V

op

---------------------- -

D

V

on rms()

V

off rms()

-----------------------

=

V

op

V

th

---------

7.2 Power-on reset

At power-on the PCF8579 resets to a defined starting condition as follows:

1. Display blank (in conjunction with PCF8578)

2. 1 : 32 multiplex rate

3. Start bank, 0 selected

4. Data pointer is set to X, Y address 0, 0

5. Character mode

6. Subaddress counter is set to 0

7. I

2

C-bus is initialized.

Data transfers on the I2C-bus should be avoided for 1 ms following power-on, to allow completion of the reset action.

Fig.4 V

bias/Vop

as a function of the multiplex rate.

1:8 1:16 1:32

1.0

0

0.8

MSA838

1:24

0.6

0.4

0.2

multiplex rate

V

bias

V

op

V

5

V

4

V

3

V

2

V

bias=V2

, V3, V4, V5. See Table 1.

1997 Apr 01 9

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

Fig.5 LCD row/column waveforms.

MSA841

V

DD

V

2

V V V V

3 4 5 LCD

T

frame

COLUMN

SYNC

V

DD

V

2

V V V V

3 4 5 LCD

ROW 0

0 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SYNC

V

DD

V

2

V V V V

3 4 5

LCD

COLUMN

V

DD

V

2

V V V V

3 4 5 LCD

ROW 0

23222120191817161514131211109876543210

SYNC

V

DD

V

2

V V V V

3 4 5 LCD

COLUMN

V

DD

V

2

V V V V

3 4 5 LCD

ROW 0

15

SYNC

14131211109876543210

V

DD

V

2

V V V V

3 4

5 LCD

COLUMN

V

DD

V

2

V V V V

3 4 5 LCD

ROW 0

0 1 2 3 4 5 67

ON OFF

1:8

1:16

1:24

1:32

column

display

1997 Apr 01 10

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

Fig.6 LCD drive mode waveforms for 1 : 8 multiplex rate.

MSA840

V

DD

V

2

V V V V

3 4 5 LCD

T

frame

ROW 1 R1 (t)

V

DD

V

2

V V V V

3 4 5 LCD

ROW 2 R2 (t)

V

DD

V

2

V V V V

3 4 5 LCD

COL 1 C1 (t)

V

DD

V

2

V V V V

3 4 5 LCD

COL 2 C2 (t)

dot matrix 1:8 multiplex rate

0.261 V

op

0.261 V

op

0 V

V

op

V

op

V

state 1

(t)

V

state 2

(t)

0.261 V

op

0.261 V

op

0 V

V

op

V

op

0.478 V

op

0.478 V

op

state 1 (OFF) state 2 (ON)

V

state 1

(t) = C1(t) R1(t):

V

on(rms)

V

op

=

188 1

8 1

()

8

=

0.430

V

state 2

(t) = C2(t) R2(t):

V

off(rms)

V

op

=

8 1

()

8

=

0.297

2

()

general relationship (n = multiplex rate)

V

on(rms)

V

op

=

1

n

1

n

1

()

n

V

off(rms)

V

op

=

n

1

n

1

()

n

2

()

1997 Apr 01 11

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

Fig.7 LCD drive mode waveforms for 1 : 16 multiplex rate.sa.

MSA836

V

DD

V

2

V V V V

3 4 5 LCD

T

frame

ROW 1 R1 (t)

V

DD

V

2

V V V V

3 4 5

LCD

ROW 2 R2 (t)

V

DD

V

2

V V V V

3 4 5 LCD

COL 1 C1 (t)

V

DD

V

2

V V V V

3 4 5 LCD

COL 2 C2 (t)

dot matrix 1:16 multiplex rate

state 1 (OFF) state 2 (ON)

0.2 V

op

0.2 V

op

0 V

V

op

V

op

V

state 1

(t)

0.2 V

op

0.2 V

op

0 V

V

op

V

op

V

state 2

(t)

0.6 V

op

0.6 V

op

V

state 1

(t) = C1(t) R1(t):

V

on(rms)

V

op

=

1

16

16 1

()

16

=

0.316

V

state 2

(t) = C2(t) R2(t):

V

off(rms)

V

op

=

16 1

()

16

=

0.254

2

()

general relationship (n = multiplex rate)

V

on(rms)

V

op

=

1

n

1

n

1

()

n

V

off(rms)

V

op

=

n

1

n

1

()

n

2

()

1997 Apr 01 12

Philips Semiconductors Product speciﬁcation

LCD column driver for dot matrix graphic displays

PCF8579

7.3 Timing generator

The timing generator of the PCF8579 organizes the internal data flow from the RAM to the display drivers. An external synchronization pulse SYNC is received from the PCF8578. This signal maintains the correct timing relationship between cascaded devices.

7.4 Column drivers

Outputs C0 to C39 are column drivers which must be connected to the LCD. Unused outputs should be left open-circuit.

7.5 Display RAM

The PCF8579 contains a 32 × 40-bit static RAM which stores the display data. The RAM is divided into 4 banks of 40 bytes (4 × 8 × 40 bits). During RAM access, data is transferred to/from the RAM via the I

2

C-bus.

7.6 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This allows an individual data byte or a series of data bytes to be written into, or read from, the display RAM, controlled by commands sent on the I

2

C-bus.

7.7 Subaddress counter

The storage and retrieval of display data is dependent on the content of the subaddress counter. Storage and retrieval take place only when the contents of the subaddress counter agree with the hardware subaddress at pins A0, A1, A2 and A3.

7.8 I

2

C-bus controller

The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display data bytes. It performs the conversion of the data input (serial-to-parallel) and the data output (parallel-to-serial). The PCF8579 acts as an I2C-bus slave transmitter/receiver. Device selection depends on the I2C-bus slave address, the hardware subaddress and the commands transmitted.

7.9 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.

7.10 RAM access

There are three RAM ACCESS modes:

• Character

• Half-graphic

• Full-graphic.

These modes are specified by bits G1 and G0 of the RAM ACCESS command. The RAM ACCESS command controls the order in which data is written to or read from the RAM (see Fig.8).

To store RAM data, the user specifies the location into which the first byte will be loaded (see Fig.9):

• Device subaddress (specified by the DEVICE SELECT command)

• RAM X-address (specified by the LOAD X-ADDRESS command)

• RAM bank (specified by bits Y1 and Y0 of the RAM ACCESS command).

Subsequent data bytes will be written or read according to the chosen RAM access mode. Device subaddresses are automatically incremented between devices until the last device is reached. If the last device has subaddress 15, further display data transfers will lead to a wrap-around of the subaddress to 0.

7.11 Display control

The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The number of rows scanned depends on the multiplex rate set by bits M1 and M0 of the SET MODE command.

The display status (all dots on/off and normal/inverse video) is set by bits E1 and E0 of the SET MODE command. For bank switching, the RAM bank corresponding to the top of the display is set by bits B1 and B0 of the SET START BANK command. This is shown in Fig.10 This feature is useful when scrolling in alphanumeric applications.

7.12 TEST pin

The TEST pin must be connected to V

SS

.