Philips PCF8578H-F1, PCF8578T, PCF8578U, PCF8578U-10, PCF8578U-12 Datasheet
...
DATA SH EET
Product specification
Supersedes data of 1997 Mar 28
File under Integrated Circuits, IC12
1998 Sep 08
INTEGRATED CIRCUITS
PCF8578
LCD row/column driver for dot
matrix graphic displays
1998 Sep 08 2
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
CONTENTS
1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
7.1 Mixed mode
7.2 Row mode
7.3 Multiplexed LCD bias generation
7.4 Power-on reset
7.5 Internal clock
7.6 External clock
7.7 Timing generator
7.8 Row/column drivers
7.9 Display mode controller
7.10 Display RAM
7.11 Data pointer
7.12 Subaddress counter
7.13 I2C-bus controller
7.14 Input filters
7.15 RAM access
7.16 Display control
7.17 TEST pin
8I
2
C-BUS PROTOCOL
8.1 Command decoder
9 CHARACTERISTICS OF THE I2C-BUS
9.1 Bit transfer
9.2 Start and stop conditions
9.3 System configuration
9.4 Acknowledge
10 LIMITING VALUES
11 HANDLING
12 DC CHARACTERISTICS
13 AC CHARACTERISTICS
14 APPLICATION INFORMATION
15 CHIP DIMENSIONS AND BONDING PAD
LOCATIONS
16 CHIP-ON GLASS INFORMATION
17 PACKAGE OUTLINE
18 SOLDERING
18.1 Introduction
18.2 Reflow soldering
18.3 Wave soldering
18.3.1 LQFP
18.3.2 VSO
18.3.3 Method (LQFP and VSO)
18.4 Repairing soldered joints
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS
21 PURCHASE OF PHILIPS I2C COMPONENTS
1998 Sep 08 3
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
1 FEATURES
• Single chip LCD controller/driver
• Stand-alone or may be used with up to 32 PCF8579s
(40960 dots possible)
• 40 driver outputs, configurable as32⁄8,24⁄16,16⁄24 or
8
⁄32rows/columns
• Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32
• Externally selectable bias configuration, 5 or 6 levels
• 1280-bit RAM for display data storage and scratch pad
• Display memory bank switching
• Auto-incremented data loading across hardware
subaddress boundaries (with PCF8579)
• Provides display synchronization for PCF8579
• On-chip oscillator, requires only 1 external resistor
• Power-on reset blanks display
• Logic voltage supply range 2.5 to 6 V
• Maximum LCD supply voltage 9 V
• Low power consumption
• I
2
C-bus interface
• TTL/CMOS compatible
• Compatible with most microcontrollers
• Optimized pinning for single plane wiring in multiple
device applications (with PCF8579)
• Space saving 56-lead plastic mini-pack and 64 pin quad
flat pack
• Compatible with chip-on-glass technology.
2 APPLICATIONS
• Automotive information systems
• Telecommunication systems
• Point-of-sale terminals
• Computer terminals
• Instrumentation.
3 GENERAL DESCRIPTION
The PCF8578 is a low power CMOS LCD row/column
driver, designed to drive dot matrix graphic displays at
multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device
has 40 outputs, of which 24 are programmable,
configurable as
32
⁄8,24⁄16,16⁄24 or8⁄32rows/columns.
The PCF8578 can function as a stand-alone LCD
controller/driver for use in small systems, or for larger
systems can be used in conjunction with up to
32 PCF8579s for which it has been optimized. Together
these two devices form a general purpose LCD dot matrix
driver chip set, capable of driving displays of up to
40960 dots. The PCF8578 is compatible with most
microcontrollers and communicates via a two-line
bidirectional bus (I2C-bus). Communication overheads are
minimized by a display RAM with auto-incremented
addressing and display bank switching.
4 ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
PCF8578T VSO56 plastic very small outline package; 56 leads SOT190-1
PCF8578U/2 − chip with bumps in tray −
PCF8578H LQFP64 plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2
1998 Sep 08 4
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
5 BLOCK DIAGRAM
Fig.1 Block diagram.
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
The pin numbers given in parenthesis refer to the LQFP64 package.
V
SS
C39 - C32
R31/C31 - R8/C8
R7 - R0
17 - 56
(29 to 35, 37, 38 to 46
48 to 62, 63, 64, 1 to 6)
MSA842
V
DD
PCF8578
V
LCD
V
2
V
3
V
4
V
5
9 (20)
10 (21)
11 (22)
12 (23)
13 (24)
14 (25)
6 (12)
OUTPUT
CONTROLLER
ROW/COLUMN
DRIVERS
(1)
DISPLAY
MODE
CONTROLLER
Y DECODER
AND SENSING
AMPLIFIERS
32 x 40-BIT
DISPLAY RAM
X DECODER
DISPLAY
DECODER
RAM DATA POINTER
SUBADDRESS
COUNTER
TIMING
GENERATOR
I C-BUS
CONTROLLER
2
INPUT
FILTERS
COMMAND
DECODER
POWER-ON
RESET
OSCILLATOR
TEST
2 (8)
1 (7)
SCL
SDA
n.c. n.c.
SA0
15, 16
(14, 15, 17 to 19
26 to 28 36, 47)
7 (13)
(16) 8
(11) 5
(10) 4
(9) 3
R
OSC
OSC
CLK
SYNC
YX
1998 Sep 08 5
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
6 PINNING
SYMBOL
PIN
DESCRIPTION
VSO56 LQFP64
SDA 1 7 I
2
C-bus serial data input/output
SCL 2 8 I
2
C-bus serial clock input
SYNC 3 9 cascade synchronization output
CLK 4 10 external clock input/output
V
SS
5 11 ground (logic)
TEST 6 12 test pin (connect to V
SS
)
SA0 7 13 I
2
C-bus slave address input (bit 0)
OSC 8 16 oscillator input
V
DD
9 20 positive supply voltage
V
2
to V
5
10 to 13 21 to 24 LCD bias voltage inputs
V
LCD
14 25 LCD supply voltage
n.c. 15, 16 14, 15, 17 to 19,
26 to 28, 36, 47
not connected
C39 to C32 17 to 24 29 to 35, 37 LCD column driver outputs
R31/C31 to R8/C8 25 to 48 38 to 46, 48 to 62 LCD row/column driver outputs
R7 to R0 49 to 56 63, 64, 1 to 6 LCD row driver outputs
1998 Sep 08 6
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
Fig.2 Pin configuration (VSO56).
1
2
3
4
5
6
7
8
9
10
11
12
13
44
43
42
41
40
39
38
37
36
35
34
33
32
31
14
15
16
17
18
19
20
22
23
24
25
26
21
46
45
47
48
49
50
51
52
53
54
55
56
27
28
30
29
MSA839
R27/C27
R26/C26
R25/C25
R24/C24
R23/C23
R22/C22
R21/C21
R20/C20
R19/C19
R18/C18
R17/C17
R16/C16
R15/C15
R14/C14
R13/C13
R12/C12
R11/C11
R10/C10
R9/C9
R8/C8
R7
R6
R5
R4
R3
R2
R1
R0
R28/C28
R29/C29
R30/C30
R31/C31
C32
C33
C34
C35
C36
C37
C38
C39
n.c.
n.c.
V
LCD
V
5
V
4
V
3
V
2
V
DD
OSC
SA0
TEST
SS
CLK
SYNC
SCL
SDA
V
PCF8578
1998 Sep 08 7
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
Fig.3 Pin configuration (LQFP64).
handbook, full pagewidth
PCF8578
MBH588
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SCL
CLK
TEST
SA0
n.c.
n.c.
OSC
V
SS
SYNC
SDA
R0
R1
R2
R3
R4
R5
R6
R7
R21/C21
R20/C20
R19/C19
R18/C18
R17/C17
R16/C16
R15/C15
R14/C14
R13/C13
R12/C12
R11/C11
R10/C10
R9/C9
R8/C8
R31/C31
C35
C34
C33
n.c.
C32
C39
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
V
LCD
V
DD
V
5V4V3V2
C38
C37
C36
R30/C30
R29/C29
R28/C28
R27/C27
R26/C26
R24/C24
R25/C25
R23/C23
n.c.
R22/C22
1998 Sep 08 8
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
7 FUNCTIONAL DESCRIPTION
The PCF8578 row/column driver is designed for use in one
of three ways:
• Stand-alone row/column driver for small displays
(mixed mode)
• Row/column driver with cascaded PCF8579s
(mixed mode)
• Row driver with cascaded PCF8579s (mixed mode).
7.1 Mixed mode
In mixed mode, the device functions as both a row and
column driver. It can be used in small stand-alone
applications, or for larger displays with up to 15 PCF8579s
(31 PCF8579s when two slave addresses are used).
See Table 1 for common display configurations.
7.2 Row mode
In row mode, the device functions as a row driver with up
to 32 row outputs and provides the clock and
synchronization signals for the PCF8579. Up to 16
PCF8579s can normally be cascaded (32 when two slave
addresses are used).
Timing signals are derived from the on-chip oscillator,
whose frequency is determined by the value of the resistor
connected between OSC and V
SS
.
Commands sent on the I2C-bus from the host
microcontroller set the mode (row or mixed), configuration
(multiplex rate and number of rows and columns) and
control the operation of the device. The device may have
one of two slave addresses. The only difference between
these slave addresses is the least significant bit, which is
set by the logic level applied to SA0. The PCF8578 and
PCF8579 also have subaddresses. The subaddress of the
PCF8578 is only defined in mixed mode and is fixed at 0.
The RAM may only be accessed in mixed mode and data
is loaded as described for the PCF8579.
Bias levels may be generated by an external potential
divider with appropriate decoupling capacitors. For large
displays, bias sources with high drive capability should be
used. A typical mixed mode system operating with up to
15 PCF8579s is shown in Fig.5 (a stand-alone system
would be identical but without the PCF8579s).
Table 1 Possible displays configurations
Notes
1. Using 15 PCF8579s.
2. Using 16 PCF8579s.
APPLICATION
MULTIPLEX
RATE
MIXED MODE ROW MODE
TYPICAL APPLICATIONS
ROWS COLUMNS ROWS COLUMNS
Stand alone 1 : 8 8 32 −−small digital or
alphanumerical displays
1:16 16 24 −−
1:24 24 16 −−
1:32 32 8 −−
With PCF8579 1 : 8 8
(1)
632
(1)
8 × 44
(2)
640
(2)
alphanumeric displays and
dot matrix graphic displays
1:16 16
(1)
624
(1)
16 × 2
(2)
640
(2)
1:24 24
(1)
616
(1)
24
(2)
640
(2)
1:32 32
(1)
608
(1)
24
(2)
640
(2)
1998 Sep 08 9
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
7.3 Multiplexed LCD bias generation
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (Vth). Vth is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 2 shows the
optimum voltage bias levels for the PCF8578 as functions
of Vop(Vop=VDD− V
LCD
), together with the discrimination
ratios (D) for the different multiplex rates. A practical value
for Vop is obtained by equating V
off(rms)
with Vth. Figure 4
shows the first 4 rows of Table 2 as graphs. Table 3 shows
the relative values of the resistors required in the
configuration of Fig.5 to produce the standard multiplex
rates.
Table 2 Optimum LCD voltages
Table 3 Multiplex rates and resistor values for Fig.5
PARAMETER
MULTIPLEX RATE
1:8 1:16 1:24 1:32
0.739 0.800 0.830 0.850
0.522 0.600 0.661 0.700
0.478 0.400 0.339 0.300
0.261 0.200 0.170 0.150
0.297 0.245 0.214 0.193
0.430 0.316 0.263 0.230
1.447 1.291 1.230 1.196
3.370 4.080 4.680 5.190
RESISTORS
MULTIPLEX RATE (n)
n = 8 n = 16, 24, 32
R1 R R
R2 R
R3
V
2
V
op
---------
V
3
V
op
---------
V
4
V
op
---------
V
5
V
op
---------
V
off rms()
V
op
-----------------------
V
on rms()
V
op
---------------------- -
D
V
on rms()
V
off rms()
-----------------------
=
V
op
V
th
---------
n2–()R
3n–()R n3–()R
7.4 Power-on reset
At power-on the PCF8578 resets to a defined starting
condition as follows:
1. Display blank
2. 1 : 32 multiplex rate, row mode
3. Start bank, 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I2C-bus interface is initialized.
Data transfers on the I
2
C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
Fig.4 V
bias/Vop
as a function of the multiplex rate.
1:8 1:16 1:32
1.0
0
0.8
MSA838
1:24
0.6
0.4
0.2
multiplex rate
V
bias
V
op
V
5
V
4
V
3
V
2
V
bias=V2
, V3, V4, V5. See Table 2.
1998 Sep 08 10
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
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R
OSC
OSC
V
SS
SDA
SA0
CLK SYNC
V3V
4
V
DD
V
LCD
A0
A1
A2
A3
V
SS
PCF8579
40
columns
SCL
V
SS
SCLSDA
SA0
CLK SYNC
V
3
V
4
V
DD
V
LCD
PCF8578
V
LCD
V
DD
V
2
V
5
VSSVDD/
V
SS
LCD DISPLAY
V
DD
R1
C
R2
C
R3
C
R2
C
R1
C
VSSV
DD
/
V
LCD
subaddress 1
VSSVDD/
40 n
columns
n
rows
HOST
MICROCONTROLLER
SCL
SDA
MSA843
Fig.5 Typical mixed mode configuration.
1998 Sep 08 11
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
Fig.6 LCD row/column waveforms.
MSA841
V
DD
V
2
V
V
V
V
3
4
5
LCD
T
frame
COLUMN
SYNC
V
DD
V
2
V
V
V
V
3
4
5
LCD
ROW 0
0 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SYNC
V
DD
V
2
V
V
V
V
3
4
5
LCD
COLUMN
V
DD
V
2
V
V
V
V
3
4
5
LCD
ROW 0
23222120191817161514131211109876543210
SYNC
V
DD
V
2
V
V
V
V
3
4
5
LCD
COLUMN
V
DD
V
2
V
V
V
V
3
4
5
LCD
ROW 0
15
SYNC
14131211109876543210
V
DD
V
2
V
V
V
V
3
4
5
LCD
COLUMN
V
DD
V
2
V
V
V
V
3
4
5
LCD
ROW 0
0 1 2 3 4 5 67
ON
OFF
1:8
1:16
1:24
1:32
column
display
1998 Sep 08 12
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
Fig.7 LCD drive mode waveforms for 1 : 8 multiplex rate.
MSA840
V
DD
V
2
V
V
V
V
3
4
5
LCD
T
frame
ROW 1
R1 (t)
V
DD
V
2
V
V
V
V
3
4
5
LCD
ROW 2
R2 (t)
V
DD
V
2
V
V
V
V
3
4
5
LCD
COL 1
C1 (t)
V
DD
V
2
V
V
V
V
3
4
5
LCD
COL 2
C2 (t)
dot matrix
1:8 multiplex rate
0.261 V
op
0.261 V
op
0 V
V
op
V
op
V
state 1
(t)
V
state 2
(t)
0.261 V
op
0.261 V
op
0 V
V
op
V
op
0.478 V
op
0.478 V
op
state 1 (OFF)
state 2 (ON)
V
state 1
(t) =C1(t) R1(t):
V
on(rms)
V
op
=
1
8
8 1
8 1
()
8
=
0.430
V
state 2
(t) = C2(t) R2(t):
V
off(rms)
V
op
=
8 1
8 1
()
8
=
0.297
2
2
()
general relationship (n = multiplex rate)
V
on(rms)
V
op
=
1
n
n
1
n
1
()
n
V
off(rms)
V
op
=
n
1
n
1
()
n
2
2
()
1998 Sep 08 13
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.
MSA836
V
DD
V
2
V
V
V
V
3
4
5
LCD
T
frame
ROW 1
R1 (t)
V
DD
V
2
V
V
V
V
3
4
5
LCD
ROW 2
R2 (t)
V
DD
V
2
V
V
V
V
3
4
5
LCD
COL 1
C1 (t)
V
DD
V
2
V
V
V
V
3
4
5
LCD
COL 2
C2 (t)
dot matrix
1:16 multiplex rate
state 1 (OFF)
state 2 (ON)
0.2 V
op
0.2 V
op
0 V
V
op
V
op
V
state 1
(t)
0.2 V
op
0.2 V
op
0 V
V
op
V
op
V
state 2
(t)
0.6 V
op
0.6 V
op
V
state 1
(t) = C1(t) R1(t):
V
on(rms)
V
op
=
1
16
16 1
16 1
()
16
=
0.316
V
state 2
(t) = C2(t) R2(t):
V
off(rms)
V
op
=
16 1
16 1
()
16
=
0.254
2
2
()
general relationship (n = multiplex rate)
V
on(rms)
V
op
=
1
n
n
1
n
1
()
n
V
off(rms)
V
op
=
n
1
n
1
()
n
2
2
()
1998 Sep 08 14
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays
PCF8578
7.5 Internal clock
The clock signal for the system may be generated by the
internal oscillator and prescaler. The frequency is
determined by the value of the resistor R
OSC
, see Fig.9.
For normal use a value of 330 kΩ is recommended.
The clock signal, for cascaded PCF8579s, is output at CLK
and has a frequency1⁄6 (multiplex rate 1 : 8, 1 : 16 and
1 : 32) or1⁄8 (multiplex rate 1 : 24) of the oscillator
frequency.
Fig.9 Oscillator frequency as a function of
external oscillator resistor, R
OSC
.
To avoid capacitive coupling, which could adversely affect oscillator
stability, R
OSC
should be placed as closely as possible to the OSC
pin. If this proves to be a problem, a filtering capacitor may be
connected in parallel to R
OSC
.
10
MSA837
10
2
10
3
10
4
1
10
3
10
10
2
f
OSC
(kHz)
R(kΩ)
OSC
7.6 External clock
If an external clock is used, OSC must be connected to
VDD and the external clock signal to CLK. Table 4
summarizes the nominal CLK and SYNC frequencies.
7.7 Timing generator
The timing generator of the PCF8578 organizes the
internal data flow of the device and generates the LCD
frame synchronization pulse
SYNC, whose period is an
integer multiple of the clock period. In cascaded
applications, this signal maintains the correct timing
relationship between the PCF8578 and PCF8579s in the
system.
7.8 Row/column drivers
Outputs R0 to R7 and C32 to C39 are fixed as row and
column drivers respectively. The remaining 24 outputs
R8/C8 to R31/C31 are programmable and may be
configured (in blocks of 8) to be either row or column
drivers. The row select signal is produced sequentially at
each output from R0 up to the number defined by the
multiplex rate (see Table 1). In mixed mode the remaining
outputs are configured as columns. In row mode all
programmable outputs (R8/C8 to R31/C31) are defined as
row drivers and the outputs C32 to C39 should be left
open-circuit.
Using a 1 : 16 multiplex rate, two sets of row outputs are
driven, thus facilitating split-screen configurations, i.e. a
row select pulse appears simultaneously at R0 and
R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex
rate of 1 : 8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly
to the LCD. Unused outputs should be left open-circuit.
In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are
rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32
R0 to R31/C31 are rows.
Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note 1.
Notes
1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
2. R
OSC
= 330 kΩ.
OSCILLATOR
FREQUENCY
f
OSC
(2)
(Hz)
FRAME FREQUENCY
f
SYNC
(Hz)
MULTIPLEX RATE (n)
DIVISION
RATIO
CLOCK FREQUENCY
f
CLK
(Hz)
12288 64 1 : 8, 1 : 16, 1 : 32 6 2048
12288 64 1 : 24 8 1536
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