Philips pcf8577c DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

PCF8577C

LCD direct/duplex driver with

2

I

C-bus interface

Product specification
Supersedes data of July 1993
File under Integrated Circuits, IC12

1995 Jun 08

Philips Semiconductors Product specification

LCD direct/duplex driver with

2

I

C-bus interface

FEATURES

• Direct/duplex drive modes with up to
32/64 LCD-segment drive capability per device

• Operating supply voltage: 2.5 to 6 V

• Low power consumption

• I2C-bus interface

• Optimized pinning for single plane wiring

• Single-pin built-in oscillator

• Auto-incremented loading across device subaddress

boundaries

• Display memory switching in direct drive mode

2

• May be used as I

• System expansion up to 256 segments

• Power-on reset blanks display.

ORDERING INFORMATION

C-bus output expander

PCF8577C

GENERAL DESCRIPTION

The PCF8577C is a single chip, silicon gate CMOS circuit.
It is designed to drive liquid crystal displays with up to
32 segments directly, or 64 segments in a duplex
configuration.

The two-line I
overheads in remote display applications. I2C-bus traffic is
minimized in multiple IC applications by automatic address
incrementing, hardware subaddressing and display
memory switching (direct drive mode).

2

C-bus interface substantially reduces wiring

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF8577CP DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
PCF8577CT VSO40 plastic very small outline package; 40 leads SOT158A
PCF8577CT − V6040 in blister tape −
PCF8577CU/10 − chip on film-frame-carrier (FFC) −

BLOCK DIAGRAM

1

SCL

2

I C - BUS

SDA

V

DD

V

SS

39

40

35

38

INPUT

FILTERS

POWER -

ON

RESET

2

I C - BUS

CONTROLLER

PCF8577C

SEGMENT BYTE

REGISTERS

AND

MULTIPLEX

LOGIC

CONTROL REGISTER

AND

COMPARATOR

BACKPLANE

AND

SEGMENT

DRIVERS

OSCILLATOR

AND

DIVIDER

S32

32

S1

33

BP1

34

A2/BP2

36

A1

37

A0/OSC

1995 Jun 08 2

MGA727

Fig.1 Block diagram.

Philips Semiconductors Product specification

LCD direct/duplex driver with

2

I

C-bus interface

PINNING

SYMBOL PIN DESCRIPTION

S32 to S1 1 to 32 segments outputs
BP1 33 cascade sync input/backplane

output

A2/BP2 34 hardware address line and

cascade sync input/backplane
output

V

DD

A1 36 hardware address line input
A0/OSC 37 hardware address line and

V

SS

SCL 39 I
SDA 40 I

35 positive supply voltage

oscillator pin input

38 negative supply voltage

2

C-bus clock line input

2

C-bus data line input/output

S32
S31
S30
S29
S28
S27
S26

S25
S24
S23
S22
S21

1
2
3
4
5
6

7
8

9
10
11
12

PCF8577C

PCF8577C

SDA

40
39

SCL
V

38

SS

A0/OSC

37
36

A1
V

35

DD

A2/BP2

34
33

BP1

32

S1

31

S2

30

S3

29

S4

S20

13

S19

15

S18

16

S17

17

S16

18

S15

19

S14

20

S13

MGA725

Fig.2 Pin configuration.

28

S5

2714

S6

26

S7

25

S8

24

S9

23

S10

22

S11

21

S12

1995 Jun 08 3

Philips Semiconductors Product specification

LCD direct/duplex driver with

2

I

C-bus interface

FUNCTIONAL DESCRIPTION
Hardware subaddress A0, A1, A2

The hardware subaddress lines A0, A1 and A2 are used to
program the device subaddress for each PCF8577C
connected to the I
OSC and BP2 respectively to reduce pin-out
requirements.

1. Line A0 is defined as LOW (logic 0) when this pin is
used for the local oscillator or when connected to VSS.
Line A0 is defined as HIGH (logic 1) when connected
to VDD.

2. Line A1 must be defined as LOW (logic 0) or as HIGH
(logic 1) by connection to VSS or VDD respectively.

3. In the direct drive mode the second backplane signal
BP2 is not used and the A2/BP2 pin is exclusively the
A2 input. Line A2 is defined as LOW (logic 0) when
connected to VSS or, if this is not possible, by leaving
it unconnected (internal pull-down). Line A2 is defined
as HIGH (logic 1) when connected to VDD.

4. In the duplex drive mode the second backplane signal
BP2 is required and the A2 signal is undefined. In this
mode device selection is made exclusively from
lines A0 and A1.

Oscillator A0/OSC

The PCF8577C has a single-pin built-in oscillator which
provides the modulation for the LCD segment driver
outputs. One external resistor and one external capacitor
are connected to the A0/OSC pin to form the oscillator (see
Figs 15 and 16 ). For correct start-up of the oscillator after
power on, the resistor and capacitor must be connected to
the same V
containing more than one PCF8577C the backplane
signals are usually common to all devices and only one
oscillator is required. The devices which are not used for
the oscillator are put into the cascade mode by connecting
the A0/OSC pin to either VDD or VSS depending on the
required state for A0. In the cascade mode each
PCF8577C is synchronized from the backplane signal(s).

2

C-bus. Lines A0 and A2 are shared with

as the chip. In an expanded system

SS/VDD

PCF8577C

There is one slave address for the PCF8577C (see Fig.6).
All addressed devices load the second byte into the control
register and each device maintains an identical copy of the
control byte in the control register at all times (see I
protocol Fig.7), i.e. all addressed devices respond to
control commands sent on the I2C-bus.

The control register is shown in more detail in Fig.3. The
least-significant bits select which device and which
segment byte register is loaded next. This part of the
register is therefore called the Segment Byte Vector
(SBV).

The upper three bits of the SBV (V5 to V3) are compared
with the hardware subaddress input signals A2, A1
and A0. If they are the same then the device is enabled for
loading, if not the device ignores incoming data but
remains active.

The three least-significant bits of the SBV (V2 to V0)
address one of the segment byte registers within the
enabled chip for loading segment data.

The control register also has two display control bits.
These bits are named MODE and BANK. The MODE bit
selects whether the display outputs are configured for
direct or duplex drive displays. The BANK bit allows the
user to display BANK A or BANK B.

Auto-incremented loading

After each segment byte is loaded the SBV is incremented
automatically. Thus auto-incremented loading occurs if
more than one segment byte is received in a data transfer.

Since the SBV addresses both device and segment
registers in all addressed chips, auto-incremented loading
may proceed across device boundaries provided that the
hardware subaddresses are arranged contiguously.

2

C-bus

User-accessible registers

There are nine user-accessible 1-byte registers. The first
is a control register which is used to control the loading of
data into the segment byte registers and to select display
options. The other eight are segment byte registers, split
into two banks of storage, which store the segment data.
The set of even numbered segment byte registers is called
BANK A. Odd numbered segment byte registers are called
BANK B.

1995 Jun 08 4

Philips Semiconductors Product specification

LCD direct/duplex driver with

2

I

C-bus interface

CONTROL REGISTER SEGMENT BYTE REGISTERS

DISPLAY

CONTROL

SEGMENT BYTE VECTOR

V5

(1) (1)

comparison

A2 A1 A0

subaddress

0 BANK 'A'
1 BANK 'B'

(SBV)

V4 V3 V2 V1 V0

device

segment byte

register

address

BANK

PCF8577C

msb lsbmsb lsb

0

2

BANK 'A'

4

6

1

3

BANK 'B'

5

7
0 DIRECT DRIVE
1 DUPLEX DRIVE

V V

(V V )

DISPLAY

MODE

(1) Bits ignored in duplex mode.

Fig.3 PCF8577C register organization.

OFF ON

V

DD

V

SS

V

DD

V

SS
SSDD

0

SSDD

1

f

LCD

Segment x

BP1 Sx

MGA733

BP1

(Sx)

MGA737

V

on(rms)=VDD

− VSS; V

off(rms)

1995 Jun 08 5

=0.

Fig.4 Direct drive mode display output waveforms.

Philips Semiconductors Product specification

LCD direct/duplex driver with

2

I

C-bus interface

Direct drive mode

The PCF8577C is set to the direct drive mode by loading
the MODE control bit with logic 0. In this mode only four
bytes are required to store the data for the 32 segment
drivers. Setting the BANK bit to logic 0 selects even bytes
(BANK A), setting the BANK bit to logic 1 selects odd bytes
(BANK B).

In the direct drive mode the SBV is auto-incremented by
two after the loading of each segment byte register. This
means that auto-incremented loading of BANK A or
BANK B is possible. Either bank may be completely or
partially loaded irrespective of which bank is being
displayed. Direct drive output waveforms are shown in
Fig.4.

OFF / OFF ON / OFF OFF / ON ON / ON

V

DD

0.5 (V V )
V

SS

V

DD

0.5 (V V )
V

SS

V

DD

V

SS

V V

0.5 (V V )
0

0.5 (V V )
(V V )

V V

0.5 (V V )
0

0.5 (V V )
(V V )

SSDD

SSDD

SSDD

SSDD

SSDD

SSDD

SSDD

SSDD

SSDD

SSDD

PCF8577C

Duplex mode

The PCF8577C is set to the duplex mode by loading the
MODE bit with logic 1. In this mode a second backplane
signal (BP2) is needed and pin A2/BP2 is used for this;
therefore A2 and its equivalent SBV bit V5 are undefined.
The SBV auto-increments by one between loaded bytes.

All of the segment bytes are required to store data for the
32 segment drivers and the BANK bit is ignored.

Duplex mode output waveforms are shown in Fig.5.

BP1

BP2

Segment x

(Sx)

BP1 Sx

BP2 Sx

1

f

LCD

MGA738

V

= 0.791 (VDD− VSS); V

on(rms)

V

on rms()

----------------------­V

off rms()

2.236=

1995 Jun 08 6

= 0.354 (VDD− VSS).

off(rms)

Fig.5 Duplex mode display output waveforms.

Philips Semiconductors Product specification

LCD direct/duplex driver with

2

I

C-bus interface

Power-on reset

At power-on reset the PCF8577C resets to a defined
starting condition as follows:

1. Both backplane outputs are set to VSS in master mode;
to 3-state in cascade mode.

2. All segment outputs are set to VSS.

3. The segment byte registers and control register are
cleared.

4. The I2C-bus interface is initialized.

Slave address

The PCF8577C slave address is shown in Fig.6.
Before any data is transmitted on the I

which should respond is addressed first. The addressing is
always done with the first byte transmitted after the start
procedure.

2

C-bus, the device

PCF8577C

I2C-bus protocol

The PCF8577C I2C-bus protocol is shown in Fig.7.
The PCF8577C is a slave receiver and has a fixed slave

address (see Fig.6). All PCF8577Cs with the same slave
address acknowledge the slave address in parallel. The
second byte is always the control byte and is loaded into
the control register of each PCF8577C connected to the
I2C-bus. All addressed devices acknowledge the control
byte. Subsequent data bytes are loaded into the segment
registers of the selected device. Any number of data bytes
may be loaded in one transfer and in an expanded system
rollover of the SBV from 111 111 to 000 000 is allowed. If
a stop (P) condition is given after the control byte
acknowledge the segment data will remain unchanged.
This allows the BANK bit to be toggled without changing
the segment register contents. During loading of segment
data only the selected PCF8577C gives an acknowledge.
Loading is terminated by generating a stop (P) condition.

0 1110100S A

SLAVE ADDRESS

MGA731

Fig.6 PCF8577C slave address.

acknowledge by

all PCF8577C

S

MGA732

0

R/W

acknowledge by

all PCF8577C

msb lsb

MODE

BANK

SEGMENT

BYTE VECTOR

ASLAVE ADDRESS

AASEGMENT DATA P

n bytescontrol byte

acknowledge by

selected PCF8577C only

auto increment

segment byte vector

1995 Jun 08 7

Fig.7 I2C-bus protocol.