Philips PCF8576U-10, PCF8576U-2, PCF8576U-5, PCF8576T, PCF8576U Datasheet

INTEGRATED CIRCUITS

DATA SH EET

PCF8576

Universal LCD driver for low multiplex rates

Product speciﬁcation Supersedes data of 1998 Feb 06 File under Integrated Circuits, IC12

2001 Oct 02

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

1 FEATURES

• Single-chip LCD controller/driver

• Selectable backplanedrive configuration: static or 2/3/4

backplane multiplexing

• Selectable display bias configuration: static,1⁄2 or1⁄

• Internal LCD bias generation with voltage-follower

buffers

• 40 segment drives: up to twenty 8-segment numeric characters; up to ten 15-segment alphanumeric characters; or any graphics of up to 160 elements

• 40 × 4-bit RAM for display data storage

• Auto-incremented display data loading across device

subaddress boundaries

• Display memory bank switching in static and duplex drive modes

• Versatile blinking modes

• LCD and logic supplies may be separated

• Wide power supply range: from 2 V for low-threshold

LCDs and up to 9 V for guest-host LCDs and high-threshold (automobile) twisted nematic LCDs

• Low power consumption

• Power-saving mode for extremely low power

consumption in battery-operated and telephone applications

• I2C-bus interface

• TTL/CMOS compatible

• Compatible with any 4-bit, 8-bit or 16-bit

microprocessors/microcontrollers

3

• May be cascaded for large LCD applications (up to 2560 segments possible)

• Cascadable with 24-segment LCD driver PCF8566

• Optimized pinning for plane wiring in both single and

multiple PCF8576 applications

• Space-saving56-leadplasticverysmalloutlinepackage (VSO56)

• Very low external component count (at most one resistor, even in multiple device applications)

• Compatible with chip-on-glass technology

• Manufactured in silicon gate CMOS process.

2 GENERAL DESCRIPTION

The PCF8576 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to40 segmentsandcaneasily be cascaded for larger LCD applications. The PCF8576 is compatible with most microprocessors/microcontrollersandcommunicatesvia a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes).

3 ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

PCF8576T VSO56 plastic very small outline package; 56 leads SOT190-1 PCF8576U − chip in tray − PCF8576U/2 − chip with bumps in tray − PCF8576U/5 − unsawn wafer − PCF8576U/10 FFC chip on ﬁlm frame carrier (FFC) − PCF8576U/12 FFC chip with bumps on ﬁlm frame carrier (FFC) −

2001 Oct 02 3

PACKAGE

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2001 Oct 02 4

4 BLOCK DIAGRAM

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

V

DD

V

LCD

CLK

SYNC

OSC

V

SS

SCL

SDA

5

R

LCD BIAS

R

12

4 3

6

11

2 1

GENERATOR

TIMING BLINKER

OSCILLATOR

INPUT

FILTERS

VOLTAGE

SELECTOR

POWER-

ON

RESET

2

I C - BUS

CONTROLLER

LCD

10

BP014BP215BP116BP3

13

BACKPLANE

OUTPUTS

PCF8576

DISPLAY

CONTROLLER

COMMAND

DECODER

INPUT

BANK

SELECTOR

S0 to S39

40

17 to 56

DISPLAY SEGMENT OUTPUTS

DISPLAY LATCH

SHIFT REGISTER

DISPLAY

RAM

40 x 4 BITS

DATA

POINTER

OUTPUT

BANK

SELECTOR

SUBADDRESS COUNTER

9

SA0

Fig.1 Block diagram (for VSO56 package; SOT190-1).

handbook, full pagewidth

A07A18A2

MBK276

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

5 PINNING

SYMBOL PIN DESCRIPTION

2

SDA 1 I SCL 2 I SYNC 3 cascade synchronization input/output CLK 4 external clock input/output V

DD

5 supply voltage OSC 6 oscillator input A0 to A2 7 to 9 I SA0 10 I V V

SS LCD

11 logic ground

12 LCD supply voltage BP0, BP2, BP1 and BP3 13 to 16 LCD backplane outputs S0 to S39 17 to 56 LCD segment outputs

C-bus serial data input/output

2

C-bus serial clock input

2

C-bus subaddress inputs

2

C-bus slave address input; bit 0

2001 Oct 02 5

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

handbook, halfpage

SDA

SCL

SYNC

CLK

V

DD

OSC

A0 A1 A2

SA0

V

SS

V

LCD

BP0 BP2 BP1 BP3

S0 S1 S2 S3 S4 S5 S6 S7 S8

S9 S10 S11

1 2 3 4 5 6 7 8

9 10 11 12 13 14

PCF8576T

15 16 17 18 19 20 21 22 23 24 25 26 27 28

MBK278

56

S39

55

S38

54

S37

53

S36

52

S35

51

S34

50

S33

49

S32

48

S31

47

S30

46

S29

45

S28

44

S27

43

S26

42

S25

41

S24

40

S23

39

S22

38

S21

37

S20

36

S19

35

S18

34

S17

33

S16

32

S15

31

S14

30

S13

29

S12

Fig.2 Pin configuration; SOT190-1.

2001 Oct 02 6

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

6 FUNCTIONAL DESCRIPTION

The PCF8576 is a versatile peripheral device designed to interface to any microprocessor/microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. The display configurations possible with the PCF8576 depend on the number of active backplane outputs required; a selection of display configurations is

The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8576. The internal oscillator is selected by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and V

) and the

LCD

LCD panel chosen for the application. given in Table . All of the display configurations given in Table can be

implemented in the typical system shown in Fig.3.

Selection of display conﬁgurations

NUMBER OF 7-SEGMENTS NUMERIC

14-SEGMENTS

ALPHANUMERIC

DOT MATRIX

BACKPLANES SEGMENTS DIGITS

INDICATOR

SYMBOLS

CHARACTERS

INDICATOR

SYMBOLS

4 160 20 20 10 20 160 dots (4 × 40) 3 120 15 15 8 8 120 dots (3 × 40) 2 80 10 10 5 10 80 dots (2 × 40) 1 40552 1240dots (1 × 40)

handbook, full pagewidth

V

DD

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

V

SS

t

r

R

2C

B

SDA

SCL

OSC

R

OSC

V

DD

512

1 17 to 56

2

PCF8576

6

78

A0 A1 A2SSSA0 V

Fig.3 Typical system configuration.

2001 Oct 02 7

V

LCD

13 to 16

91011

40 segment drives

4 backplanes

LCD PANEL

(up to 160 elements)

MBK277

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

6.1 Power-on reset

At power-on the PCF8576 resets to a starting condition as follows:

1. All backplane outputs are set to VDD.

2. All segment outputs are set to VDD.

3. Thedrive mode ‘1 : 4 multiplex with1⁄3bias’ is selected.

4. Blinking is switched off.

5. Input and output bank selectors are reset (as defined

in Table 4).

6. The I2C-bus interface is initialized.

7. The data pointer and the subaddress counter are

cleared.

Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action.

6.2 LCD bias generator

The full-scale LCD voltage (Vop) is obtained from VDD− V compensatedexternallythroughtheV

. The LCD voltage may be temperature

LCD

supplytopin 12.

LCD

Fractional LCD biasing voltages are obtained from an internal voltage divider of the three series resistors connectedbetween VDDandV

.The centre resistor can

LCD

be switched out of the circuit to provide a1⁄2bias voltage level for the 1 : 2 multiplex configuration.

6.3 LCD voltage selector

The LCD voltage selector co-ordinates the multiplexing of

the LCD in accordance with the selected LCD drive

configuration. The operation of the voltage selector is

controlled by MODE SET commands from the command

decoder. The biasing configurations that apply to the

preferred modes of operation, together with the biasing

characteristics as functions of Vop=VDD− V

LCD

and the

resulting discrimination ratios (D), are given in Table 1.

A practical value for Vopis determined by equating V

off(rms)

with a defined LCD threshold voltage (Vth), typically when

the LCD exhibits approximately 10% contrast. In the static

drive mode a suitable choice is Vop>3Vth approximately.

1

Multiplex drive ratios of 1 : 3 and 1 : 4 with

⁄2bias are

possible but the discrimination and hence the contrast

ratios are smaller ( = 1.732 for 1 : 3 multiplex or

21

= 1.528 for 1 : 4 multiplex).

---------3

3

The advantage of these modes is a reduction of the LCD full-scale voltage V

• 1 : 3 multiplex ( Vop= = 2.449 V

6V

×

as follows:

op

1

⁄2bias):

off rms〈〉

off(rms)

• 1 : 4 multiplex (1⁄2bias):

43×()

= = 2.309 V

V

op

--------------------- 3

These compare with Vop=3V

off(rms)

when1⁄3bias is used.

off(rms)

Table 1 Preferred LCD drive modes: summary of characteristics

LCD DRIVE MODE

NUMBER OF

BACKPLANES LEVELS

LCD BIAS

CONFIGURATION

V

off(rms)

-------------------- V

op

V

on(rms)

-------------------- V

op

D

static 1 2 static 0 1 ∞ 1:2 2 3 1:2 2 4 1:3 3 4 1:4 4 4

1

⁄

2

1

⁄

3

1

⁄

3

1

⁄

3

0.354 0.791 2.236

0.333 0.745 2.236

0.333 0.638 1.915

0.333 0.577 1.732

V

=

-------------------- V

on(rms)

off(rms)

2001 Oct 02 8

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

6.4 LCD drive mode waveforms

The static LCD drive mode is used when a single backplaneisprovidedintheLCD.Backplaneandsegment drive waveforms for this mode are shown in Fig.4.

When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The PCF8576 allows use of

1

⁄2bias or1⁄3bias in this mode as shown in Figs 5 and 6.

V

DD

BP0

V

LCD

V

DD

S

n

V

LCD

V

DD

S

n 1

V

LCD

(a) waveforms at driver

V

op

When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies, as shown in Fig.7.

When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies, as shown in Fig.8.

T

frame

LCD segments

state 1

(on)

state 2

(off)

state 1 0

V

op

V

op

state 2 0

V

op

(b) resultant waveforms

at LCD segment

V

t() V

state1

V

on(rms)Vop

t() V

V

state2

V

off(rms)

S

n

=

S

n1+

0V=

BP0

t() V

BP0

t()–=

Fig.4 Static drive mode waveforms (Vop=VDD− V

2001 Oct 02 9

MBE539

LCD

).

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

T

frame

V

(V )/2V

BP0

V V

(V )/2V

BP1

V V

S

n

V V

S

n 1

V

V V /2

state 1 0

V /2 V

V V /2

state 2

V /2 V

DD DD LCD

LCD DD

LCD

DD

LCD DD

LCD

op

op op

op

0

op

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

LCD segments

state 1 state 2

MBE540

V

t() V

op

t() V

op

BP0

BP1

t()–=

state1

V

on(rms)

V

state2

V

off(rms)

0.791V

=

t() V

0.354V

=

S

n

S

n

Fig.5 Waveforms for the 1 : 2 multiplex drive mode with1⁄2bias (Vop=VDD− V

2001 Oct 02 10

LCD

).

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

T

V

DD

V V /3

BP0

BP1

S

n

S

n 1

state 1 0

state 2 0

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

frame

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

LCD segments

state 1 state 2

MBE541

V

t() V

op

t() V

op

BP0

BP1

t()–=

state1

V

on(rms)

V

state2

V

off(rms)

0.745V

=

t() V

0.333V

=

S

n

S

n

Fig.6 Waveforms for the 1 : 2 multiplex drive mode with1⁄3bias (Vop=VDD− V

2001 Oct 02 11

LCD

).

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

T

V

V V /3

BP0

V 2V /3 V

V V V /3

BP1

V 2V /3 V

V

BP2/S23

V V /3 V 2V /3

V V

V V /3

S

n

V 2V /3 V

V

n 1

V V /3 V 2V /3

S

V V

n 2

V V /3 V 2V /3

S

V

2V /3 V /3

state 1 0

V /3 2V /3

V V

2V /3 V /3

state 2 0

V /3 2V /3

V

DD DD

DD LCD

DD DD

DD LCD

DD DD

DD LCD

DD DD

DD LCD

DD DD

DD LCD

DD DD

DD LCD

op

op op

op

frame

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

LCD segments

state 1 state 2

MBE542

V

t() V

op

t() V

op

BP0

BP1

t()–=

state1

V

on(rms)

V

state2

V

off(rms)

0.638V

=

t() V

0.333V

=

S

n

S

n

Fig.7 Waveforms for the 1 : 3 multiplex drive mode (Vop=VDD− V

2001 Oct 02 12

LCD

).

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

T

V

DD

V V /3

n

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

DD

V V /3

DD

V 2V /3

DD

V

LCD

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

V

op

2V /3

op

V /3

op

V /3

op

2V /3

op

V

op

BP0

BP1

BP2

BP3

S

n 1

S

n 2

S

n 3

state 1 0

state 2 0

op

frame

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

state 1 state 2

LCD segments

MBE543

V

state1

V

on(rms)

V

state2

V

off(rms)

t() V

0.577V

=

t() V

0.333V

=

S

t() V

n

t() V

n

t()–=

BP0

op

t()–=

BP1

op

Fig.8 Waveforms for the 1 : 4 multiplex drive mode (Vop=VDD− V

2001 Oct 02 13

LCD

).

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

6.5 Oscillator

6.5.1 INTERNAL CLOCK The internal logic and the LCD drive signals of the

PCF8576 are timed either by the internal oscillator or from an external clock. When the internal oscillator is used, pin OSC should be connected to pin VSS. In this event, the output from pin CLK provides the clock signal for cascaded PCF8566s in the system.

WhereresistorR

toVSSispresent,theinternaloscillator

osc

is selected. The relationship between the oscillator frequency on pin CLK (f

3

10

f

clk

(kHz)

2

10

min

) and R

clk

max

is shown in Fig.9.

osc

MBE531

6.6 Timing

ThetimingofthePCF8576organizestheinternaldataflow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal

SYNC maintains the correct timing relationship between the PCF8576s in the system. The timing also generates the LCD frame frequency which it derives as an integer multiple of the clock frequency (see Table 2). The frame frequency is set by the MODE SET commands when internal clock is used, or by the frequency applied to pin CLK when external clock is used.

The ratio between the clock frequency and the LCD frame frequency depends on the mode in which the device is operating. In the power-saving mode the reduction ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six. The reduced clock frequency results in a significant reduction in power dissipation. The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I2C-bus.

When a device is unable to digest a display data byte beforethe next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I2C-bus but no data loss occurs.

10

2

10



3.4 107×

f

----------------------- -



clk

R



osc

kHz()≈

3

10

R(kΩ)

osc

Fig.9 Oscillator frequency as a function of R

6.5.2 E

XTERNAL CLOCK

4

10

.

osc

The condition for external clock is made by connecting pin OSC to pin VDD; pin CLK then becomes the external clock input.

The clock frequency (f

) determines the LCD frame

clk

frequency and the maximum rate for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximumdata rate of 100 kHz, f

shouldbe chosen to be

clk

above 125 kHz. A clock signal must always be supplied to the device;

removing the clock may freeze the LCD in a DC state.

Table 2 LCD frame frequencies

NOMINAL

PCF8576 MODE

FRAME

FREQUENCY

FRAME

FREQUENCY

(Hz)

f

Normal mode

Power-saving mode 64

clk

------------ 2880

f

clk

--------- 480

64

6.7 Display latch

The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one column of the display RAM.

6.8 Shift register

The shift register serves to transfer display information from the display RAM to the display latch while previous data is displayed.

2001 Oct 02 14

Philips PCF8576U-10, PCF8576U-2, PCF8576U-5, PCF8576T, PCF8576U Datasheet

CONTENTS

1 FEATURES

2 GENERAL DESCRIPTION

3 ORDERING INFORMATION

4 BLOCK DIAGRAM

5 PINNING

6 FUNCTIONAL DESCRIPTION

6.1 Power-on reset

6.2 LCD bias generator

6.3 LCD voltage selector

6.4 LCD drive mode waveforms

6.5 Oscillator

6.5.1 INTERNAL CLOCK The internal logic and the LCD drive signals of the

6.6 Timing

6.7 Display latch

6.8 Shift register