Philips PCF8576 User Manual

DATA SH EET

Product speciﬁcation

Supersedes data of 1998 Feb 06

File under Integrated Circuits, IC12

2001 Oct 02

INTEGRATED CIRCUITS

PCF8576

Universal LCD driver for low

multiplex rates

2001 Oct 02 2

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

1 FEATURES

2 GENERAL DESCRIPTION

3 ORDERING INFORMATION

4 BLOCK DIAGRAM

5 PINNING

6 FUNCTIONAL DESCRIPTION

6.1 Power-on reset

6.2 LCD bias generator

6.3 LCD voltage selector

6.4 LCD drive mode waveforms

6.5 Oscillator

6.5.1 Internal clock

6.5.2 External clock

6.6 Timing

6.7 Display latch

6.8 Shift register

6.9 Segment outputs

6.10 Backplane outputs

6.11 Display RAM

6.12 Data pointer

6.13 Subaddress counter

6.14 Output bank selector

6.15 Input bank selector

6.16 Blinker

7 CHARACTERISTICS OF THE I

C-BUS

7.1 Bit transfer (see Fig.12)

7.2 START and STOP conditions (see Fig.13)

7.3 System configuration (see Fig.14)

7.4 Acknowledge (see Fig.15)

7.5 PCF8576 I

C-bus controller

7.6 Input filters

7.7 I

C-bus protocol

7.8 Command decoder

7.9 Display controller

7.10 Cascaded operation

8 LIMITING VALUES

9 HANDLING

10 DC CHARACTERISTICS

11 AC CHARACTERISTICS

11.1 Typical supply current characteristics

11.2 Typical characteristics of LCD outputs

12 APPLICATION INFORMATION

12.1 Chip-on-glass cascadability in single plane

13 BONDING PAD INFORMATION

14 TRAY INFORMATION: PCF8576U

15 TRAY INFORMATION: PCF8576U/2

16 PACKAGE OUTLINES

17 SOLDERING

17.1 Introduction to soldering surface mount

packages

17.2 Reflow soldering

17.3 Wave soldering

17.4 Manual soldering

17.5 Suitability of surface mount IC packages for

wave and reflow soldering methods

18 DATA SHEET STATUS

19 DEFINITIONS

20 DISCLAIMERS

21 PURCHASE OF PHILIPS I

C COMPONENTS

2001 Oct 02 3

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

1 FEATURES

• Single-chip LCD controller/driver

• Selectable backplanedrive configuration: static or 2/3/4

backplane multiplexing

• Selectable display bias configuration: static,

⁄

• Internal LCD bias generation with voltage-follower

buffers

• 40 segment drives: up to twenty 8-segment numeric

characters; up to ten 15-segment alphanumeric

characters; or any graphics of up to 160 elements

• 40 × 4-bit RAM for display data storage

• Auto-incremented display data loading across device

subaddress boundaries

• Display memory bank switching in static and duplex

drive modes

• Versatile blinking modes

• LCD and logic supplies may be separated

• Wide power supply range: from 2 V for low-threshold

LCDs and up to 9 V for guest-host LCDs and

high-threshold (automobile) twisted nematic LCDs

• Low power consumption

• Power-saving mode for extremely low power

consumption in battery-operated and telephone

applications

• I

C-bus interface

• TTL/CMOS compatible

• Compatible with any 4-bit, 8-bit or 16-bit

microprocessors/microcontrollers

• May be cascaded for large LCD applications (up to

2560 segments possible)

• Cascadable with 24-segment LCD driver PCF8566

• Optimized pinning for plane wiring in both single and

multiple PCF8576 applications

• Space-saving56-leadplasticverysmalloutlinepackage

(VSO56)

• Very low external component count (at most one

resistor, even in multiple device applications)

• Compatible with chip-on-glass technology

• Manufactured in silicon gate CMOS process.

2 GENERAL DESCRIPTION

The PCF8576 is a peripheral device which interfaces to

almost any Liquid Crystal Display (LCD) with low multiplex

rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up

to40 segmentsandcaneasily be cascaded for larger LCD

applications. The PCF8576 is compatible with most

microprocessors/microcontrollersandcommunicatesvia a

two-line bidirectional I

C-bus. Communication overheads

are minimized by a display RAM with auto-incremented

addressing, by hardware subaddressing and by display

memory switching (static and duplex drive modes).

3 ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF8576T VSO56 plastic very small outline package; 56 leads SOT190-1

PCF8576U − chip in tray −

PCF8576U/2 − chip with bumps in tray −

PCF8576U/5 − unsawn wafer −

PCF8576U/10 FFC chip on ﬁlm frame carrier (FFC) −

PCF8576U/12 FFC chip with bumps on ﬁlm frame carrier (FFC) −

2001 Oct 02 4

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

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4 BLOCK DIAGRAM

handbook, full pagewidth

MBK276

LCD

VOLTAGE

SELECTOR

LCD

TIMING BLINKER

OSCILLATOR

INPUT

FILTERS

I C - BUS

CONTROLLER

POWER-

RESET

CLK

SYNC

OSC

SCL

SDA

SA0

DISPLAY

CONTROLLER

COMMAND

DECODER

BACKPLANE

OUTPUTS

BP0

BP2

BP1

BP3

INPUT

BANK

SELECTOR

DISPLAY

RAM

40 x 4 BITS

OUTPUT

BANK

SELECTOR

DATA

POINTER

SUB-

ADDRESS

COUNTER

DISPLAY SEGMENT OUTPUTS

DISPLAY LATCH

SHIFT REGISTER

17 to 56

S0 to S39

PCF8576

LCD BIAS

GENERATOR

Fig.1 Block diagram (for VSO56 package; SOT190-1).

2001 Oct 02 5

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

5 PINNING

SYMBOL PIN DESCRIPTION

SDA 1 I

C-bus serial data input/output

SCL 2 I

C-bus serial clock input

SYNC 3 cascade synchronization input/output

CLK 4 external clock input/output

5 supply voltage

OSC 6 oscillator input

A0 to A2 7 to 9 I

C-bus subaddress inputs

SA0 10 I

C-bus slave address input; bit 0

11 logic ground

LCD

12 LCD supply voltage

BP0, BP2, BP1 and BP3 13 to 16 LCD backplane outputs

S0 to S39 17 to 56 LCD segment outputs

2001 Oct 02 6

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

Fig.2 Pin configuration; SOT190-1.

handbook, halfpage

PCF8576T

MBK278

SDA

SCL

SYNC

CLK

OSC

SA0

BP0

BP2

BP1

BP3

S10

S11

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

S29

S28

S27

S26

S25

S24

S23

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

LCD

2001 Oct 02 7

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

6 FUNCTIONAL DESCRIPTION

The PCF8576 is a versatile peripheral device designed to

interface to any microprocessor/microcontroller to a wide

variety of LCDs. It can directly drive any static or

multiplexed LCD containing up to four backplanes and up

to 40 segments. The display configurations possible with

the PCF8576 depend on the number of active backplane

outputs required; a selection of display configurations is

given in Table .

All of the display configurations given in Table can be

implemented in the typical system shown in Fig.3.

The host microprocessor/microcontroller maintains the

2-line I

C-bus communication channel with the PCF8576.

The internal oscillator is selected by connecting pin OSC

to pin V

. The appropriate biasing voltages for the

multiplexed LCD waveforms are generated internally. The

only other connections required to complete the system

are to the power supplies (V

, V

and V

LCD

) and the

LCD panel chosen for the application.

Selection of display conﬁgurations

NUMBER OF 7-SEGMENTS NUMERIC

14-SEGMENTS

ALPHANUMERIC

DOT MATRIX

BACKPLANES SEGMENTS DIGITS

INDICATOR

SYMBOLS

CHARACTERS

INDICATOR

SYMBOLS

4 160 20 20 10 20 160 dots (4 × 40)

3 120 15 15 8 8 120 dots (3 × 40)

2 80 10 10 5 10 80 dots (2 × 40)

1 40552 1240dots (1 × 40)

Fig.3 Typical system configuration.

handbook, full pagewidth

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

OSC

1 17 to 56

13 to 16

512

91011

40 segment drives

4 backplanes

LCD PANEL

(up to 160

elements)

PCF8576

A0 A1 A2

SA0 V

LCD

MBK277

2001 Oct 02 8

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

6.1 Power-on reset

At power-on the PCF8576 resets to a starting condition as

follows:

1. All backplane outputs are set to V

2. All segment outputs are set to V

3. Thedrive mode ‘1 : 4 multiplex with

⁄

bias’ is selected.

4. Blinking is switched off.

5. Input and output bank selectors are reset (as defined

in Table 4).

6. The I

C-bus interface is initialized.

7. The data pointer and the subaddress counter are

cleared.

Data transfers on the I

C-bus should be avoided for 1 ms

following power-on to allow completion of the reset action.

6.2 LCD bias generator

The full-scale LCD voltage (V

) is obtained from

− V

LCD

. The LCD voltage may be temperature

compensatedexternallythroughtheV

LCD

supplytopin 12.

Fractional LCD biasing voltages are obtained from an

internal voltage divider of the three series resistors

connectedbetween V

andV

LCD

.The centre resistor can

be switched out of the circuit to provide a

⁄

bias voltage

level for the 1 : 2 multiplex configuration.

6.3 LCD voltage selector

The LCD voltage selector co-ordinates the multiplexing of

the LCD in accordance with the selected LCD drive

configuration. The operation of the voltage selector is

controlled by MODE SET commands from the command

decoder. The biasing configurations that apply to the

preferred modes of operation, together with the biasing

characteristics as functions of V

− V

LCD

and the

resulting discrimination ratios (D), are given in Table 1.

A practical value for V

is determined by equating V

off(rms)

with a defined LCD threshold voltage (V

), typically when

the LCD exhibits approximately 10% contrast. In the static

drive mode a suitable choice is V

>3V

approximately.

Multiplex drive ratios of 1 : 3 and 1 : 4 with

⁄

bias are

possible but the discrimination and hence the contrast

ratios are smaller ( = 1.732 for 1 : 3 multiplex or

= 1.528 for 1 : 4 multiplex).

The advantage of these modes is a reduction of the LCD

full-scale voltage V

as follows:

• 1 : 3 multiplex (

⁄

bias):

= = 2.449 V

off(rms)

• 1 : 4 multiplex (

⁄

bias):

= = 2.309 V

off(rms)

These compare with V

=3V

off(rms)

when

⁄

bias is used.

----------

off rms〈〉

43×()

--------------------- -

Table 1 Preferred LCD drive modes: summary of characteristics

LCD DRIVE MODE

NUMBER OF

LCD BIAS

CONFIGURATION

BACKPLANES LEVELS

static 1 2 static 0 1 ∞

1:2 2 3

⁄

0.354 0.791 2.236

1:2 2 4

⁄

0.333 0.745 2.236

1:3 3 4

⁄

0.333 0.638 1.915

1:4 4 4

⁄

0.333 0.577 1.732

off(rms)

-------------------- -

on(rms)

-------------------- -

on(rms)

off(rms)

-------------------- -

2001 Oct 02 9

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

6.4 LCD drive mode waveforms

The static LCD drive mode is used when a single

backplaneisprovidedintheLCD.Backplaneandsegment

drive waveforms for this mode are shown in Fig.4.

When two backplanes are provided in the LCD, the 1 : 2

multiplex mode applies. The PCF8576 allows use of

⁄

bias or

⁄

bias in this mode as shown in Figs 5 and 6.

When three backplanes are provided in the LCD, the 1 : 3

multiplex drive mode applies, as shown in Fig.7.

When four backplanes are provided in the LCD, the 1 : 4

multiplex drive mode applies, as shown in Fig.8.

state1

t() V

BP0

t()–=

on(rms)

state2

t() V

n1+

t() V

BP0

t()–=

off(rms)

0V=

Fig.4 Static drive mode waveforms (V

− V

LCD

MBE539

LCD

state 1 0

BP0

n 1

state 2 0

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

LCD segments

state 1

(on)

state 2

(off)

frame

2001 Oct 02 10

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

Fig.5 Waveforms for the 1 : 2 multiplex drive mode with

⁄

bias (V

− V

LCD

state1

t() V

BP0

t()–=

on(rms)

0.791V

state2

t() V

BP1

t()–=

off(rms)

0.354V

MBE540

(V )/2V

V /2

state 1 0

BP0

n 1

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

LCD segments

state 2

frame

DD LCD

LCD

BP1

V /2

state 2

V /2

state 1

(V )/2V

LCD

2001 Oct 02 11

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

Fig.6 Waveforms for the 1 : 2 multiplex drive mode with

⁄

bias (V

− V

LCD

state1

t() V

BP0

t()–=

on(rms)

0.745V

state2

t() V

BP1

t()–=

off(rms)

0.333V

MBE541

2V /3

state 1 0

BP0

n 1

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

LCD segments

state 2

frame

V V /3

LCD

BP1

state 1

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V /3

2V /3

V /3

2V /3

state 2 0

V /3

2V /3

V /3

2001 Oct 02 12

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

MBE542

2V /3

state 1 0

BP0

(b) resultant waveforms

at LCD segment

LCD segments

state 2

frame

BP1

state 1

V /3

2V /3

V /3

2V /3

state 2 0

V /3

2V /3

V /3

n 1

n 2

(a) waveforms at driver

BP2/S23

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

Fig.7 Waveforms for the 1 : 3 multiplex drive mode (V

− V

LCD

state1

t() V

BP0

t()–=

on(rms)

0.638V

state2

t() V

BP1

t()–=

off(rms)

0.333V

2001 Oct 02 13

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

Fig.8 Waveforms for the 1 : 4 multiplex drive mode (V

− V

LCD

MBE543

2V /3

state 1 0

BP0

(b) resultant waveforms

at LCD segment

LCD segments

state 2

frame

BP1

state 1

V /3

2V /3

V /3

2V /3

state 2 0

V /3

2V /3

V /3

n 1

BP2

n 2

n 3

(a) waveforms at driver

BP3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

V V /3

LCD

V 2V /3

state1

t() V

BP0

t()–=

on(rms)

0.577V

state2

t() V

BP1

t()–=

off(rms)

0.333V

2001 Oct 02 14

Philips Semiconductors Product speciﬁcation

Universal LCD driver for low multiplex rates PCF8576

6.5 Oscillator

6.5.1 INTERNAL CLOCK

The internal logic and the LCD drive signals of the

PCF8576 are timed either by the internal oscillator or from

an external clock. When the internal oscillator is used,

pin OSC should be connected to pin V

. In this event, the

output from pin CLK provides the clock signal for

cascaded PCF8566s in the system.

WhereresistorR

osc

toV

ispresent,theinternaloscillator

is selected. The relationship between the oscillator

frequency on pin CLK (f

clk

) and R

osc

is shown in Fig.9.

6.5.2 E

XTERNAL CLOCK

The condition for external clock is made by connecting

pin OSC to pin V

; pin CLK then becomes the external

clock input.

The clock frequency (f

clk

) determines the LCD frame

frequency and the maximum rate for data reception from

the I

C-bus. To allow I

C-bus transmissions at their

maximumdata rate of 100 kHz, f

clk

shouldbe chosen to be

above 125 kHz.

A clock signal must always be supplied to the device;

removing the clock may freeze the LCD in a DC state.

6.6 Timing

ThetimingofthePCF8576organizestheinternaldataflow

of the device. This includes the transfer of display data

from the display RAM to the display segment outputs. In

cascaded applications, the synchronization signal

SYNC

maintains the correct timing relationship between the

PCF8576s in the system. The timing also generates the

LCD frame frequency which it derives as an integer

multiple of the clock frequency (see Table 2). The frame

frequency is set by the MODE SET commands when

internal clock is used, or by the frequency applied to

pin CLK when external clock is used.

The ratio between the clock frequency and the LCD frame

frequency depends on the mode in which the device is

operating. In the power-saving mode the reduction ratio is

six times smaller; this allows the clock frequency to be

reduced by a factor of six. The reduced clock frequency

results in a significant reduction in power dissipation. The

lower clock frequency has the disadvantage of increasing

the response time when large amounts of display data are

transmitted on the I

C-bus.

When a device is unable to digest a display data byte

beforethe next one arrives, it holds the SCL line LOW until

the first display data byte is stored. This slows down the

transmission rate of the I

C-bus but no data loss occurs.

Table 2 LCD frame frequencies

6.7 Display latch

The display latch holds the display data while the

corresponding multiplex signals are generated. There is a

one-to-one relationship between the data in the display

latch, the LCD segment outputs and one column of the

display RAM.

6.8 Shift register

The shift register serves to transfer display information

from the display RAM to the display latch while previous

data is displayed.

Fig.9 Oscillator frequency as a function of R

osc

clk

3.4 10

osc

----------------------- -







kHz()≈

MBE531

clk

(kHz)

R(kΩ)

osc

min

max

PCF8576 MODE

FRAME

FREQUENCY

NOMINAL

FRAME

FREQUENCY

(Hz)

Normal mode

Power-saving mode 64

clk

2880

------------ -

clk

480

--------- -

+ 30 hidden pages

Philips PCF8576 User Manual

CONTENTS

1 FEATURES

2 GENERAL DESCRIPTION

3 ORDERING INFORMATION

4 BLOCK DIAGRAM

5 PINNING

6 FUNCTIONAL DESCRIPTION

6.1 Power-on reset

6.2 LCD bias generator

6.3 LCD voltage selector

6.4 LCD drive mode waveforms

6.5 Oscillator

6.5.1 INTERNAL CLOCK

6.6 Timing

6.7 Display latch

6.8 Shift register