Philips pcf8573 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

PCF8573

Clock/calendar with serial I/O

Product speciﬁcation File under Integrated Circuits, IC01

May 1989

Philips Semiconductors Product speciﬁcation

Clock/calendar with serial I/O PCF8573

GENERAL DESCRIPTION

The PCF8573 is a low threshold, CMOS circuit that functions as a real time clock/calendar with an I2C-bus interface. The IC incorporates an addressable time counter and an addressable alarm register for minutes, hours, days and months. Three special control/status flags, COMP, POWF and NODA, are also available. Information is transferred via a serial two-line bidirectional bus (I2C). Back-up for the clock during supply interruptions is provided by a 1.2 V nickel cadium battery. The time base is generated from a 32.768 kHz crystal-controlled oscillator.

Features

• Serial input/output I days and months

• Additional pulse outputs for seconds and minutes

• Alarm register for presetting a time for alarm or remote

switching functions

• Battery back-up for clock function during supply interruption

• Crystal oscillator control (32.768 kHz)

C-bus interface for minutes, hours,

QUICK REFERENCE DATA

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Supply voltage range

clock (pin 16 to pin 15) V

C interface (pin 16 to pin 8) VDD−V

Crystal oscillator frequency f

DD−VSS1

SS2

osc

1.1 − 6.0 V

2.5 − 6.0 V

− 32.768 − kHz

PACKAGE OUTLINES

PCF8573P: 16-lead DIL; plastic (SOT38); SOT38-1; 1996 August 23. PCF8573T: 16-lead mini-pack; plastic (SO16L; SOT162A); SOT162-1; 1996 August 23.

May 1989 2

Philips Semiconductors Product speciﬁcation

Clock/calendar with serial I/O PCF8573

Fig.1 Block diagram.

PINNING

1 A0 address input 2 A1 address input 3 COMP comparator output

4 SDA serial data line; I 5 SCL serial clock line; I

C-bus

C-bus 6 EXTPF enable power fail ﬂag input 7 PFIN power fail ﬂag input 8V

SS2

negative supply 2 (I2C interface) 9 MIN one pulse per minute output 10 SEC one pulse per second output 11 FSET oscillator tuning output 12 TEST test input; must be connected to

when not in use

SS2

13 OSCI oscillator input 14 OSCO oscillator input/output 15 V 16 V

SS1 DD

negative supply 1 (clock)

common positive supply

Fig.2 Pinning diagram.

May 1989 3

Philips Semiconductors Product speciﬁcation

Clock/calendar with serial I/O PCF8573

FUNCTIONAL DESCRIPTION Oscillator

The PCF8573 has an integrated crystal-controlled oscillator which provides the timebase for the prescaler. The frequency is determined by a single 32.768 kHz crystal connected between OSCI and OSCO. A trimmer is connected between OSCI and V

Prescaler and time counter

The prescaler provides a 128 Hz signal at the FSET output for fine adjustment of the crystal oscillator without loading it. The prescaler also generates a pulse once a second to advance the seconds counter. The carry of the prescaler and the seconds counter are available at the outputs SEC, MIN respectively, and are also readable via the I mark-to-space ratio of both signals is 1 : 1. The time counter is advanced one count by the falling edge of output signal MIN. A transition from HIGH-to-LOW of output signal SEC triggers MIN to change state. The time counter counts minutes, hours, days and months, and provides a full calendar function which needs to be corrected once every four years. Cycle lengths are shown in Table 1.

Table 1 Cycle length of the time counter

C-bus. The

UNIT NUMBER OF BITS COUNTING CYCLE

CARRY FOR

FOLLOWING UNIT

CONTENT OF MONTH

COUNTER

minutes 7 00 to 59 59 → 00 hours 6 00 to 23 23 → 00 days 6 01 to 28 28 → 01 2 (note 1)

or 29 → 01 2 (note 1) 01 to 30 30 → 01 4, 6, 9, 11 01 to 31 31 → 01 1, 3, 5, 7, 8, 10, 12

months 5 01 to 12 12 → 01

Note to Table 1

1. Day counter may be set to 29 by a write transmission with EXECUTE ADDRESS.

Alarm register

The alarm register is a 24-bit memory. It stores the time-point for the next setting of the status flag COMP. Details of writing and reading of the alarm register are included in the description of the characteristics of the I

C-bus.

Comparator

The comparator compares the contents of the alarm register and the time counter. each with a length of 24 bits. When these contents are equal the flag COMP will be set 4 ms after the falling edge of MIN. This set condition occurs once at

the beginning of each minute. This information is latched, but can be cleared by an instruction via the I

C-bus. A clear instruction may be transmitted immediately after the flag is set and will be executed. Flag COMP information is also available at the output COMP. The comparison may be based upon hours and minutes only if the internal flag NODA (no date) is set. Flag NODA can be set and cleared by separate instructions via the I2C-bus, but it is undefined until the first set or clear instruction has been received. Both COMP and NODA flags are readable via the I2C-bus.

May 1989 4

Philips Semiconductors Product speciﬁcation

Clock/calendar with serial I/O PCF8573

Power on/power fail detection

If the voltage VDD−V

falls below a certain value the operation of the clock becomes undefined. Thus a warning signal

SS1

is required to indicate that faultless operation of the clock is not guaranteed. This information is latched in a flag called POWF (Power Fail) and remains latched after restoration of the correct supply voltage until a write procedure with EXECUTE ADDRESS has been received. The flag POWF can be set by an internally generated power fail level-discriminator signal for application with (VDD−V signal for application with (VDD−V

) less than V

SS1

) greater than V

SS1

. The external signal must be applied to the input PFIN. The input

TH1

, or by an externally generated power fail

TH1

stage operates with signals of any slow rise and fall times. Internally or externally controlled POWF can be selected by input EXTPF as shown in Table 2.

Table 2 Power fail selection

EXTPF PFIN FUNCTION

0 0 power fail is sensed internally 0 1 test mode 1 0 power fail is sensed externally 1 1 no power fail sensed

0 : connected to V

SS1

(LOW) 1 : connected to VDD (HIGH) The external power fail control operates by absence of the VDD−V

and EXTPF must be within the range of VDD−V

. A LOW level at PFIN indicates a power fail. POWF is readable via

SS1

the I2C-bus. A power on reset for the I2C-bus control is generated on-chip when the supply voltage VDD−V V

TH2

supply. Therefore the input levels applied to PFIN

SS2

is less than

SS2

Interface level shifters

The level shifters adjust the 5 V operating voltage (V (VDD−V voltage VDD−V of the VDD−V

) of the clock/calendar. The oscillator and counter are not influenced by the VDD−V

SS1

is absent (VDD = V

SS2

and the VDD−V

SS2

SS1

) the output signal of the level shifter is HIGH because VDD is the common node

SS2

supplies. Because the level shifters invert the input signals, the internal circuit

DD−VSS2

) of the microcontroller to the internal supply voltage

supply voltage. If the

SS2

behaves as if a LOW signal is present on the inputs. FSET, SEC, MIN and COMP are CMOS push-pull output stages. The driving capability of these outputs is lost when the supply voltage VDD−V

SS2

= 0.

May 1989 5

Philips Semiconductors Product speciﬁcation

Clock/calendar with serial I/O PCF8573

CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

Bit transfer (see Fig.3) One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period

of the clock pulse as changes in data line at this time will be interpreted as control signals.

Fig.3 Bit transfer.

Start and stop conditions (see Fig.4) Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P).

Fig.4 Definition of start and stop conditions.

System conﬁguration (see Fig.5) A device generating a message is a “transmitter”, a device receiving a message is the “receiver”. The device that controls

the message is the “master” and the devices which are controlled by the master are the “slaves”.

May 1989 6

Fig.5 System configuration.

Philips Semiconductors Product speciﬁcation

Clock/calendar with serial I/O PCF8573

Acknowledge (see Fig.6) The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited.

Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. (See Fig.10 and Fig.11).

Fig.6 Acknowledge on the I2C-bus.

May 1989 7

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