INTEGRATED CIRCUITS
P89C51RB2/P89C51RC2/P89C51RD2
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
Preliminary specification |
1999 Nov 22 |
IC28 Data Handbook
P s
on o s
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
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DESCRIPTION
The P89C51RB2/RC2/RD2 device contains a non-volatile 16kB/32kB/64kB Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable. In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application. In-Application Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming over a modem link.
A default serial loader (boot loader) program in ROM allows serial
In-System programming of the Flash memory via the UART without the need for a loader in the Flash code. For In-Application Programming, the user program erases and reprograms the Flash memory by use of standard routines contained in ROM.
This device executes one machine cycle in 6 clock cycles, hence providing twice the speed of a conventional 80C51. An OTP configuration bit lets the user select conventional 12 clock timing if desired.
This device is a Single-Chip 8-Bit Microcontroller manufactured in advanced CMOS process and is a derivative of the 80C51 microcontroller family. The instruction set is 100% compatible with the 80C51 instruction set.
The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits.
The added features of the P89C51RB2/RC2/RD2 makes it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control.
FEATURES
•80C51 Central Processing Unit
•On-chip Flash Program Memory with In-System Programming
(ISP) and In-Application Programming (IAP) capability
•Boot ROM contains low level Flash programming routines for downloading via the UART
•Can be programmed by the end-user application (IAP)
•6 clocks per machine cycle operation (standard)
•12 clocks per machine cycle operation (optional)
•Speed up to 20 MHz with 6 clock cycles per machine cycle (40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle
•Fully static operation
•RAM expandable externally to 64 kB
•4 level priority interrupt
•7 interrupt sources
•Four 8-bit I/O ports
•Full-duplex enhanced UART
±Framing error detection
±Automatic address recognition
•Power control modes
±Clock can be stopped and resumed
±Idle mode
±Power down mode
•Programmable clock out
•Second DPTR register
•Asynchronous port reset
•Low EMI (inhibit ALE)
•Programmable Counter Array (PCA)
±PWM
±Capture/compare
1999 Nov 22 |
2 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
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ORDERING INFORMATION
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PHILIPS |
PHILIPS |
MEMORY |
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FREQUENCY (MHz) |
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(EXCEPT NORTH |
TEMPERATURE |
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NORTH |
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AMERICA) |
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VOLTAGE |
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PART ORDER |
AMERICA |
FLASH |
RAM |
RANGE (°C) |
RANGE |
6 CLOCK |
12 CLOCK |
DWG # |
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PART ORDER |
AND PACKAGE |
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NUMBER |
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MODE |
MODE |
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PART MARKING |
NUMBER |
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1 |
P89C51RB2HBP |
P89C51RB2BP |
16 kB |
512 B |
0 to +70, PDIP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT129-1 |
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2 |
P89C51RB2HFP |
P89C51RB2FP |
16 kB |
512 B |
±40 to +85, PDIP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT129-1 |
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3 |
P89C51RB2HBA |
P89C51RB2BA |
16 kB |
512 B |
0 to +70, PLCC |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT187-2 |
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4 |
P89C51RB2HFA |
P89C51RB2FA |
16 kB |
512 B |
±40 to +85, PLCC |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT187-2 |
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5 |
P89C51RB2HBB |
P89C51RB2BB |
16 kB |
512 B |
0 to +70, PQFP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT307-2 |
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6 |
P89C51RB2HFB |
P89C51RB2FB |
16 kB |
512 B |
±40 to +85, PQFP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT307-2 |
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7 |
P89C51RC2HBP |
P89C51RC2BP |
32 kB |
512 B |
0 to +70, PDIP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT129-1 |
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8 |
P89C51RC2HFP |
P89C51RC2FP |
32 kB |
512 B |
±40 to +85, PDIP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT129-1 |
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9 |
P89C51RC2HBA |
P89C51RC2BA |
32 kB |
512 B |
0 to +70, PLCC |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT187-2 |
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10 |
P89C51RC2HFA |
P89C51RC2FA |
32 kB |
512 B |
±40 to +85, PLCC |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT187-2 |
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11 |
P89C51RC2HBB |
P89C51RC2BB |
32 kB |
512 B |
0 to +70, PQFP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT307-2 |
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12 |
P89C51RC2HFB |
P89C51RC2FB |
32 kB |
512 B |
±40 to +85, PQFP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT307-2 |
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13 |
P89C51RD2HBP |
P89C51RD2BP |
64 kB |
1 kB |
0 to +70, PDIP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT129-1 |
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14 |
P89C51RD2HFP |
P89C51RD2FP |
64 kB |
1 kB |
±40 to +85, PDIP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT129-1 |
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15 |
P89C51RD2HBA |
P89C51RD2BA |
64 kB |
1 kB |
0 to +70, PLCC |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT187-2 |
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16 |
P89C51RD2HFA |
P89C51RD2FA |
64 kB |
1 kB |
±40 to +85, PLCC |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT187-2 |
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17 |
P89C51RD2HBB |
P89C51RD2BB |
64 kB |
1 kB |
0 to +70, PQFP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT307-2 |
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18 |
P89C51RD2HFB |
P89C51RD2FB |
64 kB |
1 kB |
±40 to +85, PQFP |
4.5±5.5 V |
0 to 20 MHz |
0 to 33 MHz |
SOT307-2 |
1999 Nov 22 |
3 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
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BLOCK DIAGRAM
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P0.0±P0.7 |
P2.0±P2.7 |
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PORT 0 |
PORT 2 |
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DRIVERS |
DRIVERS |
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VCC |
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VSS |
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RAM ADDR |
RAM |
PORT 0 |
PORT 2 |
FLASH |
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REGISTER |
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LATCH |
LATCH |
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8 |
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B |
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ACC |
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STACK |
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REGISTER |
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POINTER |
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PROGRAM |
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TMP1 |
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ADDRESS |
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TMP2 |
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REGISTER |
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ALU |
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BUFFER |
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SFRs |
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TIMERS |
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PC |
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PSW |
P.C.A. |
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INCRE- |
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MENTER |
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8 |
16 |
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PROGRAM |
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COUNTER |
PSEN |
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INSTRUCTION |
REGISTER |
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ALE |
TIMING |
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DPTR'S |
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EAVPP |
AND |
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MULTIPLE |
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CONTROL |
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RST |
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PD |
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PORT 1 |
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PORT 3 |
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LATCH |
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LATCH |
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OSCILLATOR |
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PORT 1 |
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PORT 3 |
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DRIVERS |
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DRIVERS |
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XTAL1 |
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XTAL2 |
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P1.0±P1.7 |
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P3.0±P3.7 |
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SU01065 |
1999 Nov 22 |
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4 |
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Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
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LOGIC SYMBOL
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VCC |
VSS |
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XTAL1 |
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0 |
ADDRESS AND |
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PORT |
DATA BUS |
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XTAL2 |
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T2 |
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1 |
T2EX |
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RST |
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PORT |
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EA/VPP |
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PSEN |
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FUNCTIONSSECONDARY |
ALE/PROG |
2PORT |
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RxD |
3PORT |
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TxD |
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INT0 |
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INT1 |
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ADDRESS BUS |
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T0 |
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T1 |
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WR |
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RD |
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SU01302 |
PINNING
Plastic Dual In-Line Package
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T2/P1.0 |
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VCC |
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1 |
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40 |
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T2EX/P1.1 |
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2 |
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39 |
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P0.0/AD0 |
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ECI/P1.2 |
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3 |
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38 |
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P0.1/AD1 |
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CEX0/P1.3 |
4 |
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37 |
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P0.2/AD2 |
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CEX1/P1.4 |
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36 |
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P0.3/AD3 |
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CEX2/P1.5 |
6 |
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35 |
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P0.4/AD4 |
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CEX3/P1.6 |
7 |
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34 |
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P0.5/AD5 |
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CEX4/P1.7 |
8 |
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33 |
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P0.6/AD6 |
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RST |
9 |
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32 |
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P0.7/AD7 |
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DUAL |
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RxD/P3.0 |
10 |
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31 |
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EA/VPP |
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IN-LINE |
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TxD/P3.1 |
11 |
PACKAGE |
30 |
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ALE/PROG |
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12 |
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29 |
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INT0/P3.2 |
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PSEN |
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13 |
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28 |
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P2.7/A15 |
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INT1/P3.3 |
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T0/P3.4 |
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27 |
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P2.6/A14 |
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T1/P3.5 |
15 |
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26 |
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P2.5/A13 |
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16 |
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25 |
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P2.4/A12 |
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WR/P3.6 |
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17 |
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24 |
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P2.3/A11 |
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RD/P3.7 |
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XTAL2 |
18 |
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23 |
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P2.2/A10 |
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XTAL1 |
19 |
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22 |
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P2.1/A9 |
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VSS |
20 |
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21 |
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P2.0/A8 |
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Plastic Leaded Chip Carrier
6 |
1 |
40 |
7 |
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39 |
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LCC |
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17 |
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29 |
18 |
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28 |
Pin |
Function |
Pin |
Function |
Pin |
Function |
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1 |
NIC* |
16 |
P3.4/T0 |
31 |
P2.7/A15 |
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2 |
P1.0/T2 |
17 |
P3.5/T1 |
32 |
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PSEN |
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3 |
P1.1/T2EX |
18 |
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P3.6/WR |
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33 |
ALE/PROG |
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4 |
P1.2/ECI |
19 |
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34 |
NIC* |
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P3.7/RD |
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5 |
P1.3/CEX0 |
20 |
XTAL2 |
35 |
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EA/VPP |
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6 |
P1.4/CEX1 |
21 |
XTAL1 |
36 |
P0.7/AD7 |
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7 |
P1.5/CEX2 |
22 |
VSS |
37 |
P0.6/AD6 |
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8 |
P1.6/CEX3 |
23 |
NIC* |
38 |
P0.5/AD5 |
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9 |
P1.7/CEX4 |
24 |
P2.0/A8 |
39 |
P0.4/AD4 |
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10 |
RST |
25 |
P2.1/A9 |
40 |
P0.3/AD3 |
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11 |
P3.0/RxD |
26 |
P2.2/A10 |
41 |
P0.2/AD2 |
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12 |
NIC* |
27 |
P2.3/A11 |
42 |
P0.1/AD1 |
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13 |
P3.1/TxD |
28 |
P2.4/A12 |
43 |
P0.0/AD0 |
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14 |
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29 |
P2.5/A13 |
44 |
VCC |
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P3.2/INT0 |
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15 |
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30 |
P2.6/A14 |
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P3.3/INT1 |
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* NO INTERNAL CONNECTION |
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SU00023 |
Plastic Quad Flat Pack
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44 |
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34 |
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1 |
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33 |
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PQFP |
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11 |
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12 |
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22 |
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23 |
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Pin |
Function |
Pin |
Function |
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Pin |
Function |
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1 |
P1.5/CEX2 |
16 |
VSS |
31 |
P0.6/AD6 |
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2 |
P1.6/CEX3 |
17 |
NIC* |
32 |
P0.5/AD5 |
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3 |
P1.7/CEX4 |
18 |
P2.0/A8 |
33 |
P0.4/AD4 |
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4 |
RST |
19 |
P2.1/A9 |
34 |
P0.3/AD3 |
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5 |
P3.0/RxD |
20 |
P2.2/A10 |
35 |
P0.2/AD2 |
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6 |
NIC* |
21 |
P2.3/A11 |
36 |
P0.1/AD1 |
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7 |
P3.1/TxD |
22 |
P2.4/A12 |
37 |
P0.0/AD0 |
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8 |
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23 |
P2.5/A13 |
38 |
VCC |
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P3.2/INT0 |
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9 |
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24 |
P2.6/A14 |
39 |
NIC* |
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P3.3/INT1 |
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10 |
P3.4/T0 |
25 |
P2.7/A15 |
40 |
P1.0/T2 |
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11 |
P3.5/T1 |
26 |
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41 |
P1.1/T2EX |
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PSEN |
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12 |
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27 |
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42 |
P1.2/ECI |
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P3.6/WR |
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ALE/PROG |
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13 |
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28 |
NIC* |
43 |
P1.3/CEX0 |
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P3.7/RD |
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14 |
XTAL2 |
29 |
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44 |
P1.4/CEX1 |
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EA/VPP |
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15 |
XTAL1 |
30 |
P0.7/AD7 |
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* NO INTERNAL CONNECTION |
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SU00024 |
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SU00021
1999 Nov 22 |
5 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
|
|
PIN DESCRIPTIONS
MNEMONIC |
|
PIN NUMBER |
|
TYPE |
|
|
|
|
|
NAME AND FUNCTION |
||
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PDIP |
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PLCC |
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PQFP |
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VSS |
20 |
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22 |
|
16 |
I |
Ground: 0 V reference. |
|||||
VCC |
40 |
|
44 |
|
38 |
I |
Power Supply: This is the power supply voltage for normal, idle, and power-down |
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operation. |
|||||
P0.0±0.7 |
39±32 |
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43±36 |
|
37±30 |
I/O |
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s |
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written to them float and can be used as high-impedance inputs. Port 0 is also the |
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multiplexed low-order address and data bus during accesses to external program |
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and data memory. In this application, it uses strong internal pull-ups when emitting 1s. |
|||||
P1.0±P1.7 |
1±8 |
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2±9 |
|
40±44, |
I/O |
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins |
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1±3 |
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except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them |
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are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 |
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pins that are externally pulled low will source current because of the internal |
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pull-ups. (See DC Electrical Characteristics: IIL). |
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Alternate functions for 89C51RB2/RC2/RD2 Port 1 include: |
|||||
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1 |
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2 |
|
40 |
I/O |
|
T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable |
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Clock-Out) |
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2 |
|
3 |
|
41 |
I |
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T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control |
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3 |
|
4 |
|
42 |
I |
|
ECI (P1.2): External Clock Input to the PCA |
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4 |
|
5 |
|
43 |
I/O |
|
CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 |
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|
5 |
|
6 |
|
44 |
I/O |
|
CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 |
||||
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6 |
|
7 |
|
1 |
I/O |
|
CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 |
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7 |
|
8 |
|
2 |
I/O |
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CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 |
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8 |
|
9 |
|
3 |
I/O |
|
CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 |
||||
P2.0±P2.7 |
21±28 |
|
24±31 |
|
18±25 |
I/O |
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that |
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have 1s written to them are pulled high by the internal pull-ups and can be used as |
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inputs. As inputs, port 2 pins that are externally being pulled low will source current |
|||||
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because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 |
|||||
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emits the high-order address byte during fetches from external program memory |
|||||
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and during accesses to external data memory that use 16-bit addresses (MOVX |
|||||
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@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. |
|||||
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During accesses to external data memory that use 8-bit addresses (MOV @Ri), |
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port 2 emits the contents of the P2 special function register. |
|||||
P3.0±P3.7 |
10±17 |
|
11, |
|
5, 7±13 |
I/O |
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that |
|||||
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13±19 |
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have 1s written to them are pulled high by the internal pull-ups and can be used as |
|||||
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inputs. As inputs, port 3 pins that are externally being pulled low will source current |
|||||
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|
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because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves |
|||||
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|
|
|
the special features of the 89C51RB2/RC2/RD2, as listed below: |
|||||
|
10 |
|
11 |
|
5 |
I |
|
RxD (P3.0): Serial input port |
||||
|
11 |
|
13 |
|
7 |
O |
|
TxD (P3.1): Serial output port |
||||
|
12 |
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14 |
|
8 |
I |
|
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|
|
|
(P3.2): External interrupt |
|
|
|
|
INT0 |
||||||||
|
13 |
|
15 |
|
9 |
I |
|
|
|
|
(P3.3): External interrupt |
|
|
|
|
|
INT1 |
||||||||
|
14 |
|
16 |
|
10 |
I |
|
T0 (P3.4): Timer 0 external input |
||||
|
15 |
|
17 |
|
11 |
I |
|
T1 (P3.5): Timer 1 external input |
||||
|
16 |
|
18 |
|
12 |
O |
|
|
|
(P3.6): External data memory write strobe |
||
|
|
|
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WR |
||||||||
|
17 |
|
19 |
|
13 |
O |
|
|
(P3.7): External data memory read strobe |
|||
|
|
|
|
RD |
||||||||
RST |
9 |
|
10 |
|
4 |
I |
Reset: A high on this pin for two machine cycles while the oscillator is running, |
|||||
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|
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resets the device. An internal resistor to VSS permits a power-on reset using only |
|||||
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|
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|
|
|
|
an external capacitor to VCC. |
|||||
ALE |
30 |
|
33 |
|
27 |
O |
Address Latch Enable: Output pulse for latching the low byte of the address |
|||||
|
|
|
|
|
|
|
during an access to external memory. In normal operation, ALE is emitted twice |
|||||
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|
|
every machine cycle, and can be used for external timing or clocking. Note that one |
|||||
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|
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ALE pulse is skipped during each access to external data memory. ALE can be |
|||||
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disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a |
|||||
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MOVX instruction. |
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|
|
1999 Nov 22 |
6 |
Philips Semiconductors Preliminary specification
|
80C51 8-bit Flash microcontroller family |
|
|
P89C51RB2/P89C51RC2/ |
|||||||||||||||||||
|
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
|
|
|
|
|
|
P89C51RD2 |
|||||||||||||||
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MNEMONIC |
|
PIN NUMBER |
|
TYPE |
|
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|
|
|
|
NAME AND FUNCTION |
|||||||||||
|
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||||||||||||
PDIP |
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PLCC |
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PQFP |
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29 |
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32 |
|
26 |
O |
Program Store Enable: The read strobe to external program memory. When |
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PSEN |
|
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||||||||||||||||||||
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executing code from the external program memory, |
PSEN |
is activated twice each |
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machine cycle, except that two |
PSEN |
activations are skipped during each access |
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to external data memory. |
PSEN |
is not activated during fetches from internal |
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program memory. |
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31 |
|
35 |
|
29 |
I |
External Access Enable/Programming Supply Voltage: |
|
must be externally |
|||||||||||
|
EA/VPP |
|
|
EA |
|||||||||||||||||||
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held low to enable the device to fetch code from external program memory |
|||||||||||||
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locations. If |
EA |
is held high, the device executes from internal program memory. |
|||||||||||
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The value on the |
EA |
pin is latched when RST is released and any subsequent |
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changes have no effect. This pin also receives the programming supply voltage |
|||||||||||||
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|
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(VPP) during Flash programming. |
|||||||||||||
|
XTAL1 |
19 |
|
21 |
|
15 |
I |
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock |
|||||||||||||||
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generator circuits. |
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|||||||||||||||
|
XTAL2 |
18 |
|
20 |
|
14 |
O |
Crystal 2: Output from the inverting oscillator amplifier. |
NOTE: |
|
|
|
|
|
To avoid ªlatch-upº effect at power-on, the voltage on any pin (other than V |
) must not be higher than V |
CC |
+ 0.5 V or less than V |
SS |
± 0.5 V. |
PP |
|
|
|
1999 Nov 22 |
7 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
|
|
Table 1. Special Function Registers
SYMBOL |
DESCRIPTION |
DIRECT |
|
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION |
RESET |
||||||||||||||
ADDRESS |
MSB |
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LSB |
VALUE |
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ACC* |
Accumulator |
E0H |
|
E7 |
|
E6 |
E5 |
E4 |
|
E3 |
|
E2 |
E1 |
E0 |
00H |
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AUXR# |
Auxiliary |
8EH |
± |
|
± |
|
± |
± |
± |
|
± |
|
EXTRAM |
AO |
xxxxxx10B |
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AUXR1# |
Auxiliary 1 |
A2H |
± |
|
± |
|
ENBOOT |
± |
|
GF2 |
0 |
|
± |
DPS |
xxxxxxx0B |
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B* |
B register |
F0H |
|
F7 |
|
F6 |
F5 |
F4 |
|
F3 |
|
F2 |
F1 |
F0 |
00H |
||||
CCAP0H# |
Module 0 Capture High |
FAH |
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xxxxxxxxB |
CCAP1H# |
Module 1 Capture High |
FBH |
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xxxxxxxxB |
CCAP2H# |
Module 2 Capture High |
FCH |
|
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xxxxxxxxB |
CCAP3H# |
Module 3 Capture High |
FDH |
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xxxxxxxxB |
CCAP4H# |
Module 4 Capture High |
FEH |
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xxxxxxxxB |
CCAP0L# |
Module 0 Capture Low |
EAH |
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xxxxxxxxB |
CCAP1L# |
Module 1 Capture Low |
EBH |
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|
xxxxxxxxB |
CCAP2L# |
Module 2 Capture Low |
ECH |
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|
xxxxxxxxB |
CCAP3L# |
Module 3 Capture Low |
EDH |
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xxxxxxxxB |
CCAP4L# |
Module 4 Capture Low |
EEH |
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xxxxxxxxB |
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CCAPM0# |
Module 0 Mode |
DAH |
± |
|
ECOM |
CAPP |
CAPN |
|
MAT |
|
TOG |
PWM |
ECCF |
x0000000B |
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CCAPM1# |
Module 1 Mode |
DBH |
± |
|
ECOM |
CAPP |
CAPN |
|
MAT |
|
TOG |
PWM |
ECCF |
x0000000B |
|||||
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CCAPM2# |
Module 2 Mode |
DCH |
± |
|
ECOM |
CAPP |
CAPN |
|
MAT |
|
TOG |
PWM |
ECCF |
x0000000B |
|||||
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CCAPM3# |
Module 3 Mode |
DDH |
± |
|
ECOM |
CAPP |
CAPN |
|
MAT |
|
TOG |
PWM |
ECCF |
x0000000B |
|||||
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CCAPM4# |
Module 4 Mode |
DEH |
± |
|
ECOM |
CAPP |
CAPN |
|
MAT |
|
TOG |
PWM |
ECCF |
x0000000B |
|||||
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DF |
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DE |
DD |
DC |
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DB |
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DA |
D9 |
D8 |
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CCON*# |
PCA Counter Control |
D8H |
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CF |
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CR |
± |
CCF4 |
CCF3 |
CCF2 |
CCF1 |
CCF0 |
00x00000B |
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CH# |
PCA Counter High |
F9H |
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00H |
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CL# |
PCA Counter Low |
E9H |
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00H |
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CMOD# |
PCA Counter Mode |
D9H |
CIDL |
WDTE |
± |
± |
± |
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CPS1 |
CPS0 |
ECF |
00xxx000B |
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DPTR: |
Data Pointer (2 bytes) |
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DPH |
Data Pointer High |
83H |
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00H |
DPL |
Data Pointer Low |
82H |
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00H |
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AF |
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AE |
AD |
AC |
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AB |
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AA |
A9 |
A8 |
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IE* |
Interrupt Enable 0 |
A8H |
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EA |
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EC |
ET2 |
ES |
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ET1 |
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EX1 |
ET0 |
EX0 |
00H |
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BF |
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BE |
BD |
BC |
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BB |
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BA |
B9 |
B8 |
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IP* |
Interrupt Priority |
B8H |
± |
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PPC |
PT2 |
PS |
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PT1 |
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PX1 |
PT0 |
PX0 |
x0000000B |
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B7 |
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B6 |
B5 |
B4 |
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B3 |
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B2 |
B1 |
B0 |
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IPH# |
Interrupt Priority High |
B7H |
± |
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PPCH |
PT2H |
PSH |
PT1H |
PX1H |
PT0H |
PX0H |
x0000000B |
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87 |
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86 |
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85 |
84 |
83 |
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82 |
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81 |
80 |
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P0* |
Port 0 |
80H |
AD7 |
AD6 |
AD5 |
AD4 |
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AD3 |
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AD2 |
AD1 |
AD0 |
FFH |
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97 |
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96 |
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95 |
94 |
93 |
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92 |
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91 |
90 |
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P1* |
Port 1 |
90H |
CEX4 |
CEX3 |
CEX2 |
CEX1 |
CEX0 |
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ECI |
T2EX |
T2 |
FFH |
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A7 |
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A6 |
A5 |
A4 |
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A3 |
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A2 |
A1 |
A0 |
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P2* |
Port 2 |
A0H |
AD15 |
AD14 |
AD13 |
AD12 |
AD11 |
AD10 |
AD9 |
AD8 |
FFH |
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B7 |
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B6 |
B5 |
B4 |
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B3 |
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B2 |
B1 |
B0 |
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P3* |
Port 3 |
B0H |
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RD |
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WR |
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T1 |
T0 |
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INT1 |
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INT0 |
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TxD |
RxD |
FFH |
PCON#1 |
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Power Control |
87H |
SMOD1 |
SMOD0 |
± |
± |
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GF1 |
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GF0 |
PD |
IDL |
00xxx000B |
*SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
± Reserved bits.
1. Reset value depends on reset source.
1999 Nov 22 |
8 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
|
|
Table 1. Special Function Registers (Continued)
SYMBOL |
DESCRIPTION |
DIRECT |
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION |
RESET |
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ADDRESS |
MSB |
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LSB |
VALUE |
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D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
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PSW* |
Program Status Word |
D0H |
CY |
AC |
F0 |
RS1 |
RS0 |
OV |
F1 |
P |
00000000B |
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RCAP2H# |
Timer 2 Capture High |
CBH |
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00H |
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RCAP2L# |
Timer 2 Capture Low |
CAH |
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00H |
SADDR# |
Slave Address |
A9H |
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00H |
SADEN# |
Slave Address Mask |
B9H |
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00H |
SBUF |
Serial Data Buffer |
99H |
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xxxxxxxxB |
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9F |
9E |
9D |
9C |
9B |
9A |
99 |
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98 |
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SCON* |
Serial Control |
98H |
SM0/FE |
SM1 |
SM2 |
REN |
TB8 |
RB8 |
TI |
RI |
00H |
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SP |
Stack Pointer |
81H |
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07H |
8F |
8E |
8D |
8C |
8B |
8A |
89 |
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88 |
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TCON* |
Timer Control |
88H |
TF1 |
TR1 |
TF0 |
TR0 |
IE1 |
IT1 |
IE0 |
IT0 |
00H |
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CF |
CE |
CD |
CC |
CB |
CA |
C9 |
C8 |
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T2CON* |
Timer 2 Control |
C8H |
TF2 |
EXF2 |
RCLK |
TCLK |
EXEN2 |
TR2 |
C/T2 |
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CP/RL2 |
00H |
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T2MOD# |
Timer 2 Mode Control |
C9H |
± |
± |
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± |
± |
± |
± |
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T2OE |
DCEN |
xxxxxx00B |
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TH0 |
Timer High 0 |
8CH |
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00H |
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TH1 |
Timer High 1 |
8DH |
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00H |
TH2# |
Timer High 2 |
CDH |
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00H |
TL0 |
Timer Low 0 |
8AH |
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00H |
TL1 |
Timer Low 1 |
8BH |
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00H |
TL2# |
Timer Low 2 |
CCH |
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00H |
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TMOD |
Timer Mode |
89H |
GATE |
C/T |
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M1 |
M0 |
GATE |
C/T |
M1 |
M0 |
00H |
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WDTRST |
Watchdog Timer Reset |
A6H |
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*SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
± Reserved bits.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. Minimum and maximum high and low times specified in the data sheet must be observed.
This device is configured at the factory to operate using 6 clock periods per machine cycle, referred to in this datasheet as ª6 clock modeº. (This yields performance equivalent to twice that of standard
80C51 family devices). It may be optionally configured on commercially-available EPROM programming equipment to operate at 12 clocks per machine cycle, referred to in this datasheet as ª12 clock modeº. Once 12 clock mode has been configured, it cannot be changed back to 6 clock mode.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (12 oscillator periods in 6 clock mode, or 24 oscillator periods in 12 clock mode), while the oscillator is running. To ensure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 (min.) is applied to RESET.
The value on the EA pin is latched when RST is deasserted and has no further effect.
1999 Nov 22 |
9 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
|
|
LOW POWER MODES Stop Clock Mode
The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested.
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated.
Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values.
To properly terminate Power Down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms).
With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
POWER OFF FLAG
The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the P89C51RB2/RC2/RD2 rises from 0 to 5 V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown.
The VCC level must remain above 3 V for the POF to remain unaffected by the VCC level.
Design Consideration
•When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
ONCE Mode
The ONCE (ªOn-Circuit Emulationº) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by:
1.Pull ALE low while the device is in reset and PSEN is high;
2.Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed:
1.to input the external clock for Timer/Counter 2, or
2.to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating frequency (61 Hz to 4 MHz in 12 clock mode).
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation:
Oscillator Frequency
n (65536 RCAP2H, RCAP2L)
n = 2 in 6 clock mode
4 in 12 clock mode
Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.
Table 2. External Pin Status During Idle and Power-Down Mode
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MODE |
PROGRAM MEMORY |
ALE |
|
PSEN |
PORT 0 |
PORT 1 |
PORT 2 |
PORT 3 |
|
Idle |
Internal |
1 |
|
1 |
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Data |
Data |
Data |
Data |
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Idle |
External |
1 |
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1 |
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Float |
Data |
Address |
Data |
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Power-down |
Internal |
0 |
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0 |
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Data |
Data |
Data |
Data |
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Power-down |
External |
0 |
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0 |
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Float |
Data |
Data |
Data |
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|
1999 Nov 22 |
10 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
|
|
TIMER 2 OPERATION
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2* in the special function register T2CON (see Figure 1). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 3.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/6 pulses (osc/12 in 12 clock mode).).
Counter Enable) which is located in the T2MOD register (see Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin.
Figure 4 shows Timer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means.
If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1.
In Figure 5 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.
When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2.
Auto-Reload Mode (Up or Down Counter)
In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2* in T2CON]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down
The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.
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(MSB) |
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(LSB) |
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TF2 |
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EXF2 |
RCLK |
TCLK |
EXEN2 |
TR2 |
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C/T2 |
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CP/RL2 |
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Symbol |
Position |
Name and Significance |
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TF2 |
T2CON.7 |
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set |
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when either RCLK or TCLK = 1. |
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EXF2 |
T2CON.6 |
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and |
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EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 |
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interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down |
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counter mode (DCEN = 1). |
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RCLK |
T2CON.5 |
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock |
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in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. |
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TCLK |
T2CON.4 |
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock |
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in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. |
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EXEN2 |
T2CON.3 |
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative |
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transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to |
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ignore events at T2EX. |
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TR2 |
T2CON.2 |
Start/stop control for Timer 2. A logic 1 starts the timer. |
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T2CON.1 |
Timer or counter select. (Timer 2) |
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C/T2 |
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0 = Internal timer (OSC/6 in 6 clock mode or OSC/12 in 12 clock mode) |
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1 = External event counter (falling edge triggered). |
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T2CON.0 |
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When |
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CP/RL2 |
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cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when |
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EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload |
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on Timer 2 overflow. |
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SU01251 |
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Figure 1. Timer/Counter 2 (T2CON) Control Register
1999 Nov 22 |
11 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
||||
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
||||
Table 3. Timer 2 Operating Modes |
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RCLK + TCLK |
CP/RL2 |
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TR2 |
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MODE |
0 |
0 |
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1 |
16-bit Auto-reload |
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0 |
1 |
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1 |
16-bit Capture |
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1 |
X |
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1 |
Baud rate generator |
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X |
X |
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0 |
(off) |
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OSC |
n* |
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C/T2 = 0 |
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TL2 |
TH2 |
TF2 |
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(8-bits) |
(8-bits) |
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C/T2 = 1 |
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T2 Pin |
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Control |
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TR2 |
Capture |
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Transition |
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Timer 2 |
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Detector |
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Interrupt |
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RCAP2L |
RCAP2H |
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T2EX Pin |
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EXF2 |
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Control |
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EXEN2 |
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SU01252 |
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* n = 6 in 6 clock mode, or 12 in 12 clock mode.
Figure 2. Timer 2 in Capture Mode
T2MOD |
Address = 0C9H |
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Reset Value = XXXX XX00B |
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Not Bit Addressable |
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Ð |
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Ð |
Ð |
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Ð |
Ð |
Ð |
T2OE |
DCEN |
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Bit |
7 |
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6 |
5 |
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4 |
3 |
2 |
1 |
0 |
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Symbol |
Function |
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Ð |
Not implemented, reserved for future use.* |
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T2OE |
Timer 2 Output Enable bit. |
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DCEN |
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. |
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
SU00729
Figure 3. Timer 2 Mode (T2MOD) Control Register
1999 Nov 22 |
12 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
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OSC |
n* |
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C/T2 = 0 |
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TL2 |
TH2 |
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(8-BITS) |
(8-BITS) |
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C/T2 = 1 |
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T2 PIN |
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CONTROL |
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TR2 |
RELOAD |
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TRANSITION |
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DETECTOR |
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RCAP2L |
RCAP2H |
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TF2 |
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TIMER 2 |
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INTERRUPT |
T2EX PIN |
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EXF2 |
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CONTROL |
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EXEN2 |
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SU01253 |
* n = 6 in 6 clock mode, or 12 in 12 clock mode.
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
(DOWN COUNTING RELOAD VALUE)
FFH |
FFH |
TOGGLE |
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EXF2 |
OSC |
n* |
C/T2 = 0 |
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OVERFLOW |
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TL2 |
TH2 |
TF2 |
INTERRUPT |
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T2 PIN |
C/T2 = 1 |
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CONTROL |
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TR2 |
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COUNT |
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DIRECTION |
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1 = UP |
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0 = DOWN |
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RCAP2L |
RCAP2H |
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(UP COUNTING RELOAD VALUE) |
T2EX PIN |
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* n = 6 in 6 clock mode, or 12 in 12 clock mode. |
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SU01254 |
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
1999 Nov 22 |
13 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
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Timer 1
Overflow
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2 |
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OSC |
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ª0º |
ª1º |
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C/T2 = 0 |
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SMOD |
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ª1º |
ª0º |
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TL2 |
TH2 |
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(8-bits) |
(8-bits) |
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RCLK |
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C/T2 = 1 |
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T2 Pin |
Control |
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16 |
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RX Clock |
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TR2 |
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Reload |
ª1º |
ª0º |
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TCLK |
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Transition |
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Detector |
RCAP2L |
RCAP2H |
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16 |
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TX Clock |
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T2EX Pin |
EXF2 |
Timer 2 |
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Interrupt |
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Control
EXEN2
Note availability of additional external interrupt.
SU01213
Figure 6. Timer 2 in Baud Rate Generator Mode
Table 4. Timer 2 Generated Commonly Used
Baud Rates
Baud Rate |
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Timer 2 |
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Osc Freq |
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12 clock |
6 clock |
RCAP2H |
RCAP2L |
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mode |
mode |
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375 k |
750 k |
12 MHz |
FF |
FF |
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9.6 k |
19.2 k |
12 MHz |
FF |
D9 |
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2.8 k |
5.6 k |
12 MHz |
FF |
B2 |
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2.4 k |
4.8 k |
12 MHz |
FF |
64 |
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1.2 k |
2.4 k |
12 MHz |
FE |
C8 |
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300 |
600 |
12 MHz |
FB |
1E |
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110 |
220 |
12 MHz |
F2 |
AF |
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300 |
600 |
6 MHz |
FD |
8F |
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110 |
220 |
6 MHz |
F9 |
57 |
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The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate given below:
Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate 16
The timer can be configured for either ªtimerº or ªcounterº operation. In many applications, it is configured for ªtimerº operation (C/T2*=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator.
Usually, as a timer it would increment every machine cycle (i.e.,
1/6 the oscillator frequency in 6 clock mode, 1/12 the oscillator frequency in 12 clock mode). As a baud rate generator, it increments at the oscillator frequency in 6 clock mode (OSC/2 in 12 clock mode). Thus the baud rate formula is as follows:
Modes 1 and 3 Baud Rates =
Oscillator Frequency
[ n * [65536 (RCAP2H, RCAP2L)]]
Baud Rate Generator Mode
Bits TCLK and/or RCLK in T2CON (Table 4) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates ± one generated by Timer 1, the other by Timer 2.
Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode,in that a rollover in
TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.
* n = 16 in 6 clock mode 32 in 12 clock mode
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
The Timer 2 as a baud rate generator mode shown in Figure 6, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.
1999 Nov 22 |
14 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
|
|
When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
Table 4 shows commonly used baud rates and how they can be obtained from Timer 2.
Summary of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is:
Baud Rate + Timer 2 Overflow Rate
16
If Timer 2 is being clocked internally, the baud rate is:
Baud Rate + fOSC
[ n * [65536 (RCAP2H, RCAP2L)]]
* n = 16 in 6 clock mode 32 in 12 clock mode
Where fOSC= Oscillator Frequency
To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as:
RCAP2H, RCAP2L + 65536 |
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fOSC |
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n * |
Baud Rate |
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Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 5 for set-up of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a counter.
Table 5. Timer 2 as a Timer
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T2CON |
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MODE |
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INTERNAL CONTROL |
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EXTERNAL CONTROL |
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(Note 1) |
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(Note 2) |
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16-bit Auto-Reload |
00H |
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08H |
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16-bit Capture |
01H |
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09H |
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Baud rate generator receive and transmit same baud rate |
34H |
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36H |
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Receive only |
24H |
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26H |
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Transmit only |
14H |
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16H |
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Table 6. Timer 2 as a Counter
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TMOD |
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MODE |
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INTERNAL CONTROL |
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EXTERNAL CONTROL |
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(Note 1) |
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(Note 2) |
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16-bit |
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02H |
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0AH |
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Auto-Reload |
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03H |
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0BH |
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NOTES:
1.Capture/reload occurs only on timer/counter overflow.
2.Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode.
1999 Nov 22 |
15 |
Philips Semiconductors Preliminary specification
80C51 8-bit Flash microcontroller family |
P89C51RB2/P89C51RC2/ |
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM |
P89C51RD2 |
|
|
Enhanced UART
The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART.
When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the ªGivenº address or the ªBroadcastº address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are ªdon't careº. The SADEN mask can be logically ANDed with the SADDR to create the ªGivenº address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme:
Slave 0 |
SADDR |
= |
1100 |
0000 |
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SADEN |
= |
1111 |
1101 |
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Given |
= |
1100 |
00X0 |
Slave 1 |
SADDR |
= |
1100 |
0000 |
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SADEN |
= |
1111 |
1110 |
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Given |
= |
1100 |
000X |
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.
In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:
Slave 0 |
SADDR |
= |
1100 |
0000 |
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SADEN |
= |
1111 |
1001 |
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Given |
= |
1100 |
0XX0 |
Slave 1 |
SADDR |
= |
1110 |
0000 |
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SADEN |
= |
1111 |
1010 |
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Given |
= |
1110 |
0X0X |
Slave 2 |
SADDR |
= |
1110 |
0000 |
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SADEN |
= |
1111 |
1100 |
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Given |
= |
1110 |
00XX |
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all ªdon't caresº as well as a Broadcast address of all ªdon't caresº. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.
1999 Nov 22 |
16 |