Philips N74ALS273DB, N74ALS273D, N74ALS273N Datasheet
74ALS273
Octal D–type flip–flop
Product specification
IC05 Data Handbook
1991 Feb 08
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74ALS273Octal D-type flip-flop
2
1991 Feb 08 853–1398 01670
FEA TURES
•Eight edge-triggered D-type flip-flops
•Buffered common clock
•Buffered asynchronous master reset
•See 74ALS377 for clock enable version
•See 74ALS373 for transparent latch version
•See 74ALS374 for 3-State version
DESCRIPTION
The 74ALS273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered clock (CP)
and master reset (MR
) inputs load and reset all flip-flops
simultaneously .
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
All outputs will be forced Low independently of clock or data inputs
by a Low voltage level on the MR
input.
The device is useful for applications where the true output only is
required and the CP and MR
are common to all flip-flops.
TYPE
TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS273 95MHz 16mA
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3 Q4
GND
D4
D5
Q5
Q6
D6
D7
Q7
V
CC
CP
SF00346
ORDERING INFORMA TION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
DRAWING
NUMBER
20-pin plastic DIP 74ALS273N SOT146-1
20-pin plastic SO 74ALS273D SOT163-1
20-pin plastic SSOP
Type II
74ALS273DB SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 – D7 Data inputs 1.0/2.0 20µA/0.2mA
CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.1mA
MR Master Reset input (active-Low) 1.0/1.0 20µA/0.1mA
Q0 – Q7 3-State outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
3 4 7 8 13 14 1817
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
1
11
MR
CP
V
CC
= Pin 20
GND = Pin 10
SF00347
IEC/IEEE SYMBOL
SF00348
1
32
4
5
7
6
8
9
R
11
C1
13
12
14
15
17
16
18
19
1D
Philips Semiconductors Product specification
74ALS273Octal D-type flip-flop
1991 Feb 08
3
LOGIC DIAGRAM
DQ
RD
Q0
2
V
CC
= Pin 20
GND = Pin 10
CP
D0
3
DQ
RD
Q1
5
CP
D1
4
DQ
RD
Q2
6
CP
D2
7
DQ
RD
Q3
9
CP
D3
8
DQ
RD
Q4
12
CP
D4
13
DQ
RD
Q5
15
CP
D5
14
DQ
RD
Q6
16
CP
D6
17
DQ
RD
Q7
19
CP
D7
18
11
1
CP
MR
SF00349
FUNCTION TABLE
INPUTS OUTPUTS
MR CP Dn Qn
OPERATING MODE
L X X L Reset (clear)
H ↑ h H Load “1”
H ↑ l L Load “0”
H = High-voltage level
h = High state must be present one setup time before the Low-to-High clock transition
L = Low-voltage level
l = Low state must be present one setup time before the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER RATING UNIT
V
CC
Supply voltage –0.5 to +7.0 V
V
IN
Input voltage –0.5 to +7.0 V
I
IN
Input current –30 to +5 mA
V
OUT
Voltage applied to output in High output state –0.5 to V
CC
V
I
OUT
Current applied to output in Low output state 48 mA
T
amb
Operating free-air temperature range 0 to +70 °C
T
stg
Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5.0 5.5 V
V
IH
High-level input voltage 2.0 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –2.6 mA
I
OL
Low-level output current 24 mA
T
amb
Operating free-air temperature range 0 +70 °C
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