Philips FBL22041BB Datasheet

INTEGRATED CIRCUITS

FBL22041

3.3V BTL 7-bit Futurebus + transceiver
(standard A-port)

Product specification
Supersedes data of 1998 Feb 02
IC23 Data Handbook

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1998 Aug 12

Philips Semiconductors Product specification

ns

ns

ICCSupply Current

mA

FBL220413.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

FEA TURES

•7-bit BTL transceiver

•Separate I/O on TTL A-port

•Inverting

•Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit

arrangement

•Drives heavily loaded backplanes with equivalent load

impedances down to 10Ω.

•High drive 100mA BTL open collector drivers on B-port

•Allows incident wave switching in heavily loaded backplane buses

•Reduced BTL voltage swing produces less noise and reduces

power consumption

•Built-in precision band-gap reference provides accurate receiver

thresholds and improved noise immunity

•Compatible with IEEE Futurebus+ or proprietary BTL backplanes

•Controlled output ramp and multiple GND pins minimize ground

bounce

•Each BTL driver has a dedicated Bus GND for a signal return

•Glitch-free power up/power down operation

•Low I

current

CC

•Tight output skew

•Supports live insertion

•Pins for the optional JTAG boundary scan function are provided

•High density packaging in plastic Quad Flatpack

•5V compatible I/O on A-port

•The A port includes a series resistor of 30Ω making external

terminating resistors unnecessary

DESCRIPTION

The FBL22041 is a 7-bit bidirectional BTL transceiver and is
intended to provide the electrical interface to a high performance
wired-OR bus. The FBL22041 is an inverting transceiver.

The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V .

The FBL22041 is designed with a 30Ω series resistance in both the
HIGH and LOW states of the output.

The FBL22041 is pin and function compatible with FB2041 but
operates at a 3.3V supply voltage, greatly reducing power
consumption.

QUICK REFERENCE DATA

SYMBOL PARAMETER TYPICAL UNIT

t

PLH

t

PHL

t

PLH

t

PHL

C

I

OB

OL

pp

Propagation delay 4.1

AIn to Bn 3.6

Propagation delay 5.2

Bn to AOn 5.1

Output capacitance (B0 - B6 only) 6 pF

Output current (B0 - B6 only) 100 mA

Standby 6.0

AIn to Bn (outputs Low or High) 5.1

Bn to AOn (outputs Low) 13.4

Bn to AOn (outputs High) 10.6

ORDERING INFORMATION

PACKAGE

52-pin Plastic Quad Flatpack FBL22041BB SOT379-1

COMMERCIAL RANGE

VCC = 3.3V±10%; T

= 0 to +70°C

amb

DWG

No.

1998 Aug 12 853-2039 19863

2

Philips Semiconductors Product specification

FBL220413.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

CC

V

AI0

AO1

AO0

52 51 50 49 48 47 46 45 44 43 42 41 40

LOGIC GND

LOGIC GND

LOGIC GND

LOGIC GND

LOGIC GND

AI1

AI2

AO2

AO3

AI3

AI4

AO4

AO5

1
2
3
4
5
6
7

8

9
10
11
12
13

14 15 16 17 18 19 20 21 22 23 24 25 26

AI5

7-Bit Transceiver

52-lead PQFP

CC

AO6

BG V

LOGIC GND

The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.

There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1
OEA2/OEB2
OEA3/OEB3

, output drivers for bits 1–2–3 are enabled with
and output drivers for bits 4–5–6 are enabled with
.

CC

BIAS V

OEA1

AI6

BG GND

OEB0

OEA2

V

OEB1

TCK (option)

CC

V

TDI (option)

TDO (option)

TMS (option)

BUS GND

B0

OEB2

OEA3

OEB3

39
38
37
36
35
34
33

32
31
30
29
28
27

BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND

B5
BUS GND
B6
N/C

SG00084

The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/of f cycles, the A-port
drivers are held in a High impedance state when V

CC

The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn
be enabled. When OEB0 is Low or if OEBn

is Low the output driver will

is High, the B-port

drivers will be inactive and at the level of the backplane signal.

is below 1.3V.

1998 Aug 12

3

Philips Semiconductors Product specification

FBL220413.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

PIN DESCRIPTION

SYMBOL PIN NUMBER TYPE NAME AND FUNCTION

ai0 – ai6 51, 2, 3, 8, 9, 14, 18 Input Data inputs (TTL)

aO0 – aO6 50, 52, 4, 6, 10, 12, 16 Output 3-state outputs (TTL)

b0 – b6 40, 38, 36, 34, 32, 30, 28 i/o Data inputs/Open Collector outputs, High current drive (BTL)

OEB0 46 Input Enables the Bn outputs when High
OEB1 45 Input Enables the B0 output when Low
OEB2 25 Input Enables the B1 – B3 outputs when Low
OEB3 26 Input Enables the B4 – B6 outputs when Low
OEA1 47 Input Enables the A0 outputs when High
OEA2 20 Input Enables the A1 – A3 outputs when High
OEA3 24 Input Enables the A4 – A6 outputs when High

bus gnd 41, 39, 37, 35, 33, 31, 29 GND Bus ground (0V)

LOGIC gnd 1, 5, 7, 11, 13, 15 GND Logic ground (0V)

LOGIC/bus V

BG V

BIAS V 48 Power Positive supply voltage

BG GND 19 GND BAND GAP GROUND (0V)

CC

CC

TMS 42 Input Test Mode Select (no-connect)

Tck 44 Input Test Clock (no-connect)
Tdi 22 Input T est Data In (shorted to TDO)

Tdo 21 Output Test Data Out (TDI)

23, 43, 49 Power Positive supply voltage

17 Power Positive supply voltage BAND GAP

1998 Aug 12

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Philips Semiconductors Product specification

MODE

FBL220413.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

FUNCTION TABLE

INPUTS OUTPUTS

AIn Bn* OEB0 OEB1 OEB2 OEB3 OEA1 OEA2 OEA3 AOn Bn*

L — H L L L L L L Z H**

AIn to Bn H — H L L L L L L Z L

L — H L L L H H H L H**

H — H L L L H H H H L

L — H L X X L L L Z H**

AI0 to B0 H — H L X X L L L Z L

L — H L X X H H H L H**

H — H L X X H H H H L

L — H X L X L L L Z H**

AI1 – AI3 to B1 – B3 H — H X L X L L L Z L

L — H X L X H H H L H**

H — H X L X H H H H L

L — H X X L L L L Z H**

AI4 – AI6 to B4 – B6 H — H X X L L L L Z L

L — H X X L H H H L H**

H — H X X L H H H H L

Disable Bn outputs X X L X X X X X X X H**

X X X H H H X X X X H**
Disable B0 outputs X X H H X X X X X X H**
Disable B1 – B3 outputs X X H X H X X X X X H**
Disable B4 – B6 outputs X X H X X H X X X X H**

X L L X X X H H H H Input
Bn to AOn X H L X X X H H H L Input

X L X H H H H H H H Input

X H X H H H H H H L Input

X L L X X X H X X H Input
B0 to AO0 X H L X X X H X X L Input

X L X H H H H X X H Input

X H X H H H H X X L Input

X L L X X X X H X H Input
B1 – B3 to AO1 – AO3 X H L X X X X H X L Input

X L X H H H X H X H Input

X H X H H H X H X L Input

X L L X X X X X H H Input
B4 – B6 to AO4 – AO6 X H L X X X X X H L Input

X L X H H H X X H H Input

X H X H H H X X H L Input
Disable AOn outputs X X X X X X L L L Z X
Disable AO0 outputs X X X X X X L X X Z X
Disable AO1 – AO3 outputs X X X X X X X L X Z X
Disable AO4 – AO6 outputs X X X X X X X X L Z X

NOTES:

H = High voltage level
L = Low voltage level
X = Don’t care
Z = High-impedance (OFF) state
— = Input not externally driven
H** = Goes to level of pull-up voltage
B* = Precaution should be taken to ensure B inputs do not float.

If they do, they are equal to Low state.

Z = High-impedance (OFF) state
— = Input not externally driven
H** = Goes to level of pull-up voltage
B* = Precaution should be taken to ensure B inputs do not float.

If they do, they are equal to Low state.

1998 Aug 12

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