Philips FBL22040BB Datasheet

INTEGRATED CIRCUITS
FBL22040
3.3V BTL8-bit TTL to BTL transceiver
Product specification IC23 Data Handbook
 
1998 Dec 07
V
In ut voltage
V
I
mA

FBL220403.3V BTL 8-bit TTL to BTL transceiver

FEA TURES

Resistor version of FB2040
8-bit BTL transceivers
Separate I/O on TTL A-port
Inverting
Drives heavily loaded backplanes with equivalent load
impedances down to 10Ω.
High drive 100mA BTL open collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes

QUICK REFERENCE DATA

SYMBOL PARAMETER TYPICAL UNIT
t
PLH
t
PHL
t
PLH
t
PHL
C
I
I
OB
OL
CC
Propagation delay AIn to Bn
Propagation delay Bn to AOn
Output capacitance (B0 – B7 only) 4 pF Output current (B0 – B7 only) 100 mA
Supply current
Controlled output ramp and multiple GND pins minimize ground
bounce
Each BTL driver has a dedicated Bus GND for a signal return
Glitch-free power up/power down operation
Low I
current
CC
Tight output skew
Supports live insertion
Pins for the optional JTAG boundary scan function are provided
High density packaging in plastic Quad Flat Pack
Same pin and function as FBL2040 except for a 30 series
termination resistor
The A outputs include a series resistor of 30 making external
terminating resistors unnecessary
4.4
3.1
3.4
3.2
Standby 4
AIn to Bn
(outputs Low )
Bn to AOn
(outputs Low)
AIn to Bn
(outputs High)
Bn to AOn
(outputs High)
8
18
13
16
ns
ns
mA

ORDERING INFORMATION

PACKAGES
52-pin Plastic Quad Flat Pack (QFP) FBL22040BB SOT379-1
COMMERCIAL RANGE
VCC = 3V±10%; T
= –40°C to +85°C
amb
DRAWING
NUMBER

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
V
CC
IN
I
IN
V
OUT
OUT
T
amb
T
STG
1998 Dec 07 853-2137 20493
Supply voltage -0.5 to +4.6 V
p
Input current -18 to +5.0 mA Voltage applied to output in High output state -0.5 to +7.0 V Current applied to output in Low
output state Operating free-air temperature range -40 to +85 °C
Storage temperature -65 to +150 °C
PARAMETER RATING UNIT
AI0 – AI7, OEB0, OEB1, OEA -0.5 to +7.0
B0 – B7 -0.5 to +3.5
A0 – A7 24, –24 B0 – B7 200
2
Philips Semiconductors Product specification
FBL220403.3V BTL 8-bit TTL to BTL transceiver

PIN CONFIGURATION

CC
LOGIC V
AI0
AO1
AO0
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
AI1
AI2
AO2
AO3
AI3
AI4
AO4
AO5
1 2 3 4 5 6 7
8
9 10 11 12 13
14 15 16 17 18 19 20 21 22 23 24 25 26
AI5
8-Bit Transceiver
52-lead PQFP
CC
AO6
BG V
LOGIC GND

DESCRIPTION

The FBL22040 is an 8-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FBL22040 is an inverting transceiver.
The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V .
The B-port interfaces to “Backplane Transceiver Logic” (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes.
The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEA goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEA goes Low, A-port drivers become High impedance without any extra delay. During power on/of f cycles, the A-port drivers are held in a High impedance state when V
The B-port has two output enables, OEB0 and OEB1. When OEB0 is High and OEB1
is Low the output is enabled. When OEB0 is Low
is below 1.3V.
CC
OEA
BIAS V
OEB0
FBL22040
AI6
AO7
BG GND
CC
TMS (option)
TCK (option)
OEB1
TDI (option)
TDO (option)
or if OEB1
BUS V
CC
BUS V
is High, the B-port is inactive and is at the level of the
AI7
B0/B0
BUS GND
39 38 37 36 35 34 33
32 31 30 29 28 27
B7
NC
BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND
SG00114
backplane signal. To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while V BIAS V pin should be tied to a V
is Low. If live insertion is not a requirement, the
CC
CC
pin.
The LOGIC GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package.
Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot.
The LOGIC V
and BUS VCC pins are also isolated internally to
CC
minimize noise and may be externally decoupled separately or simply tied together.
JTAG boundary scan pins are provided with signals TMS, TCK, TDI and TDO. TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally. Boundary scan functionality is not implemented at this time.
1998 Dec 07
3
Philips Semiconductors Product specification
MODE
AIn to Bn
Disable Bn out uts
Bn to AOn
FBL220403.3V BTL 8-bit TTL to BTL transceiver

PIN DESCRIPTION

SYMBOL PIN NUMBER TYPE NAME AND FUNCTION
AI0 – AI7 51, 2, 3, 8, 9, 14, 18, 24 Input Data inputs (TTL)
AO0 – AO7 50, 52, 4, 6, 10, 12, 16, 20 Output 3-state outputs (TTL)
B0 – B7
OEB0 46 Input Enables the B outputs when High OEB1 45 Input Enables the B outputs when Low
OEA 47 Input Enables the A outputs when High
BUS GND 41, 39, 37, 35, 33, 31, 29, 27 GND Bus ground (0V)
LOGIC GND 1, 5, 7, 11, 13, 15 GND Logic ground (0V)
BUS V
CC
LOGIC V
CC
BG V
CC
BG GND 19 GND Band Gap threshold voltage reference ground
BIAS V 48 Power Live insertion pre-bias pin
TMS 42 Input Test Mode Select (optional, if not implemented then no-connect) TCK 44 Input Test Clock (optional, if not implemented then no-connect)
TDI 22 Input Test Data In (optional, if not implemented then shorted to TDO)
TDO 21 Output Test Data Out (optional, if not implemented then shorted to TDI)
NC 25 NC No Connect
40, 38, 36, 34,
32, 30, 28, 26
23, 43 Power Positive supply voltage
49 Power Positive supply voltage 17 Power Band Gap threshold voltage reference
I/O Data inputs/Open Collector outputs. High current drive (BTL)

FUNCTION TABLE

INPUTS OUTPUTS
AIn Bn* OEB0 OEB1 OEA AOn Bn*
L H L L Z H**
H H L L Z L
L H L H L H**
H H L H H L
p
Disable AOn outputs X X X L Z X
H** = Goes to level of pull-up voltage B* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
X X L X X X H** X X X H X X H** X L L X H H Input X H X H H L Input X L X H H H Input X H L X H L Input
1998 Dec 07
4
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