Philips 74HCT365U, 74HCT365NB, 74HCT365N, 74HCT365DB, 74HCT365D Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT365

Hex buffer/line driver; 3-state

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Hex buffer/line driver; 3-state 74HC/HCT365

FEATURES

• Non-inverting outputs

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT365 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT365 are hex non-inverting buffer/line
drivers with 3-state outputs. The 3-state outputs (nY) are
controlled by the output enable inputs (

OE1, OE2).

A HIGH on OEn causes the outputs to assume a high
impedance OFF-state.

The “365” is identical to the “366” but has non-inverting
outputs.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi + ∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay

nA to nY

CL= 15 pF; VCC=5 V 9 11 ns

C

I

input capacitance 3,5 3,5 pF

C

PD

power dissipation capacitance per buffer notes 1 and 2 40 40 pF

December 1990 3

Philips Semiconductors Product specification

Hex buffer/line driver; 3-state 74HC/HCT365

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 15

OE1, OE

2

output enable inputs (active LOW)
2, 4, 6, 10, 12, 14 1A to 6A data inputs
3, 5, 7, 9, 11, 13 1Y to 6Y data outputs
8 GND ground (0 V)
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Fig.3 IEC logic symbol.