Philips 74HCT138U, 74HCT138NB, 74HCT138N, 74HCT138DB, 74HCT138D Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT138

3-to-8 line decoder/demultiplexer; inverting

Product specification			September 1993
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
3-to-8 line decoder/demultiplexer; inverting	74HC/HCT138

FEATURES

·Demultiplexing capability

·Multiple input enable for easy expansion

·Ideal for memory chip select decoding

·Active LOW mutually exclusive outputs

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled,

provide 8 mutually exclusive active LOW outputs (Y0 to

Y7).

The “138” features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be

HIGH unless E1 and E2 are LOW and E3 is HIGH.

This multiple enable function allows easy parallel expansion of the “138” to a 1-of-32 (5 lines to 32 lines) decoder with just four “138” ICs and one inverter.

The ”138” can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state.

The ”138” is identical to the “238” but has inverting outputs.

SYMBOL						PARAMETER	CONDITIONS	TYPICAL		UNIT
								HC	HCT
	propagation delay						CL = 15 pF; VCC = 5 V
tPHL/ tPLH
		An to		Y		n		12	17	ns
tPHL/ tPLH		E3 to		Y		n		14	19	ns
		E	n to	Y	n
CI	input capacitance							3.5	3.5	pF
CPD	power dissipation capacitance per package						notes 1 and 2	67	67	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

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Philips Semiconductors									Product specification
3-to-8 line decoder/demultiplexer; inverting									74HC/HCT138
PIN DESCRIPTION
PIN NO.		SYMBOL						NAME AND FUNCTION
1, 2, 3		A0 to A2						address inputs
4, 5					2			enable inputs (active LOW)
		E	1,	E
6		E3						enable input (active HIGH)
8		GND						ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7							7	outputs (active LOW)
		Y	0 to			Y
16		VCC						positive supply voltage

Fig.1 Pin configuration.

handbook, halfpage

1										A 0		Y		0			15
2										A 1		Y	1				14
3										A 2		Y	2				13
												Y	3				12
																	11
												Y	4
							E	1					5				10
4												Y
5							E	2				Y	6				9
6
							E3					Y7					7
											MLB312

Fig.2 Logic symbol.

(a)

(b)

Fig.3 IEC logic symbol.

Fig.4 Functional diagram.

September 1993

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