Philips 74HCT107U, 74HCT107N, 74HCT107D, 74HC107U, 74HC107PW Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT107
Dual JK flip-flop with reset; negative-edge trigger
Product specification |
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December 1990 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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Dual JK flip-flop with reset; negative-edge trigger |
74HC/HCT107 |
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FEATURES
·Output capability: standard
·ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
SYMBOL |
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PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLH |
propagation delay |
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16 |
16 |
ns |
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nCP |
to nQ |
CL = 15 pF; |
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nCP to nQ |
16 |
18 |
ns |
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VCC = 5 V |
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nR to nQ, nQ |
16 |
17 |
ns |
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fmax |
maximum clock frequency |
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78 |
73 |
MHz |
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CI |
input capacitance |
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3.5 |
3.5 |
pF |
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CPD |
power dissipation |
notes 1 and 2 |
30 |
30 |
pF |
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capacitance per flip-flop |
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Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC - 1.5 V.
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 |
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Philips Semiconductors |
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Product specification |
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Dual JK flip-flop with reset; negative-edge trigger |
74HC/HCT107 |
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PIN DESCRIPTION |
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PIN NO. |
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SYMBOL |
NAME AND FUNCTION |
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1, 8, 4, 11 |
1J, 2J, 1K, 2K |
synchronous inputs; flip-flops 1 and 2 |
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2, 6 |
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complement flip-flop outputs |
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1Q, |
2Q |
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3, 5 |
1Q, 2Q |
true flip-flop outputs |
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7 |
GND |
ground (0 V) |
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12, 9 |
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clock input (HIGH-to-LOW, edge-triggered) |
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1CP, |
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2CP |
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13, 10 |
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asynchronous reset inputs (active LOW) |
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1R, |
2R |
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14 |
VCC |
positive supply voltage |
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Fig.1 Pin configuration. |
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Fig.2 Logic symbol. |
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Fig.3 IEC logic symbol. |
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December 1990 |
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