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NTMD6N03R2
Power MOSFET
30 V, 6 A, Dual N−Channel SO−8
Features
• Designed for use in low voltage, high speed switching applications
• Ultra Low On−Resistance Provides
Higher Efficiency and Extends Battery Life
− R
− R
• Miniature SO−8 Surface Mount Package Saves Board Space
• Diode is Characterized for Use in Bridge Circuits
• Diode Exhibits High Speed, with Soft Recovery
Applications
• Dc−Dc Converters
• Computers
• Printers
• Cellular and Cordless Phones
• Disk Drives and Tape Drives
MAXIMUM RATINGS (T
Drain−to−Source Voltage V
Gate−to−Source Voltage − Continuous V
Drain Current
− Continuous @ T
− Single Pulse (tp ≤ 10 s)
Total Power Dissipation
@ T
@ T
Operating and Storage Temperature
Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
(V
DD
V
DS
L = 10 mH, R
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes for 10 seconds
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 1″ pad size, t ≤ 10 s
2. When surface mounted to an FR4 board using 1″ pad size, t = steady state
= 0.024 , VGS = 10 V (Typ)
DS(on)
= 0.030 , VGS = 4.5 V (Typ)
DS(on)
= 25°C unless otherwise noted)
J
Rating
= 25°C
A
= 25°C (Note 1)
A
= 25°C (Note 2)
A
= 25°C
= 25 Ω)
G
J
= 30 Vdc, VGS = 5.0 Vdc,
= 20 Vdc, Peak IL = 9.0 Apk,
Symbol Value Unit
DSS
I
I
DM
P
TJ, T
E
R
T
GS
D
AS
D
stg
JA
L
30 Volts
20 Volts
6.0
30
2.0
1.29
−55 to
+150
325 mJ
62.5
97
260 °C
Adc
Apk
Watts
°C
°C/W
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V
DSS
30 V 24 mΩ @ VGS = 10 V 6.0 A
G
D
R
DS(ON)
N−Channel
S
TYP ID MAX
D
G
S
MARKING
8
1
SO−8, DUAL
CASE 751
STYLE 11
DIAGRAM
8
E6N03
LYWW
1
PIN ASSIGNMENTS
Source−1
Gate−1
Source−2
Gate−2
1
2
3
4
(Top View)
E6N03 = Device Code
L = Assembly Location
Y = Year
WW = Work Week
8
7
6
5
Drain−1
Drain−1
Drain−2
Drain−2
ORDERING INFORMATION
Device Package Shipping
NTMD6N03R2 SO−8 2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
†
Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 1
1 Publication Order Number:
NTMD6N03R2/D
NTMD6N03R2
)
f
MHz)
R
G
Ω)
R
G
Ω)
I
D
A)
)
dIS/dt
100 A/µs)
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
C
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
= 0 Vdc, ID = 250 µA)
(V
GS
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
= 24 Vdc, VGS = 0 Vdc, TJ = 25°C)
DS
= 24 Vdc, VGS = 0 Vdc, TJ = 125°C)
(V
DS
Gate−Body Leakage Current
= ±20 Vdc, VDS = 0 Vdc)
(V
GS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
= VGS, ID = 250 µAdc)
(V
DS
Temperature Coefficient (Negative)
Static Drain−to−Source On−State Resistance
(V
= 10 Vdc, ID = 6 Adc)
GS
= 4.5 Vdc, ID = 3.9 Adc)
(V
GS
Forward Transconductance
(V
= 15 Vdc, ID = 5.0 Adc)
DS
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 24 Vdc, VGS = 0 Vdc,
f = 1.0 MHz
= 1.0
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 15 Vdc, ID = 1 A,
VGS = 10 V,
= 6 Ω)
R
6
G
Fall Time
Turn−On Delay Time t
Rise Time
Turn−Off Delay Time
(VDD = 15 Vdc, ID = 1 A,
VGS = 4.5 V,
= 6 Ω)
6
R
G
Fall Time
Gate Charge Q
(VDS = 15 Vdc,
VGS = 10 Vdc,
= 5 A)
5
I
D
BODY−DRAIN DIODE RATINGS (Note 3)
Diode Forward On−Voltage
(IS = 1.7 Adc, VGS = 0 V)
(I
= 1.7 Adc, VGS = 0 V, TJ = 150°C)
S
Reverse Recovery Time
(IS = 5 A, VGS = 0 V,
/dt = 100 A/µs
=
dI
Reverse Recovery Stored Charge
(I
= 5 A, dIS/dt = 100 A/s, VGS = 0 V)
S
3. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
g
C
C
C
t
d(on)
t
d(off)
d(on)
t
d(off)
Q
Q
Q
V
t
t
t
Q
FS
iss
oss
rss
t
t
t
t
SD
rr
a
b
RR
30
−
30
−
−
mV/°C
−
µAdc
Vdc
−
−
−
−
1.0
20
nAdc
− − 100
Vdc
1.0
−
1.8
4.6
2.5
mV/°C
−
Ω
−
−
0.024
0.030
0.032
0.040
Mhos
− 10 −
− 680 950 pF
− 210 300
− 70 135
− 9 18
r
− 22 40
ns
− 45 80
f
r
− 45 80
− 13 30
− 27 50
ns
− 22 40
f
T
1
2
3
− 34 70
− 19 30
− 2.4 −
− 5.0 −
− 4.3 −
−
−
0.75
0.62
1.0
− 26 −
nC
Vdc
−
ns
− 11 −
− 15 −
− 0.015 − µC
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2
NTMD6N03R2
TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
12
10 V
6 V
10
4 V
8
6
4
, DRAIN CURRENT (AMPS)
2
D
I
0
0
0.40.2
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
3.4 V
3.6 V
3.8 V
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.05
0.045
0.035
VGS = 10
0.04
0.03
TJ = 25°C
VGS = 2.6 V
0.80.6 1.6
1 1.2 1.4 1.8
T = 125°C
3.2 V
3 V
2.8 V
12
VDS ≥ 10 V
10
8
6
TJ = 25°C
4
, DRAIN CURRENT (AMPS)
2
D
I
2
0
04215
V
GS
0.05
0.045
0.035
TJ = 25°C
0.04
0.03
TJ = 125°C
TJ = −55°C
3
, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS = 4.5 V
0.025
0.02
0.015
, DRAIN−TO−SOURCE RESISTANCE (Ω)
0.01
1
DS(on)
R
28
Figure 3. On−Resistance versus Drain Current
1.8
1.6
1.4
1.2
(NORMALIZED)
0.8
, DRAIN−TO−SOURCE RESISTANCE
0.6
DS(on)
R
ID = 3 A
V
GS
1
−50 0−25 5025
Figure 5. On−Resistance Variation with
T = 25°C
T = −55°C
34 1091112
ID, DRAIN CURRENT (AMPS)
765
0.025
0.02
0.015
, DRAIN−TO−SOURCE RESISTANCE (Ω)
0.01
DS(on)
R
and Temperature
10,000
= 10 V
1000
, LEAKAGE (nA)
DSS
I
10075 125
TJ, JUNCTION TEMPERATURE (°C)
150
Temperature
VGS = 10 V
21110987
1
312
ID, DRAIN CURRENT (AMPS)
654
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
VGS = 0 V
TJ = 150°C
TJ = 125°C
100
10
0152010 305
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
versus V oltage
25
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3
NTMD6N03R2
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
tr = Q2 x RG/(VGG − V
tf = Q2 x RG/V
GSP
GSP
)
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
and is read at a voltage corresponding to the
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
1600
C
1400
1200
1000
C, CAPACITANCE (pF)
iss
C
800
rss
600
400
200
0
VDS = 0 V
10 15 2010550 25
V
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VGS = 0 V
V
DS
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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C
C
C
4
TJ = 25°C
iss
oss
rss
NTMD6N03R2
10
8
6
V
DS
Q
1
4
2
Q
0
, GATE−TO−SOURCE VOLTAGE (VOLTS)
0816
GS
V
Q
2
3
246 101214
Qg, TOTAL GATE CHARGE (nC)
Q
T
V
GS
ID = 6 A
T
= 25°C
J
18 20
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
, due
rr
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
and low QRR specifications to
rr
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
6
VGS = 0 V
T
= 25°C
J
5
30
20
10
0
1000
100
t, TIME (ns)
10
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
V
VDD = 15 V
I
= 6 A
D
V
= 10 V
GS
1
1 100
R
, GATE RESISTANCE (Ω)
G
10
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
high di/dts. The diode’s negative di/dt during t
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
serves as a good indicator of recovery
b/ta
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
), have less stored charge and a softer
rr
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
t
d(off)
t
f
t
r
t
d(on)
is directly
a
4
3
2
, SOURCE CURRENT (AMPS)
1
S
I
0
0.5
0.6
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.7 0.8 0.9
Figure 10. Diode Forward Voltage versus Current
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NTMD6N03R2
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
) nor rated voltage (V
DM
) is exceeded, and that the
DSS
transition time (tr, tf) does not exceed 10 µs. In addition the
100
VGS = 12 V
SINGLE PULSE
= 25°C
T
A
10
1
0.1
, DRAIN CURRENT (AMPS)
D
I
0.01
0.1
V
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
1.0
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10 ms
dc
10
1.0 ms
100
total power averaged over a complete switching cycle must
not exceed (T
J(MAX)
− TC)/(R
).
JC
θ
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
325
300
275
250
225
200
175
150
125
100
75
50
AVALANCHE ENERGY (mJ)
25
, SINGLE PULSE DRAIN−TO−SOURCE
0
25 125 1501007550
AS
E
, STARTING JUNCTION TEMPERATURE (°C)
T
J
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
ID = 6 A
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NTMD6N03R2
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
THERMAL RESISTANCE
0.01
CHIP
JUNCTION
Rthja(t), EFFECTIVE TRANSIENT
SINGLE PULSE
0.001
1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01
t, TIME (s)
Figure 13. Thermal Response
0.0106
0.0253 F
0.0431
0.1406 F
0.1643
0.5064 F
0.3507
2.9468 F
0.4302
177.14 F
1.0E+02 1.0E+03
AMBIENT
di/dt
I
S
t
rr
t
t
a
b
TIME
t
p
0.25 I
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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−Y−
−Z−
NTMD6N03R2
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE AD
NOTES:
−X−
A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
G
N
C
SEATING
PLANE
0.10 (0.004)
H
D
0.25 (0.010) Z
M
Y
SXS
X 45
M
J
SOLDERING FOOTPRINT
1.52
0.060
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
INCHES
7.0
0.275
0.6
0.024
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
4.0
0.155
1.270
0.050
SCALE 6:1
mm
inches
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NTMD6N03R2/D
8
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