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NTLTD7900ZR2
Power MOSFET
9 A, 20 V, Logic Level, N−Channel
Micro8] Leadless
EZFETs™ are an advanced series of Power MOSFETs which
contain monolithic back−to−back Zener diodes. These Zener diodes
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature ultra low R
DS(on)
and true
logic level performance. EZFET devices are designed for use in low
voltage, high speed switching applications where power efficiency is
important. Typical applications are DC−DC converters, and power
management in portable and battery powered products such as
computers, printers, cellular and cordless phones.
Features
• Pb−Free Package is Available
Applications
• Zener Protected Gates Provide Electrostatic Discharge Protection
• Designed to Withstand 4000 V Human Body Model
• Ultra Low R
Battery Life
Provides Higher Efficiency and Extends
DS(on)
• Logic Level Gate Drive − Can be Driven by Logic ICs
• Micro8 Leadless Surface Mount Package − Saves Board Space
• I
Specified at Elevated Temperature
DSS
MAXIMUM RATINGS (T
Rating
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain Current (Note 1)
T
= 25°C
A
= 85°C
T
A
Pulsed Drain Current
(tp v 10 ms)
Continuous Source−Diode
Conduction (Note 1)
Total Power Dissipation (Note 1)
TA = 25°C
TA = 85°C
Operating Junction and Storage
Temperature Range
Thermal Resistance (Note 1)
Junction−to−Ambient
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to 1″ x1″ FR−4 board.
= 25°C unless otherwise noted)
J
Symbol 10 Sec
DSS
GS
I
I
DM
P
TJ, T
R
D
I
s
D
stg
q
JA
9.0
6.4
2.9 1.4 A
3.2
1.7
−55 to 150 °C
38 82 °C/W
Steady
State
20 V
±12 V
6.0
4.3
30 A
1.5
0.79
Unit
A
W
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9 AMPERES
20 VOLTS
R
DS(on)
= 4.5 V, ID = 6.5 A)
(V
GS
R
DS(on)
= 26 mW
= 31 mW
(VGS = 2.5 V, ID = 5.8 A)
DD
2.4 kW 2.4 kW
G
1
N−Channel N−Channel
1
Micro8 LEADLESS
CASE 846C
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
PIN ASSIGNMENT
Drain
8
Drain
7
6
Drain
5
Drain
(Bottom View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
G
2
S
1
MARKING DIAGRAM
1
7900
AYWW
Source 1
1
Gate 1
Drain
2
Source 2
3
Gate 2
4
S
G
2
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 6
1 Publication Order Number:
NTLTD7900ZR2/D
NTLTD7900ZR2
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
= 0 Vdc, ID = 250 mAdc)
(V
GS
Zero Gate Voltage Drain Current
(V
= 16 Vdc, VGS = 0 Vdc)
DS
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 85°C)
Gate−Body Leakage Current
(V
= "4.5 Vdc, VDS = 0 Vdc)
GS
(VGS = "12 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
= VGS, ID = 250 mAdc)
(V
DS
Static Drain−to−Source On−Resistance (Note 2)
(V
= 4.5 Vdc, ID = 6.5 Adc)
GS
= 2.5 Vdc, ID = 5.8 Adc)
(V
GS
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance C
(VDS = 16 Vdc, VGS = 0 V,
f = 1.0 MHz)
Transfer Capacitance C
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t
(VGS = 4.5 Vdc, VDD = 10 Vdc,
= 1.0 Adc, RG = 9.1 W)
I
D
(Note 2)
Fall Time t
Gate Charge
Gate Charge Q
(VGS = 4.5 Vdc, ID = 6.5 Adc,
V
= 10 Vdc)
DS
(Note 2)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 1.0 Adc, VGS = 0 Vdc)
I
= 1.0 Adc, VGS = 0 Vdc, TJ = 85°C)
S
(Note 2)
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
Symbol Min Ty p Max Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
C
t
d(on)
d(off)
Q
Q
V
iss
oss
rss
SD
20 24 −
−
−
−
−
−
−
−
−
1.0
20
1.0
500
0.4 0.67 1.0
−
−
21
27
26
31
− 7.4 15
− 237 400
− 4.1 10 pF
− 0.55 1.0 ms
r
− 1.17 2.0
− 1.87 3.0
f
T
1
2
− 4.8 7.0
− 12 18
− 0.7 −
− 3.7 − nC
−
−
0.69
0.62
0.8
−
Vdc
mAdc
mAdc
mAdc
Vdc
mW
pF
ms
nC
Vdc
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NTLTD7900ZR2
TYPICAL ELECTRICAL CHARACTERISTICS
8
6
4
, GATE−CURRENT (mA)
2
GSS
I
0
VGS, GATE−TO−SOURCE VOLTAGE (V)
12 15 189630
Figure 1. Gate−Current versus Gate−Source
Voltage
30
24
18
12
, DRAIN CURRENT (A)
D
I
6
0
2.4 V
2.8 V
3.5 V
4.5 V
10 V
0
2 0.4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
46810
2.2 V
2.0 V
1.8 V
1.6 V
1.4 V
VGS = 1.2 V
10,000
1000
100
TJ = 150°C
TJ = 25°C
, GATE−CURRENT (mA)
I
GSS
10
1
0.1
0.01
0
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 2. Gate−Current versus Gate−Source
Voltage
30
24
18
12
, DRAIN CURRENT (A)
6
D
I
0
0 0.8 1.2 1.6 2.4
VGS, GATE−TO−SOURCE VOLTAGE (V)
TC = 25°C
TC = 125°C
TC = −55°C
12 15963
2.0
Figure 3. On−Region Characteristics
0.06
0.05
0.04
0.03
0.02
0.01
, DRAIN−TO−SOURCE RESISTANCE (W)
0
0 6 12 18
DS(on)
R
Figure 5. On−Resistance versus Drain Current
Figure 4. Transfer Characteristics
VGS = 2.5 V
VGS = 4.5 V
24 30
ID, DRAIN CURRENT (A)
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3
NTLTD7900ZR2
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
known as the plateau voltage, V
remains virtually constant at a level
GS
. Therefore, rise and fall
SGP
times may be approximated by the following:
t
= Q2 x RG/(VGG − V
r
tf = Q2 x RG/V
GSP
GSP
)
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
RG = the gate drive resistance
and Q
and V
2
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
and is read at a voltage corresponding to the
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 8) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
1200
1000
800
600
400
C, CAPACITANCE (pF)
200
0
TJ = 25°C
V
C
oss
C
and C
iss
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
are below 10 pF
rss
51015
VOLTAGE (V)
Figure 6. Capacitance Variation
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4
GS
= 0 V
200
NTLTD7900ZR2
5
4
3
2
1
, GATE−TO−SOURCE VOLTAGE (V)
GS
0
V
10
TJ = 25°C
= 6.5 A
I
D
TJ = 25°C
V
= 0 V
GS
812146420
10
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Gate−to−Source
10,000
t
f
t
d(off)
t
t
d(on)
r
1000
t, TIME (ns)
VDS = 10 V
I
= 6.5 A
D
= 4.5 V
V
GS
100
1 10 100
RG, GATE RESISTANCE (W)
Figure 8. Resistive Switching Time Variation
versus Gate Resistance
1.8
1.6
1.4
ID = 9 A
V
GS
= 4.5 V
1
TJ = 150°C
, SOURCE CURRENT (A)
S
I
TJ = 25°C
0.1
0
0.2
0.4 0.6 0.8 1
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Diode Forward Voltage versus Current
0.2
ID = 250 mA
0.1
0
−0.1
−0.2
, THRESHOLD VARIANCE (V)
−0.3
GS(th)
V
−0.4
−25 12575 100
−50 0 25 50 150
TJ, JUNCTION TEMPERATURE (°C)
1.2
1.0
−0.8
RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE
0.6
−50 0 25 50 150
−25 125
75 100
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. On−Resistance Variation with
Temperature
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
, DRAIN−TO−SOURCE RESISTANCE (W)
DS(on)
R
0
51015
TJ = 125°C
TJ = 25°C
TJ = −55°C
20 25
ID, DRAIN CURRENT (A)
300
Figure 11. Threshold Voltage
Figure 12. On−Resistance versus Drain
Current and Temperature
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5
NTLTD7900ZR2
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
r(t), EFFECTIVE TRANSIENT
0.01
THERMAL RESISTANCE (NORMALIZED)
10−410−210−11
SINGLE PULSE
10−3 100
P
(pk)
t
1
DUTY CYCLE, D = t1/t
t
2
t, TIME (seconds)
Figure 13. Thermal Response
ORDERING INFORMATION
Device Package Shipping
NTLTD7900ZR2 Micro8 LL 3000 / Tape & Reel
NTLTD7900ZR2G Micro8 LL
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
3000 / Tape & Reel
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
J(pk)
2
− TC = P
(pk)
1
R
(t)
q
JC
10 1000
†
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6
NTLTD7900ZR2
PACKAGE DIMENSIONS
Micro8 LEADLESS
CASE 846C−01
ISSUE C
INDEX AREA
2X
NOTE 4
DETAIL Z
0.15 T
2X
W0.10 YT
W0.05 T
8XD
6X
G
0.15 T
U 4X
TOP VIEW
E
8
7
6
5
VIEW AA−AA
SEATING
T
A
W
Y
J
B
PLANE
AA
8
7
6
5
NOTE 6
K
AA
C
0.10 T
8X
0.08
T
L
8X
L
1
2
F
3
P
4
SIDE VIEW
NOTE 4L1
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. THE TERMINAL #1 IDENTIFIER AND TERMINAL
NUMBERING CONVENTION SHALL CONFORM TO
JESD 95−1 SPP−012. DETAILS OF TERMINAL #1
IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE
TERMINAL #1 IDENTIFIER MAY BE EITHER A
MOLD OR MARKED FEATURE.
4. DIMENSION D APPLIES TO METALLIZED
TERMINAL AND IS MEASURED BETWEEN
0.25 MM AND 0.30 MM FROM TERMINAL TIP.
DIMENSION L1 IS THE TERMINAL PULL BACK
FROM PACKAGE EDGE, UP TO 0.1 MM IS
ACCEPTABLE. L1 IS OPTIONAL.
5. DEPOPULATION IS POSSIBLE IN A
SYMMETRICAL FASHION.
6. OPTIONAL SIDE VIEW CAN SHOW LEADS 5 AND
8 REMOVED.
MILLIMETERS
DIM MIN MAX
A 3.30 BSC
B 3.30 BSC
C 0.85 0.95
D 0.25 0.35
E 1.30 1.50
F 2.55 2.75
G 0.65 BSC
H 0.95 1.15
J 0.25 BSC
K 0.00 0.05
L 0.35 0.45
L1 0.00 0.10
P 1.28 1.38
0.17 TYP
U
DETAIL Z
H
SOLDERING FOOTPRINT*
2.75
1.23
1.50
3.60
0.40
8X
0.58
8X
0.33
0.65 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NTLTD7900ZR2
EZFET is a trademark of Semiconductor Components Industries, LLC (SCILLC).
Micro8 is a trademark of International Rectifier Corporation.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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For additional information, please contact your
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NTLTD7900ZR2/D
8
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