OLYMPUS E-100 RS Description of Mechanism V1
H. DESCRIPTION OF MECHANISM
E-100RS
H. DESCRIPTION OF MECHANISM
[1] CA1 CIRCUIT DESCRIPTION ........................................................................ H-2,3,4
[2] CA2 CIRCUIT DESCRIPTION .............................................................................. H-5
[3] TC2/CA3 CIRCUIT DESCRIPTION ...................................................................... H-6
[4] PW1 POWER CIRCUIT DESCRIPTION ............................................................... H-7
[5] PW1 STOROBE CIRCUIT DESCRIPTION .......................................................... H-8
[6] SY1 CIRCUIT DESCRIPTION .................................................................... H-9,10,11
SERVER_DIS
H-1
Ver. 1
H. DESCRIPTION OF MECHANISM
10
9 6 5 4 3 2 1
13
14 15 16 17
18
19
20
G
R
G
R
G
R
B
G
B
G
B
G
G
R
G
R
G
R
B
G
B
G
B
G
Vertical register
Horizontal register
Note
Note: Photo sensor
VOUT
GND
NC
NC
V
ø3
øSUB
NC
C
SUB
NC
V
L
øRG
12
GND
11
VDD
7
GND
8
NC
V
ø2B
Vø2A
Vø1
Hø1
Hø2
[1 ]CA1 CIRCUIT DESCRIPTION
1. IC Configuration
IC903 (ICX267) CCD imager
IC902, IC904, IC908 (74ACT04MTC) H driver
IC907 (CXD3400N) V driver
IC905 (AD9840) CDS, AGC, A/D converter
2. IC903 (CCD)
[Structure]
Interline type CCD image sensor
Optical size Diagonal 8 mm (1/2 type)
Effective pixels 1392 (H) X 1040 (V)
Pixels in total 1434 (H) X 1050 (V)
Actual pixels 1360 (H) X 1024 (V)
Optical black
Horizontal (H) direction: Front 2 pixels, Rear 40 pixels
Vertical (V) direction: Front 8 pixels, Rear 2 pixels
Dummy bit number Horizontal : 20 Vertical : 3
Pin 1
2
E-100RS
Fig. 1-2. CCD Block Diagram
V
2
Pin 11
Fig. 1-1.Optical Black Location (Top View)
Pin No.
1
2, 3
4
5, 6, 8,
14, 16
7, 9, 12
10
11
13
15
17
Symbol
Vφ
Vφ
2A, Vφ2B
Vφ3
NC
GND
VOUT
VDD
φSUB
CSUB
VL
1
8
H
40
Pin Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
Circuit power
Substrate clock
Substrate bias
Protection transistor bias
Waveform
GND
DC
DC
DC
Voltage
-8.0 V, 0 V
-8.0 V, 0 V, 15 V
-8.0 V, 0 V
0 V
Aprox. 7 V
15 V
Different from every CCD
Different from every CCD
-8 V
18
19
20
φRG
Hφ
Hφ
Reset gate clock
1
2
Horizontal register transfer clock
Horizontal register transfer clock
12 V, 17 V
0 V, 5 V
0 V, 5 V
Table 1-1. CCD Pin Description
H-2 Ver.1SERVER_DIS
DESCRIPTION OF MECHANISME-100RS
3. IC902, IC904, IC908 (H Driver) and IC907
(V Driver)
An H driver and V driver are necessary in order to generate the clocks (vertical transfer clock, horizontal transfer
clock and electronic shutter clock) which driver the CCD.
IC902, IC904 and IC908 are inverter IC which drives the
horizontal CCDs (H1 and H2). In addition the XV1-XV3 signals which are output from IC102 are the vertical transfer
clocks, and the XSG1 and XSG signal which is output from
IC102 is superimposed onto XV2A and XV2B at IC907 in
order to generate a ternary pulse. In addition, the XSUB
signal which is output from IC102 is used as the sweep
pulse for the electronic shutter, and the RG signal which is
output from IC102 is the reset gate clock.
14
CC
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
V
13
6A
12
6Y
11
5A
10
5Y
4A
9
4Y
8
4. IC905 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to
Pin (30) of IC905. There are S/H blocks inside IC905 generated from the XSHP and XSHD pulses, and it is here that
CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally
into a 10-bit signal, and is then input to IC102 of the CA2
circuit board. The gain of the AGC amplifier is controlled by
serial data which is output from IC102 of the CA2 circuit
board.
PBLK
CCDIN
CLPDM
AUX1IN
AUX2IN
AVDD
CDS
CLP
CLP
4 dB
MUX
AVSS
2~36 dB
2:1
VGA
MUX
10
BUF
2:1
CONTROL
REGISTERS
DIGITAL
INTERFACE
SCK
SL
SEN
SDATA
Offset
DAC
8
CLPOB
CLP
10-BIT
ADC
BANDGAP
REFERENCE
INTERNAL
INTERNAL
TIMING
Fig. 1-5. IC905 Block Diagram
AD9840
BIAS
DATA
SHDSHP
CLK
DRVDD
DRVSS
10
DOUT
VRT
VRB
CML
DVDD
DVSS
Fig. 1-3. IC902, IC904 and IC908 Block Diagram
V
DD
1
Input
Buffer
XSHT
2
XV2B
3
XSG2
4
NC
5
XV2A
6
NC
7
XSG1
8
XV1
9
XV3
10
SHT
V2B
V
NC
NC
V
V2A
V1
V3
GND
20
19
L
18
17
16
H
15
14
13
12
11
Fig. 1-4. IC907 Block Diagram
H-3Ver.1 SERVER_DIS
H. DESCRIPTION OF MECHANISM
E-100RS
5. Transfer of Electric Charge by the Horizontal CCD
The transfer system for the horizontal CCD emplays a 2-phase drive method.
The electric charges sent to the final stage of the horizontal CCD are transferred to the floating diffusion, as shown in Fig. 1-
6. RG is turned on by the timing in (1), and the floating diffusion is charged to the potential of PD. The RG is turned off by the
timing in (2). In this condition, the floating diffusion is floated at high impedance. The H1 potential becomes shallow by the
timing in (3), and the electric charge now moves to the floating diffusion.
Here, the electric charges are converted into voltages at the rate of V = Q/C by the equivalent capacitance C of the floating
diffusion. RG is then turned on again by the timing in (1) when the H1 potential becomes deep.
Thus, the potential of the floating diffusion changes in proportion to the quantity of transferred electric charge, and becomes
CCD output after being received by the source follower. The equivalent circuit for the output circuit is shown in Fig. 1-7.
(1)
H1 H2 H1 H2 H1 HOG RG
CCD OUT
Floating diffusion
(2)
H1 H2 H1 H2 H1 HOG RG
PD
PD
CCD OUT
H1
H2
RG
15.5V
(1) (2) (3)
5.0V
0V
5.0V
0V
12V
(3)
H1 H2 H1 H2 H1 HOG RG
CCD OUT
Fig. 1-6. Horizontal Transfer of CCD Imager and Extraction of Signal Voltage
Reset gate pulse
Direction of transfer
H Register
Electric
charge
Floating diffusion gate is
floated at a high impedance
C is charged
equivalently
12V Pre-charge drain bias(PD)
Voltage output
Fig. 1-7. Theory of Signal Extraction Operation
6. Lens drive block
6-1. Shutter drive
The shutter drive signal (SHUTTER) which is output by the
ASIC and the aperture enable signal (AE SW) cause a positive and negative voltage are applied to the aperture drive
coil to open and close the lens aperture.
CCD OUT
RG pulse peak signal
Signal voltage
6-2. Iris drive
When in the aperture enable (AE SW) state, the target aperture value signal (IRIS PWM) which is output by the ASIC
and the aperture value signal (HALL OUT +/put by the lens are compared so that feedback control can
be carried out.
6-3. Focus drive
When the drive signals (FRSTB, FCW, FOEB and FCLK)
which are output from the ASIC, the focus stepping motor is
sine-wave driven by the micro-step motor driver (IC953). Detection of the standard focusing positions is carried out by
means of the photointerruptor (FOCUS PI) inside the lens
block.
6-4. Zoom drive
When the drive signals (ZRSTB, ZCW, ZOEB and ZCLK)
which are output from the ASIC, the zoom stepping motor is
sine-wave driven by the micro-step motor driver (IC954). Detection of the zoom positions is carried out by means of
photoreflector (ZOOM PI) inside the lens block.
H-4 Ver.1SERVER_DIS
Black level
) which is out-
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