OLYMPUS C-310 Zoom DESCRIPTION OF MECHANISM

H. DESCRIPTION OF MECHANISM

X-100/D-540ZOOM/C-310ZOOM

H. DESCRIPTION OF MECHANISM

[1] CP1 CIRCUIT DESCRIPTION ................................................................................ H-2

[2] PWA POWER CIRCUIT DESCRIPTION ................................................................. H-6

[3] ST1 STROBE CIRCUIT DESCRIPTION................................................................. H-7

[4] SYA CIRCUIT DESCRIPTION................................................................................. H-8

H-1 Ver.1

H. DESCRIPTION OF MECHANISM X-100/D-540 ZOOM/C-310 ZOOM

2

5

2

[1] CP1 CIRCUIT DESCRIPTION

1. IC Configuration

IC903 (RJ23P3AA3DT) CCD imager
IC901 (LR36688U) V driver
IC902 (AD9847AKCPZ) CDS, AGC, A/D converter

2. IC903 (CCD)

[Structure]

Interline type CCD image sensor

Optical size 1/2.7 type format
Effective pixels 2080 (H) X 1544 (V)
Pixels in total 2096 (H) X 1560 (V)
Optical black

Horizontal (H) direction: Front 2 pixels, Rear 54 pixels
Vertical (V) direction: Front 5 pixels, Rear 2 pixels

Dummy bit number Horizontal : 24 Vertical :2

Pin 11

V

Pin 1

H

54

Fig. 1-1.Optical Black Location (Top View)

GND

19

OOFD

7

20

OS

Vertical shift register

1

Output part

Horizontal shift register

5

φRS

8

9

: Photo diode

φH2

φH1

OD

10
11
12
13
14
15
16
17
18

3
4

φV5A
φV4

φV3B
φV3A
φV2
φV1B

φV1A
φV6
φV5B

OFD
PW

Pin No.

1

2, 19

3

4

5

6

7

8

9

10, 18

11

12, 13

14

Symbol

OD

GND

φrs

NC

φH1

φH2

φV5A, φV5B

φV4

φV3B, φV3A

φV2

Pin Description

Output transistor drain

GND

Overflow drainOFD

P wellPW

Reset gate clock

Overflow drain outputOOFD

Horizontal register transfer clock

Horizontal register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Fig. 1-2. CCD Block Diagram

Waveform

DC

GND

DC

DC

DC

Voltage

15.5 V

0 V

Approx. 7 V
(Different from every CCD)

-8 V

7.8 V, 12 V

8 V

0 V, 4.7 V

0 V, 4.7 V

-8.0 V, 0 V, 15.5 V

-8.0 V, 0 V

-8.0 V, 0 V

-8.0 V, 0 V

15, 16

17

20

φV1B, φV1A

φV6

Vertical register transfer clock

Vertical register transfer clock

Signal outputOS

DC

-8.0 V, 0 V

-8.0 V, 0 V

Approx. 7.0 V

Table 1-1. CCD Pin Description

H-2 Ver. 1

H. DESCRIPTION OF MECHANISMX-100/D-540 ZOOM/C-310 ZOOM

C

B
M

A

A

B

V

V

V

3. Part of IC902 (H Driver) and IC901 (V Driver)

An H driver (part of IC902) and V driver (IC901) are neces­sary in order to generate the clocks (vertical transfer clock,
horizontal transfer clock and electronic shutter clock) which
driver the CCD.
IC902 has the generation of horizontal transfer clock and
the function of H driver, and is an inverter IC which drives
the horizontal CCDs (H1 and H2). In addition the XV1-XV6
signals which are output from IC101 are the vertical trans­fer clocks, and the XSG1 and XSG signal which is output
from IC101 is superimposed onto XV1, XV3 and XV5 at
IC901 in order to generate a ternary pulse. In addition, the
XSUB signal which is output from IC101 is used as the
sweep pulse for the electronic shutter, and the RG signal
which is output from IC101 is the reset gate clock.

GND

GND

V1~V3

VL

VH

GND

V5A, V7

VL

VH

GND

V8A~V9

VL

VH

GND

V8B~V9

VL

VH

POFD

VL

1X~V3X

5X, V7X

VH5AX,
VH7AX

8X~V9X

VH8AX~
VH9AX

VH8BX~
VH9BX

OFDX

VH

VL VDD

MIX

MIX

MIX

4. IC906 (H Driver, CDS, AGC and A/D converter)

IC906 contains the functions of H driver, CDS, AGC and A/
D converter. As horizontal clock driver for CCD image sen­sor, H¯1 (A and B) and H¯2 (A and B) are generated in­side, and output to CCD.
The video signal which is output from the CCD is input to
pins (29) of IC902. There are sampling hold blocks inside
IC905 generated from the SHP and SHD pulses, and it is
here that CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier (VGA: Variable Gain Amplifier).
It is A/D converted internally into a 10-bit signal, and is then
input to ASIC (IC101). The gain of the VGA amplifier is con­trolled by pin (36)-(38) serial signal which is output from
ASIC (IC101).

VRB

VRT

VREF

CDIN

RG

H1-H4

2~36 dB

VGA

PxGA

CDS

HORIZONTAL

4

DRIVERS

CLAMP

INTERNAL

CLOCKS

PRECISION

TIMING

CORE

SYNC

GENERATOR

VD

HD

Fig. 1-4. IC902 Block Diagram

ADC

CLAMP

INTERNAL

REGISTERS

SL

SCK

SDATA

12

DOUT

CLPO
CLPD
PBLK
CLI

Fig. 1-3. IC901 Block Diagram

H-3 Ver. 1

H. DESCRIPTION OF MECHANISM X-100/D-540 ZOOM/C-310 ZOOM

5. Transfer of Electric Charge by the Horizontal CCD

The transfer system for the horizontal CCD emplays a 2-phase drive method.
The electric charges sent to the final stage of the horizontal CCD are transferred to the floating diffusion, as shown in Fig. 1-

5. RG is turned on by the timing in (1), and the floating diffusion is charged to the potential of PD. The RG is turned off by the
timing in (2). In this condition, the floating diffusion is floated at high impedance. The H1 potential becomes shallow by the
timing in (3), and the electric charge now moves to the floating diffusion.
Here, the electric charges are converted into voltages at the rate of V = Q/C by the equivalent capacitance C of the floating
diffusion. RG is then turned on again by the timing in (1) when the H1 potential becomes deep.
Thus, the potential of the floating diffusion changes in proportion to the quantity of transferred electric charge, and becomes
CCD output after being received by the source follower. The equivalent circuit for the output circuit is shown in Fig. 1-6.

(1)

H1 H2 H1 H2 H1 HOG RG

CCD OUT

Floating diffusion

(2)

H1 H2 H1 H2 H1 HOG RG

PD

H1

H2

CCD OUT

PD

RG

(1) (2) (3)

3.5V
0V

3.5V
0V

13.5V
0V

(3)

H1 H2 H1 H2 H1 HOG RG

Reset gate pulse

Direction of transfer

H Register

Electric
charge

Floating diffusion gate is
floated at a high impedance.

CCD OUT

CCD OUT

Fig. 1-5. Horizontal Transfer of CCD Imager and Extraction of Signal Voltage

12V Pre-charge drain bias (PD)

Voltage output

C is charged
equivalently

RG pulse leak signal

Signal voltage

Black level

Fig. 1-6. Theory of Signal Extraction Operation

H-4 Ver. 1

H. DESCRIPTION OF MECHANISMX-100/D-540 ZOOM/C-310 ZOOM

6. Circuit description
6-1. Digital clamp

The optical black section of the CCD extracts averaged val­ues from the subsequent data to make the black level of
the CCD output data uniform for each line. The optical black
section of the CCD averaged value for each line is taken
as the sum of the value for the previous line multiplied by
the coefficient k and the value for the current line multiplied
by the coefficient 1-k.

6-2. Signal processor

γγ

1.

γ correction circuit

γγ

This circuit performs (gamma) correction in order to main­tain a linear relationship between the light input to the cam­era and the light output from the picture screen.

The AF, AE, AWB, shutter, and AGC value are computed
from this data, and three exposures are made to obtain the
optimum picture. The data which has already been stored
in the SDRAM is read by the CPU and color generation is
carried out. After AWB and γ processing are carried out, a
matrix is generated and aperture correction is carried out
for the Y signal, and the data is then compressed by JPEG
and is then written to card memory.
When the data is to be output to an external device, it is
taken data from the memory and output via the USART.
When played back on the LCD and monitor, data is trans­ferred from memery to the SDRAM, and the image is then
elongated so that it is displayed over the SDRAM display
area.

2. Color generation circuit

This circuit converts the CCD data into RGB signals.

3. Matrix circuit

This circuit generates the Y signals, R-Y signals and B-Y
signals from the RGB signals.

4. Horizontal and vertical aperture circuit

This circuit is used gemerate the aperture signal.

6-3. AE/AWB and AF computing circuit

The AE/AWB carries out computation based on a 64-seg­ment screen, and the AF carries out computations based
on a 6-segment screen.

6-4. SDRAM controller

This circuit outputs address, RAS, CAS and AS data for
controlling the SDRAM. It also refreshes the SDRAM.

6-5. Communication control

1. SIO

This is the interface for the 8-bit microprocessor.

2. PIO/PWM/SIO for LCD

8-bit parallel input and output makes it possible to switch
between individual input/output and PWM input/output.

6-6. TG/SG

Timing generated for 3 million pixel CCD control.

6-7. Digital encorder

It generates chroma signal from color difference signal.

7. Outline of Operation

When the shutter opens, the reset signals (ASIC and CPU)
and the serial signals (take a picture commands) from
the 8-bit microprocessor are input and operation starts.
When the TG/SG drives the CCD, picture data passes
through the A/D and CDS, and is then input to the ASIC as
12-bit data.

8. LCD Block

LCD block is in the CP1 board, and it is constructed by
VCOM generation circuit etc.
The video signal from the ASIC are 6-bit digital signal, and
input to LCD directly. It is converted into RGB signals at
driver circuit in the LCD.
The VCOM (common polar voltage: AC) and the R, G and
B signals becomes greater, the display becomes darker; if
the difference in potential is smaller, the element opens and
the LCD become brighter. And also the timing pulse except
the video signal is input to LCD directly from ASIC.

9. Lens drive block

9-1. Shutter drive

The shutter drive signal (SIN1 and SIN2) which is output
from the ASIC expansion port (IC106) is drived the shutter
constant level driver, and then shutter plunger is opened and
closed.

9-2. Iris drive

The iris stepping motor drive signals (IIN1 and IIN2) which
are output from the ASIC (IC101) are used to drive by the
motor driver (IC951).

9-3. Focus drive

The focus stepping motor drive signals (FIN1, FIN2, FIN3
and FIN4) which are output from the ASIC (IC101) are used
to drive by the motor driver (IC951). Detection of the stan­dard focusing positions is carried out by means of the
photointerruptor (PI) inside the lens block.

9-4. Zoom drive

The zoom stepping motor drive signals (ZIN1 and ZIN2)
which are output from the ASIC (IC101) are used to drive by
the motor driver (IC951). Detection of the zoom positions is
carried out by means of photoreflector (PR) inside the lens
block.

H-5 Ver. 1

H. DESCRIPTION OF MECHANISM X-100/D-540 ZOOM/C-310 ZOOM

[2] PWA POWER CIRCUIT DESCRIPTION

1. Outline

This is the main power circuit, and is comprised of the fol­lowing blocks.
Switching controller (IC501)
Analog +3.45 V (A) power output (L5003, Q5009, IC502)
Analog +15.5 V (A) and -8 V (A) system power output

(T5001, Q5001)
Digital 3.25 V (D) power output (L5004)
Digital 1.53 V (D) power output (L5005)
LCD 15 V (L) power output (L5001, Q5002)
LCD 5 V (L) power output (L5003, Q5009, Q5006)
Backlight power output (L5002)
Motor (BOOST system) power output (IC955, L9551,
Q9551)

3. Analog System Power Output

+15.5 V (A), +4.7 V (A) and -8.0 V (A) are output. Feedback
for the +15.5 V (A) is provided to the switching controller
(Pin (53) of IC501) so that PWM control can be carried out.

4. Digital 3.25 V Power Output

+3.25 V (D) is output. Feedback for the +3.25 V (D) is pro­vided to the swiching controller (Pin (32) of IC501) so that
PWM control can be carried out.

5. Digital 1.53 V Power Output

+1.53 V (D) is output. Feedback for the +1.53 V (D) is pro­vided to the swiching controller (Pin (31) of IC501) so that
PWM control can be carried out.

2. Switching Controller (IC501)

This is the basic circuit which is necessary for controlling
the power supply for a PWM-type switching regulator, and
is provided with seven built-in channels, only CH2 (digital

3.25 V), CH3 (digital 1.53 V), CH4 (analog 4.7 V and digital
5 V), CH5 (analog system) CH6 (LCD system) and CH7
(backlight system) are used. Feedback from 3.25 V (D)
(CH2), 15.3 V (D) (CH3), digital system (CH4), analog sys­tem (CH5), LCD system (CH6) and backlight system (CH7)
power supply outputs are received, and the PWM duty is
varied so that each one is maintained at the correct voltage
setting level.
Feedback for the backlight power (CH7) is provided to the
both ends voltage of registance so that regular current can
be controlled to be current that was setting.

2-1. Short-circuit protection circuit

If output is short-circuited for the length of time determined
by the condenser which is connected to Pin (42) of IC501,
all output is turned off. The control signal (P ON) are recon­trolled to restore output.

6. Digital System Power Output

+5.0 V (D) is output. Feedback for the +5.0 V (D) is pro­vided to the swiching controller (Pin (52) of IC501) so that
PWM control can be carried out.

7. LCD System Power Output

+15 V (L) and +5 V (L) is output. Feedback for the +15 V (L)
is provided to the switching power controller (Pin (56) of
IC501) so that PWM control can be carried out.

8. Backlight Power Output

Regular current (17 mA) is being transmitted to LED for
LCD backlight. Feedback for the both ends voltage of
registance that is being positioned to in series LED are pro­vided to the switching controller (Pin (48) of IC501) so that
PWM control to be carried out.

9. Motor (Boost System) Power Output

3.7 V is output. Feedback for the 3.7 V is provided to the
switching power controller (Pin (1) of IC955) so that PWM
control can be carried out.

H-6 Ver. 1

H. DESCRIPTION OF MECHANISMX-100/D-540 ZOOM/C-310 ZOOM

[3] ST1 STROBE CIRCUIT DESCRIPTION

1. Charging Circuit

When UNREG power is supplied to the charge circuit and
the CHG signal from SYA circuit on the CP1 board becomes
High (3.3 V), the charging circuit starts operating and the
main electorolytic capacitor is charged with high-voltage
direct current.
However, when the CHG signal is Low (0 V), the charging
circuit does not operate.

1-1. Power switch

When the CHG signal switches to Hi, Q5407 turns ON and
the charging circuit starts operating.

1-2. Power supply filter

C5401 constitutes the power supply filter. They smooth out
ripples in the current which accompany the switching of the
oscillation transformer.

1-3. Oscillation circuit

This circuit generates an AC voltage (pulse) in order to in­crease the UNREG power supply voltage when drops in
current occur. This circuit generates a drive pulse with a
frequency of approximately 50-100 kHz. Because self-ex­cited light omission is used, the oscillation frequency
changes according to the drive conditions.

2. Light Emission Circuit

When RDY and TRIG signals are input from the ASIC ex­pansion port, the stroboscope emits light.

2-1. Emission control circuit

When the RDY signal is input to the emission control cir­cuit, Q5409 switches on and preparation is made to let cur­rent flow to the light emitting element. Moreover, when a
STOP signal is input, the stroboscope stops emitting light.

2-2. Trigger circuit

When a TRIG signal is input to the trigger circuit, D5405
switches on, a high-voltage pulse of several kilovolts is gen­erated inside the trigger circuit, and this pulse is then ap­plied to the light emitting part.

2-3. Light emitting element

When the high-voltage pulse form the trigger circuit is ap­plied to the light emitting part, currnet flows to the light emit­ting element and light is emitted.

Beware of electric shocks.

1-4. Oscillation transformer

The low-voltage alternating current which is generated by
the oscillation control circuit is converted to a high-voltage
alternating current by the oscillation transformer.

1-5. Rectifier circuit

The high-voltage alternating current which is generated at
the secondary side of T5401 is rectified to produce a high­voltage direct current and is accumulated at electrolytic ca­pacitor C5412 on the main circuit board.

1-6. Voltage monitoring circuit

This circuit is used to maintain the voltage accumulated at
C5412 at a constance level.
After the charging voltage is divided and converted to a
lower voltage by R5417 and R5419, it is output to the SYA
circuit on the CP1 board as the monitoring voltage VMONIT.
When this VMONIT voltage reaches a specified level at the
SYA circuit on the CP1 board, the CHG signal is switched
to Low and charging is interrupted.

H-7 Ver. 1

H. DESCRIPTION OF MECHANISM X-100/D-540 ZOOM/C-310 ZOOM

[4] SYA CIRCUIT DESCRIPTION

1. Configuration and Functions

For the overall configuration of the SYA block, refer to the block diagram. The configuration of the SYA block centers around
a 8-bit microprocessor (IC301).
The 8-bit microprocessor handles the following functions.

1. Operation key input, 2. Clock control, 3. Power ON/OFF, 4. Storobe charge control

Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21 SCAN OUT0

22 IC

23 XCOUT

24

25 RESET

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

Signal

BATTERY

VMONIT

SCAN IN4

COMREQ

SCAN IN1

SCAN IN2

SCAN IN3

CARD SW

AVSS

CHG ON

SCAN OUT2

BATOFF

SREQ

LCD ON3

SCAN IN0

SCK/PRG SCK

VDD

SO/PRG SO

SI/PRG SI

SCAN OUT1

XCIN

XOUT

XIN

VSS

VDD

PA ON2

LCD ON2

P ON

PA ON

LCD ON

BL ON

ASIC TEST

VSS

PLLEN

MAIN RESET

AVREF ON

BACKUP CTL

I/O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Outline

I

I

I

I

I

I

I

I

-

I

I

I

I

I

-

I

I

I

-

I

-

Battery voltage detection

Main capacitor charge voltage detection

Key matrix input

Command request

Key matrix input

Key matrix input

Key matrix input

Card switch detection

GND

Strobe charge control

Key matrix output

Battery off detection signal input

Serial communication requirement signal

D/D converter (LCD system) ON/OFF signal 3

Key matrix input

Serial clock output/serial clock output for flash

VDD

Serial data output/serial data output for flash

Serial data input/serial data input for flash

Key matrix output

Key matrix output

Power for program writing

Clock oscillation terminal

Clock oscillation terminal (32.768 kHz)

Reset input

Main clock oscillation terminal

Main clock oscillation terminal (4 MHz)

GND

VDD

D/D converter (analog system) ON/OFF signal 2

D/D converter (LCD system) ON/OFF signal 2

D/D converter (digital system) ON/OFF signal

D/D converter (analog system) ON/OFF signal

D/D converter (LCD system) ON/OFF signal

Backlight ON/OFF

ASIC control signal (ZTEST)

GND

PLL oscilllation ON/OFF

System reset (MRST)

AD VREF ON/OFF signal

Backup battery charge control

H-8

Ver. 1

H. DESCRIPTION OF MECHANISMX-100/D-540 ZOOM/C-310 ZOOM

42

43

44

SCAN OUT3

AVDD

AVRE F

O Key matrix output

I

I

Table 4-1. 8-bit Microprocessor Port Specification

VDD

Analog standard voltage input terminal

2. Internal Communication Bus

The SYA block carries out overall control of camera operation by detecting the input from the keyboard and the condition of
the camera circuits. The 8-bit microprocessor reads the signals from each sensor element as input data and outputs this data
to the camera circuits (ASIC) or to the LCD display device as operation mode setting data. Fig. 4-1 shows the internal
communication between the 8-bit microprocessor and ASIC.

8-bit micro processor ASIC

setting of
external port

communi­cation

MRST

ZTEST

PLLEN

SI

SO

SCK

SREQ

COMREQ

Fig. 4-1 Internal Bus Communication System

3. Key Operaiton

For details of the key operation, refer to the instruction manual.

SCAN

SCAN
OUT

IN

0

0

1

2

3

REC

OFF

PLAY

123

2nd

TELE

UP

LEFT

Table 4-2. Key Operation

1st

WIDE

DOWN

RIGHT

H-9

USB CONNECT

DC IN

LCD

TEST

4

CARD

OK

PW_TEST

Ver. 1

H. DESCRIPTION OF MECHANISM X-100/D-540 ZOOM/C-310 ZOOM

4. Power Supply Control

The 8-bit microprocessor controls the power supply for the overall system.
The following is a description of how the power supply is turned on and off. When the battery is attached, IC955 is operating
and creating 3.6 V, a regulated 3.2 V voltage is normally input to the 8-bit microprocessor (IC301) by IC302, clock counting
and key scanning is carried out even when the power switch is turned off, so that the camera can start up again.
When the power switch is off, the 8-bit microprocessor halts 4 MHz of the main clock, and operates 32.768 kHz of subclock.
When the battery is removed, the 8-bit microprocessor power switches the capacitor for memory backup by IC302, and
operates at low consumption. At this condition, the 8-bit microprocessor halts the main clock, and operates clock counting by
sub clock.
Also, the battery for backup is charged 10 hours from it to be attached.
When the power switch is on, the 8-bit microprocessor starts processing. The 8-bit microprocessor first sets both the PON
signal at pin (32) and the PAON signal at pin (33) to High, and then turn on the power circuit. After PON signal is to High, sets
external port of ASIC after approximately 100 ms. According to setting of this external port, carry out setting of the operating
frequency and oscillation control in the ASIC. Also, it starts communication with ASIC, and confirms the system is operative.
When the through image is operating, set the PAON signal to High and then turn on the CCD. When the through image is
playing, set the PAON signal to Low and then turn off the CCD. When LCD panel turns on, set LCDON signal at pin (34) to
High, and then turn on the power. Set BLON signal at pin (35) to High, and turn on the backlight power.
When the power switch is off, the lens will be stowed, and PON, PAON, LCDON and BLON signals to Low and the power
supply to the whole system is halted. The 8-bit microprocessor halts oscillation of the main clock, and set operation mode of
clock ocillation.

Power supply voltage

Power OFF

Playback mode

Shooting mode (LCD)

Shooting mode (EVF)

Shooting

USB connection

ASIC,

memory

1.53 V, 3.25 V

OFF

ON

ON

OFF

ON

ON

Table 4-3. Power supply control

CCD

4.7 V, 15.5 V

-8 V

OFF

OFF

OFF

OFF

ON

OFF

8bit

CPU

3.2 V

32KHz

4MHz

4MHz

4MHz

4MHz

4MHz

LCD

MONITOR

15 V, 8.5 V

5 V

OFF

ON

ON

OFF

ON

OFF

H-10

Ver. 1