OLYMPUS C-310 Zoom DESCRIPTION OF MECHANISM
H. DESCRIPTION OF MECHANISM
X-100/D-540ZOOM/C-310ZOOM
H. DESCRIPTION OF MECHANISM
[1] CP1 CIRCUIT DESCRIPTION ................................................................................ H-2
[2] PWA POWER CIRCUIT DESCRIPTION ................................................................. H-6
[3] ST1 STROBE CIRCUIT DESCRIPTION................................................................. H-7
[4] SYA CIRCUIT DESCRIPTION................................................................................. H-8
H-1 Ver.1
H. DESCRIPTION OF MECHANISM X-100/D-540 ZOOM/C-310 ZOOM
2
5
2
[1] CP1 CIRCUIT DESCRIPTION
1. IC Configuration
IC903 (RJ23P3AA3DT) CCD imager
IC901 (LR36688U) V driver
IC902 (AD9847AKCPZ) CDS, AGC, A/D converter
2. IC903 (CCD)
[Structure]
Interline type CCD image sensor
Optical size 1/2.7 type format
Effective pixels 2080 (H) X 1544 (V)
Pixels in total 2096 (H) X 1560 (V)
Optical black
Horizontal (H) direction: Front 2 pixels, Rear 54 pixels
Vertical (V) direction: Front 5 pixels, Rear 2 pixels
Dummy bit number Horizontal : 24 Vertical :2
Pin 11
V
Pin 1
H
54
Fig. 1-1.Optical Black Location (Top View)
GND
19
OOFD
7
20
OS
Vertical shift register
1
Output part
Horizontal shift register
5
φRS
8
9
: Photo diode
φH2
φH1
OD
10
11
12
13
14
15
16
17
18
3
4
φV5A
φV4
φV3B
φV3A
φV2
φV1B
φV1A
φV6
φV5B
OFD
PW
Pin No.
1
2, 19
3
4
5
6
7
8
9
10, 18
11
12, 13
14
Symbol
OD
GND
φrs
NC
φH1
φH2
φV5A, φV5B
φV4
φV3B, φV3A
φV2
Pin Description
Output transistor drain
GND
Overflow drainOFD
P wellPW
Reset gate clock
Overflow drain outputOOFD
Horizontal register transfer clock
Horizontal register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Fig. 1-2. CCD Block Diagram
Waveform
DC
GND
DC
DC
DC
Voltage
15.5 V
0 V
Approx. 7 V
(Different from every CCD)
-8 V
7.8 V, 12 V
8 V
0 V, 4.7 V
0 V, 4.7 V
-8.0 V, 0 V, 15.5 V
-8.0 V, 0 V
-8.0 V, 0 V
-8.0 V, 0 V
15, 16
17
20
φV1B, φV1A
φV6
Vertical register transfer clock
Vertical register transfer clock
Signal outputOS
DC
-8.0 V, 0 V
-8.0 V, 0 V
Approx. 7.0 V
Table 1-1. CCD Pin Description
H-2 Ver. 1
H. DESCRIPTION OF MECHANISMX-100/D-540 ZOOM/C-310 ZOOM
C
B
M
A
A
B
V
V
V
3. Part of IC902 (H Driver) and IC901 (V Driver)
An H driver (part of IC902) and V driver (IC901) are necessary in order to generate the clocks (vertical transfer clock,
horizontal transfer clock and electronic shutter clock) which
driver the CCD.
IC902 has the generation of horizontal transfer clock and
the function of H driver, and is an inverter IC which drives
the horizontal CCDs (H1 and H2). In addition the XV1-XV6
signals which are output from IC101 are the vertical transfer clocks, and the XSG1 and XSG signal which is output
from IC101 is superimposed onto XV1, XV3 and XV5 at
IC901 in order to generate a ternary pulse. In addition, the
XSUB signal which is output from IC101 is used as the
sweep pulse for the electronic shutter, and the RG signal
which is output from IC101 is the reset gate clock.
GND
GND
V1~V3
VL
VH
GND
V5A, V7
VL
VH
GND
V8A~V9
VL
VH
GND
V8B~V9
VL
VH
POFD
VL
1X~V3X
5X, V7X
VH5AX,
VH7AX
8X~V9X
VH8AX~
VH9AX
VH8BX~
VH9BX
OFDX
VH
VL VDD
MIX
MIX
MIX
4. IC906 (H Driver, CDS, AGC and A/D converter)
IC906 contains the functions of H driver, CDS, AGC and A/
D converter. As horizontal clock driver for CCD image sensor, H¯1 (A and B) and H¯2 (A and B) are generated inside, and output to CCD.
The video signal which is output from the CCD is input to
pins (29) of IC902. There are sampling hold blocks inside
IC905 generated from the SHP and SHD pulses, and it is
here that CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier (VGA: Variable Gain Amplifier).
It is A/D converted internally into a 10-bit signal, and is then
input to ASIC (IC101). The gain of the VGA amplifier is controlled by pin (36)-(38) serial signal which is output from
ASIC (IC101).
VRB
VRT
VREF
CDIN
RG
H1-H4
2~36 dB
VGA
PxGA
CDS
HORIZONTAL
4
DRIVERS
CLAMP
INTERNAL
CLOCKS
PRECISION
TIMING
CORE
SYNC
GENERATOR
VD
HD
Fig. 1-4. IC902 Block Diagram
ADC
CLAMP
INTERNAL
REGISTERS
SL
SCK
SDATA
12
DOUT
CLPO
CLPD
PBLK
CLI
Fig. 1-3. IC901 Block Diagram
H-3 Ver. 1
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