The MSM6688/6688L is a “solid-state recorder” IC developed using the ADPCM method. By
externally connecting a microphone, a speaker, a speaker drive amplifier, and a dedicated register
to store ADPCM data, it can record and play back voice data in a manner similar to a tape recorder.
The MSM6688 supports 5 V operation and has a stand-alone mode and a microcontroller interface
mode.
The MSM6688L supports 3 V operation and controls recording/playback in microcontroller interface
mode.
In the stand-alone mode, recording/playback conditions can be selected by pins and the MSM6688/
6688L can be controlled by a simple drive timing. In the microcontroller interface mode, recording/
playback can be controlled by commands from the microcontroller. In the microcontroller interface
mode, the MSM6688/6688L is much more flexible than in the stand-alone mode.
In addition, the MSM6688/6688L can form easily a recording and playback circuit with fixed
messages by connecting serial registers and serial voice ROMs as external memories.
Note:This data sheet explains a stand-alone mode and a microcontroller interface mode, separately.
Differences Between MSM6688 and MSM6688L
ParameterMSM6688MSM6688L
Operating voltage3.5 to 5.5 V2.7 to 3.6 V
Control modeStandalone mode,
Microcontroller interface mode
Full scale of A/D and D/A
converters
Voice detection level for voice
triggered starting
External-only register32M bits (max.)
±
0 to V
DD
V
DD
64
4M bits (MSM6684B)
8M bits (MSM6685)
, ±
V
DD
, ±
32
V
DD
16
Microcontroller interface
mode only
1
VDD to
4
V
DD
±
128
4M bits (max.)
4M bits (MSM66V84B)
, ±
3
V
DD
4
V
DD
64
, ±
V
DD
32
1/159
¡ SemiconductorMSM6688/6688L
CONTENTS
(1) STAND-ALONE MODE
(for MSM6688 (5 V Version))
FEATURES ........................................................ 3
• External memories
Serial registers, 32M bits maximum (for variable messages)
8M bit serial register (MSM6685) can be driven directly
Serial voice ROMs, 4M bits maximum (for fixed messages)
1M bit serial voice ROM (MSM6595A) can be driven directly
2M bit serial voice ROM (MSM6596A) can be driven directly
3M bit serial voice ROM (MSM6597A) can be driven directly
• Sampling frequency
4.0 kHz, 5.3 kHz, 6.4 kHz or 8.0 kHz (master clock frequency = 4.096 MHz)
8.0 kHz, 10.6 kHz, 12.8 kHz, or 16.0 kHz (master clock frequency = 8.192 MHz)
• Number of phrases
63 phrases for variable messages
63 phrases for fixed messages
• Maximum recording time (when external 32M bit RAM is connected)
34 minutes (for 16 kbps ADPCM)
23 minutes (for 24 kbps ADPCM)
17 minutes (for 32 kbps ADPCM)
Digital power supply pin. Insert a bypass capacitor of 0.1µF or more
DV
DV
DD
DD'
—
between this pin and the DGND pin.
—Digital power supply pin
Analog power supply pin. Insert a bypass capacitor of 0.1µF or more
AV
DD
—
between this pin and the AGND pin.
DGND—Digital ground pin
AGND—Analog ground pin
SG
SGC
MIN
LIN
MOUT
LOUT
O
O
Output pin for analog circuit reference voltage (signal ground)
Inverting input pin of the built-in OP amplifier. Non-inverting input
I
pin is internally connected to SG (signal ground).
MOUT and LOUT are output pins of the built-in OP amplifier for MIN
and LIN, respectively.
This pin is connected to the LOUT pin in the recording mode and to
AMONO
the DA converter output in the playback mode. Used to connect the
built-in LPF input (FIN pin).
FINIInput pin of the built-in LPF.
Output pin of the built-in LPF. Used to connect the AD converter
FOUTO
input (ADIN pin).
ADINIInput pin of the built-in 12-bit AD converter.
Output pin of the built-in LPF. This pin outputs playback waveforms
AOUTO
and used to connect an external speaker drive amplifier.
(Serial Address Data). SADX is used to connect the SAD pin of each
SADX
SADY
O
external serial register and the SADX pin of each external serial voice
ROM. SADY is used to connect the SADY pin of each external serial
voice ROM. Outputs of starting address of read/write.
(Serial Address Strobe). Used to connect the SAS pin of external
SASO
serial register and the SASX and SASY pins of
external serial voice ROM. Clock pin to write the serial address.
(Transfer Address Strobe). Used to connect the TAS pin of each
external serial register and serial voice ROM.
TASO
This pin outputs address strobe outputs to set the serial address
data from the SADX and SADY pins into the internal address counter
of each serial register and serial voice ROM.
50
46
RWCKO
WEO
(Read/Write Clock). Used to connect the RWCK pin of each external
serial register and the RDCK pin of each external
serial voice ROM. This pin outputs a clock to read data from or write
it into each external serial register.
(Write Enable) Used to connect the WE pin of each external
serial register. This pin outputs WE signal to
select either read or write mode.
6/159
¡ SemiconductorMSM6688/6688L
Pin
45
40
41
42
43
31
32
10
53
35
SymbolTypeDescription
(Data I/O). Used to connect the DIN and DOUT pins of serial register.
DI/O44
DROM
CS1
CS2
CS3
CS4
RSEL1
RSEL2
MCUMI
RESETI
PDWNI
I/O
O
This pin outputs the data to be written into the serial register or
inputs the data read from the serial registers.
(Data ROM). Used to connect the DOUT pin of each external serial
I
voic ROM.
(Chip Select). Used to connect the CS pin of serial register and the
CS (CS1, CS2, CS3) pins of serial voice ROM.
(Register Select). These are used to select the number of external
serial registers.
I
RSEL2LLHH
RSEL1LHLH
Number of serial registers1234
This pin is used to select either the stand-alone mode or the
microcontroller interface mode.
Low level: Stand-alone mode
High level: Microcontroller interface mode.
A high input level to this pin causes the MSM6688 to be initialized
and to go into the power down state.
(Power Down). When a low level is input to this pin, the MSM6688
goes to the power down state. Unlike the RESET pin, this pin does
not force to reset the MSM6688. When an Low level is applied to
this PDWN pin during recording operation, the MSM6688 is halted,
and will be maintained in the power down state while PDWN is low.
After this pin is restored to a high level, postprocessing for
recording will be performed.
47
48
34
33
XTI
XTO
TEST
TEST
Used to connect an oscillator. When an external clock is used,
input the clock through this pin. At the power down state, this pin
must be set to the ground level.
Used to connect an oscillator, when an external clock is used, this
pin must be left open.
I
Used to test the MSM6688. Input a low level to the TEST pin and
a high level to the TEST pin.
7/159
¡ SemiconductorMSM6688/6688L
Pin
15
56
55
54
8
7
TypeSymbolDescription
ROMI
REC/PLAYI
STI
SPI
PAUSEI
DELI
When low, selects the record/playback operation. When high, selects the ROM
playback operation.
Used to select the recording mode or the playback mode. This pin is invalid
during the ROM playback operation. When low, selects the playback mode.
When high, selects the recording mode.
When a low-level pulse is applied to this pin, the record/playback or ROM
playback is started.
When a low-level pulse is applied to this pin, the record/playback or ROM
playback is stopped.
When a low-level pulse is applied to this pin, the record/playback or ROM
operation is stopped temporarily.
When a low level pulse is applied to this pin, all phase deletion or specified
phrase deletion can be performed according to the setting of pins CA0
through CA5,
ch00: All phase deletion
ch01 to ch3F: Specified phrase deletion
After powering up, be sure to input RESET signal and then to delete all phrases.
After completing this procedure, start the record/playback operation.
1-6
13
CA0-CA5I
4B/3BI
Input pins used to specify desired phases.
A total of 63 phrases can be specified independently for the record/playback
operation and the ROM playback operation.
CA5 CA4 CA3 CA2 CA1 CA0Phrase No.Remarks
LLLLLLch00All phrase deletion
LLLLLHch01
LLLLHL
.
.
.
.
.
.
HHHHH Lch3E
HHHHHHch3F
Input pin used to select one of two types of ADPCM bit length.
When low, selects the 3-bit ADPCM.
When high, selects the 4-bit ADPCM.
.
.
.
.
.
.
.
.
.
.
.
.
ch02
.
.
.
A total of 63 phrases
can be used both for
record/playback and
ROM playback
operation.
8/159
¡ SemiconductorMSM6688/6688L
Pin
11
12
9
SymbolTypeDescription
Used to select one of the following four types of sampling
frequency. The relationship between the master clock frequency
(fosc) and the sampling frequency (fsamp) is shown below.
Values in parentheses denote the sampling frequencies for
SAM1
SAM2
I
fosc = 4.096 MHz.
SAM2LLHH
SAM1LHLH
fsamp
fosc
1024
(4.0kHz)
fosc
768
(5.3kHz)
This input pin is used to select the condition for transition to the
power-down state.
Low level: The MSM6688 automatically goes to the power-down
state, excepting the time the record/playback
operation is being performed.
High level: The MSM6688 automatically goes to the standby
PDMDI
state, instead of the power-down state, excepting the
time the record/playback operation is being
performed. In this case, the MSM6688 can be placed
in the power-down state by setting the RESET pin to
a high level. If it is desired to use the built-in LPF for
an external circuit, this standby mode must be
selected by applying a high level to the PDMD pin.
fosc
640
(6.4kHz)
fosc
512
(8.0kHz)
14
51
52
VDSI
MONO
NARO
Used to select the voice triggered starting that starts recording
when the voice input exceeds the preset amplitude. A high input
level on this pin enables the voice triggered starting circuit.
Outputs a high level while the record/playback operation is being
performed.
Output pin to indicate the enable or disable state of the operation
for specifying a phrase. When continuous ROM playback is
performed, the next phrase can be specified after verifying that the
NAR pin becomes high.
9/159
¡ SemiconductorMSM6688/6688L
ABSOLUTE MAXIMUM RATINGS (for MSM6688 (5 V Version))
ParameterSymbolConditionRatingUnit
Power supply voltageV
Input VoltageV
Storage temperatureT
DD
IN
STG
Ta=25°C–0.3 to +7.0V
Ta=25°C–0.3 to VDD+0.3V
—–55 to +150°C
RECOMMENDED OPERATING CONDITIONS (for MSM6688 (5 V Version))
ParameterSymbolConditionRangeUnit
Power supply voltageV
Operating temperatureT
Master clock frequencyf
DD
op
osc
Note:1. Recording and playback should be performed at a power supply voltage of 4.5 to 5.5V.
For other operations such as backup for a serial register, the IC operates at 3.5 to 5.5V.
DGND=AGND=0V3.5 to 5.5 (Note 1)V
—–40 to +85°C
—4.0 to 8.192MHz
10/159
¡ SemiconductorMSM6688/6688L
ELECTRICAL CHARACTERISTICS (for MSM6688 (5 V Version))
DC Characteristics
ParameterSymbolConditionTyp.Unit
High input voltageV
Low input voltageV
High output voltageV
Low output voltageV
High input current (Note 1)
High input current (Note 2)
Low input current (Note 3)
Low input current (Note 2)
Low input current (Note 4)
Operating current
consumption
Standby current
consumption
I
I
I
I
I
I
I
DDS
IH
OH
OL
IH1
IH2
IL1
IL2
IL3
DD
=DV
DV
DD
=AVDD=4.5 to 5.5V (Note 5)
DD'
DGND=AGND=0V Ta=–40 to +85°C
Min.
—
IL
I
= –40mA
OH
I
= 2mA
OL
V
= V
IH
V
= V
IH
V
= GND–10mA
IL
V
= GND–20mA
IL
V
= GND–400mA
IL
——V
DD
DD
0.8¥V
DD
VDD–0.3
—V
—mA
—mA
fosc = 8 MHz, no load—mA
During power down, no load
Ta=–40 to +70°C
During power down, no load
Ta=–40 to +85°C
—mA
—mA
—
—
—
—
—
—
—
—
—
15
—10
—
Max.
—
0.2¥V
—
0.45
10
20
—
—
–20
30
50
V
DD
V
Note:1. Applies to all input pins excluding the XT pin.
2. Applies to the XT pin.
3. Applies to the all input pins without pull-up resistors, excluding the XT pin.
4. Applies to the input pins (ST, SP, PAUSE, DEL) with pull-up resistors, excluding the XT
pin.
11/159
¡ SemiconductorMSM6688/6688L
Analog Characteristics
ParameterSymbolConditionMin.Typ.Max.Unit
DA output relative error|V
FIN admissible input
voltage range
FIN input impedanceR
ADIN admissible input
voltage range
ADIN input impedanceR
Op-amp open loop gainG
Op-amp input impedanceR
Op-amp load resistance
AOUT load resistanceR
FOUT load resistanceR
DV
=DV
DD
=AVDD=4.5 to 5.5V
DD'
DGND=AGND=0V Ta=–40 to +85°C
|no load——10mV
DAE
V
V
R
FIN
FIN
ADIN
ADIN
OP
INA
OUTA
AOUT
FOUT
—1—V
DD
—1——MW
—0—V
DD
—1——MW
fIN=0-4kHz40——dB
—1——MW
—200——kW
—50——kW
—50——kW
-1V
V
12/159
¡ SemiconductorMSM6688/6688L
AC Characteristics
Parameter
RESET pulse width
RESET execution time
PDWN low level time
PDWN high level time
Oscillating time after input of PDWN
BUSY time after release of PDWN
ST pulse width
SP pulse width
PAUSE pulse width
DEL pulse width
Time required to delete all phrases
Time required to delete a specified phrase
(Note 1)*
(Note 1)*
(Note 1)*
(Note 2)**
**
**
(Note 2)*
DVDD=DV
=AVDD=4.5 to 5.5V
DD'
DGND=AGND=0V Ta=–40 to +85°C
fosc=4.096MHz f
Symbol Min.Typ.Max.Unit
t
RST
t
REX
t
*
PDL
t
PDH
t
*
PX
t
BPD
t
ST
t
SP
t
PSE
t
DEL
t
*
WBLA
t
*
WBL1
1
—
500
500
125
0.25
40
40
40
40
550
70
—
1
—
—
—
—
—
—
—
—
—
—
SAMP
—
—
—
—
500
—
—
—
—
—
—
—
=8.0kHz
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
Time from input of DEL pulse to CSI fall
(Note 2)*
Hold time of CA0~CA5, REC/PLAY after MON rise
Address control time at the start of record/playback
Time from input of ST pulse to NAR fall
(Note 2)*
Unvoiced time between phrases during repeated playback
Record
Time from input of ST pulse
to MON rise
Playback
ROM playback
Record
POMD=H
Time from input of SP pulse
to MON fall
Playback
ROM playback
Time from input of ST pulse to standby for
t
DCS
t
CAH
t
*
AD1
t
STN
*
t
MID
t
*
TMH1
*
t
TMH2
*
t
TMH3
*
t
PMH1
*
t
PMH2
*
t
PMH3
*
t
STVH
—
1
—
—
0.75
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
270
—
—
40
1
50
20
1
80
2
2
50
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
voice
Time from input of SP pulse during standby
*
t
SPVH
—
—
80
ms
for voice to release of standby for voice
Items with * are proportional to the period of master clock frequency fosc.
Items with **are proportional to the period of the master clock frequency fosc, and are also
proportional to the sampling frequency f
Note:1. The oscillation start stabilization time is added to t
during record/playback.
SAMP
and t
REX
BPD
.
The oscillation start stabilization time is several tens of milliseconds for crystals and
several hundreds of microseconds for ceramic oscillators.
Note:2. The oscillation start stabilization time is added if PDMD pin = "L".
The oscillation start stabilization time is several tens of milliseconds for crystals and
several hundreds of microseconds for ceramic oscillators.
13/159
¡ SemiconductorMSM6688/6688L
PDMD=L
Parameter
Record
Time from input of ST pulse
to MON rise
Playback
ROM playback
Record
Time from input of SP pulse
to MON fall
Playback
ROM playback
Time from input of ST pulse to standby for
voice
Time from input of SP pulse during standby
for voice to release of standby for voice
Standby transition time at start of playback
Standby transition time at end of playback
*
*
*
*
*
*
*
*
*
*
Symbol
t
TML1
t
TML2
t
TML3
t
PML1
t
PML2
t
PML3
t
STVL
t
SPVL
t
AOR
t
AOF
DVDD=DV
=AVDD=4.5 to 5.5V
DD'
DGND=AGND=0V Ta=–40 to +85°C
fosc=4.096MHz f
Min.
—
—
—
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
64
256
SAMP
Max.
=8.0kHz
120
150
150
80
260
260
120
80
—
—
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
Time from input of PAUSE pulse to pause
Time from input of ST pulse during pause to restart of
record/playback
**
**
t
t
PP
PST
—
—
—
—
1
1
ms
ms
Items with * are proportional to the period of master clock frequency fosc.
Items with ** are proportional to the period of the master clock frequency fosc, and are also
proportional to the sampling frequency f
during record/playback.
SAMP
14/159
¡ SemiconductorMSM6688/6688L
TIMING DIAGRAMS
RESET FUNCTION
V
DD
RESET (I)
t
RST
t
REX
UndefinedPower down
Power Down by PDWN Pin
PDWN (I)
XT (I)
XT (O)
Oscillation in progress
tPX Note 1
t
Reset operation in progress
PDL
Standby for record/playback
t
PDH
Oscillation in progress
t
BPD
Power downPostprocessingStandby
Note:1. When an external clock is used, continue to apply the clock input to the XT terminal
during tPX after the PDWN pin is set to a low level.
15/159
¡ SemiconductorMSM6688/6688L
Timing for Deletion of All Phrases
CA0-CA5 (I)
t
DEL
DEL (I)
t
WBLA
t
DCS
CSI (O)
Standby
Deletion of all phrases
Timing for Deletion of a Specified Phrase
CA0-CA5 (I)
t
DEL
DEL (I)
t
WBL1
t
DCS
CSI (O)
Standby
Deletion of a specified phrase
Standby
Standby
16/159
17/159
¡ SemiconductorMSM6688/6688L
Recording Timing (PDMD Pin = High)
ST
MON
Standby
Power down
Oscillation in progress
t
TMH1
XT
t
STN
t
ST
t
CAH
Power down
Address controlRecording in progress
Standby
t
SP
Phase designation
Bit rate designation
t
PMH1
t
AD1
RESET
ROM
SAM1, SAM2
4B/3B
CA0-CA5
REC/PLAY
SP
XT
NAR
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(O)
18/159
¡ SemiconductorMSM6688/6688L
Timing for Voice Triggered Recording (PDMD Pin = High)
ST
MON
Standby
Power down
Oscillation in progress
t
STVH
XT
t
STN
t
ST
t
CAH
Power down
Standby for voiceRecording
Standby
t
SP
Phrase designation
Bit rate designation
t
SPVH
t
AD1
RESET
SAM1, SAM2
4B/3B
CA0-CA5
REC/PLAY
SP
XT
NAR
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(O)
ROM(I)
t
SP
t
PMH1
Address control
VDS
Voice detected
When STOP pulse is input during standby for voice,
the MSM6688 goes to the recording standby state.
19/159
¡ SemiconductorMSM6688/6688L
Playback Timing (PDMD Pin = High)
ST
MON
Standby
Power down
Oscillation in progress
t
TMH2
XT
t
STN
t
ST
t
CAH
Power down
Playback
Standby
Phrase designation
Bit rate designation
t
AD1
RESET
SAM1, SAM2
4B/3B
CA0-CA5
REC/PLAY
SP
XT
AOUT
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(O)
RO(I)
t
SP
t
PMH2
Address control
NAR(O)
1/2 VDD level
GND level
1/2 VDD level
GND level
20/159
¡ SemiconductorMSM6688/6688L
ROM Playback Timing (PDMD Pin = High)
ST
MON
Standby
Power down
Oscillation in progress
t
TMH3
XT
t
STN
t
ST
t
CAH
Power down
Playback
Standby
Phrase designation
t
AD1
RESET
CA0-CA5
SP
XT
AOUT
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(O)
ROM(I)
t
SP
t
PMH3
Address control
NAR(O)
1/2 VDD level
GND level
1/2 VDD level
GND level
21/159
¡ SemiconductorMSM6688/6688L
Continuous ROM Playback Timing (PDMD Pin = High)
ST
MON
Standby
Power down
Oscillation in progress
t
TMH3
XT
t
STN
Power down
Unvoiced
2nd phrase playback
1st phrase designation
t
AD1
RESET
CA0-CA5
SP
XT
AOUT
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(O)
ROM(I)
t
SP
t
PMH3
Address control
NAR(O)
1/2 VDD level
GND level
1/2 VDD level
GND level
1st phrase playback
2nd phrase designation
t
MID
Standby
22/159
¡ SemiconductorMSM6688/6688L
Recording Timing (PDMD Pin = Low)
ST
MON
Analog stable time
Power down
Oscillation in progress
t
TML1
XT
t
STN
t
ST
t
CAH
Power down
Address controlRecording in progress
t
SP
Phrase specifying operation
Bit rate specifying operation
t
PML1
t
AD1
RESET
ROM
SAM1, SAM2
4B/3B
CA0-CA5
REC/PLAY
SP
XT
NAR
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(O)
23/159
¡ SemiconductorMSM6688/6688L
Timing for Voice Triggered Recording (PDMD Pin = Low)
ST
MON
Analog stable time
Power down
Oscillation in progress
t
STVL
XT
t
STN
t
ST
t
CAH
Power down
Standby for voiceRecording
t
SP
Phrase designation
Bit rate designation
t
SPVL
t
AD1
RESET
SAM1, SAM2
4B/3B
CA0-CA5
REC/PLAY
SP
XT
NAR
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(O)
ROM(I)
t
SP
t
PML1
Address control
VDS
Voice detected
When STOP pulse is input during standby for voice,
the MSM6688 goes to the recording standby state.
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¡ SemiconductorMSM6688/6688L
Playback Timing (PDMD Pin = Low)
ST
MON
Analog stable time
Power down
Oscillation in progress
t
TML2
XT
t
STN
t
ST
t
CAH
Power down
Playback
Phrase designation
Bit rate designation
t
AD1
RESET
SAM1, SAM2
4B/3B
CA0-CA5
REC/PLAY
SP
XT
AOUT
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(I)
(I)
(I)
(O)
ROM(I)
t
SP
t
PML2
Address control
NAR(O)
GND level
1/2 V
DD
level
GND level
Standby transition
t
AOR
t
AOF
Standby transition
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¡ SemiconductorMSM6688/6688L
ROM Playback Timing (PDMD Pin = Low)
ST
MON
Analog stable time
Power down
Oscillation in progress
t
TML3
XT
t
STN
t
ST
t
CAH
Power down
Playback
Phrase designation
t
AD1
RESET
CA0-CA5
SP
XT
AOUT
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(O)
ROM(I)
t
SP
t
PML3
Address control
NAR(O)
GND level
1/2 V
DD
level
GND level
Standby transition
t
AOR
Standby transition
t
AOF
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¡ SemiconductorMSM6688/6688L
Continuous ROM Playback Timing (PDMD Pin = Low)
ST
MON
Power down
Oscillation in progress
t
TML3
XT
t
STN
Power down
Unvoiced
2nd phrase playback
1st phrase designation
t
AD1
RESET
CA0-CA5
SP
XT
AOUT
(I)
(O)
(O)
(I)
(I)
(I)
(I)
(O)
ROM(I)
t
SP
t
PML3
Address control
NAR(O)
GND level
1/2 V
DD
level
GND level
1st phrase playback
2nd phrase designation
t
MID
Standby transitionAnalog stable time
t
AOR
t
AOF
Standby transition
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¡ SemiconductorMSM6688/6688L
Record/Playback Pause Timing
ST
MON
Standby
Pause
SP
(I)
(O)
(I)
t
ST
Note 1
t
PST
Record/PlaybackPauseRecord/PlaybackStandby
t
ST
t
PSE
t
SP
t
PSE
t
PP
t
PP
PAUSE
(I)
Start pulseRestart pulse
Note 1: This time interval varies depending on the state of PDMD pin and
the record/playback mode and is one of t
PMH1
, t
PMH2
, t
PMH3
, t
PML1
,
t
PML2
and t
PML3
.
¡ SemiconductorMSM6688/6688L
FUNCTIONAL DESCRIPTION
Recording Time and Memory Capacity
The recording time depends on the memory capacity of the external serial registers, sampling
frequency, and ADPCM bit length, and is given by
Recording time =(seconds)
1.024 ¥ memory capacity (K bits)
sampling frequency (kHz) ¥ bit length (bits)
For example, if the sampling frequency is kHz (= 5.333 kHz), ADPCM bit length is 3 bits, and
4096
768
four 8M bit serial registers are used, the recording time can be obtained as follows.
Recording time == 2093 seconds
1.024 ¥ (8192 ¥ 4 – 64)
5.333 ¥ 3
= 34 minutes 53 seconds
In the above equation, the memory capacity is obtained by subtracting the memory capacity (64
Kbits) for the channel index area from the total memory capacity.
Connection of an Oscillator
Connect a ceramic oscillator or a crystal oscillator to XT and XT pins as shown below. The optimal
load capacities when connecting ceramic oscillators from MURATA MFG. and KYOCERA
CORPORATION are shown below for reference.
MSM6688
XTXT
MURATA
MFG.
KYOCERA
CORPORATION
CSA4.00MG
CST4.00MGW
CSA6.00MG
CST6.00MGW
CSA8.00MTZ
CST8.00MTW
KBR-4.0MSA
KBR-4.0MKS
PBRC4.00A
PBRC4.00B
KBR-6.0MSA
KBR-6.0MKS
PBRC6.00A
PBRC6.00B
KBR-8.0M
PBRC8.00A
PBRC8.00B
C
1
Ceramic oscillatorOptimal load capacity
TypeFreq(MHz)C
(with capacitor)
(with capacitor)
(with capacitor)
(with capacitor)
(with capacitor)
2
C
1
(pF)C2(pF)
4.0
6.0
8.0
4.0
6.0
8.0
30
3333
30
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¡ SemiconductorMSM6688/6688L
Power Supply Wiring
As shown in the following diagram, supply the power to this MSM6688 from the same power source,
but separate the power supply wiring to the analog portion from that to the logic position.
+5V
DV
DV
DD
DD'
DGNDAGND
MSM6688
AV
DD
The following connections are not permitted.
Analog power supply
Digital power supply
DV
DV
DD
DD'AVDD
+5V
DV
DV
DD'
DD
AV
DD
Analog Input Amplifier Circuit
This MSM6688 has two built-in operational amplifiers for amplifying the microphone output. Each
OP amplifier is provided with the inverting input pin and output pin. The analog circuit reference
voltage SG (signal ground) is connected internally to the non-inverting input of each OP amplifier.
For amplification, form an inverting amplifier circuit and adjust the amplification ratio by using
external resistors as shown below.
V
IN
+
–
R1R3R4
R2
V
MO
V
LO
V
DD
V
LO
VDD–1
SG
VLO=
MIN
–
+
R4R2 • R4
R3R1 • R3
MOUTLINLOUT
–
OP amp 1OP amp 2
=V
V
MO
+
(V)
IN
1/2V
1
GND
DD
During the time the recording operation is performed, the output VLO of OP amp 2 is connected to
the input FIN of the built-in LPF. The FIN allowable input voltage (V
) ranges from 1V to (V
FIN
DD
– 1)V. Therefore, the amplification ratio must be adjusted so that the VLO amplitude can be within
the FIN allowable input voltage range.
For example, if VDD = 5V, V
becomes 3 V
LO
max. If VLO exceeds the FIN allowable input voltage
p-p
range, the output of the LPF will be a clipped waveform.
The load resistance R
of the OP amp is 200 kW minimum, so that the feedback resistors R2 and
OUTA
R4 of the inverting amplifier circuit must be 200 kW or more.
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¡ SemiconductorMSM6688/6688L
Connection of LPF Circuit Peripherals
The AMON pin is connected internally to the output of the amplifier circuit (LOUT pin) in the
recording mode and to the output of the built-in DA converter in the playback mode. Therefore,
connect the AMON pin directly to the input (FIN pin) of the built-in LPF.
Both the FOUT and AOUT pins are the output pins of the built-in LPF. Connect the FOUT pin to the
input (ADIN pin) of the built-in AD converter and connect the AOUT pin to an external speaker
through an external speaker drive amplifier.
In the MSM6688, the connection of each of the FOUT and AOUT pins is changed to one of the output
of the LPF, GND (ground) level, and SG (signal ground) level, depending on the operation status as
shown below.
When PDMD pin = high level:
During operation
Analog pin
At power down
(RESET pin = H)
Recording modePlayback mode
(RESET pin = L)
FOUT pin
AOUT pin
When PDMD pin = L:
Analog pinAt power down
FOUT pin
AOUT pin
GND level
GND level
GND level
GND level
LPF output
(recording waveform)
SG level
During operation
Recording modePlayback mode
LPF output
(recording waveform)
GND level
LPF output
LPF output
(playback waveform)
LPF output
LPF output
(playback waveform)
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