OKI MSM66507-xxxJS-B, MSM66P507-xxxJS-B Datasheet

E2E1028-27-Y5

¡ Semiconductor MSM66507/66P507

¡ Semiconductor

This version: Jan. 1998

Previous version: Nov. 1996

MSM66507/66P507

OLMS-66K Series 16-Bit Microcontroller

GENERAL DESCRIPTION

The MSM66507/66P507 is a high-performance 16-bit microcontroller that employs OKI
original nX­The MSM66507/66P507 includes a 16-bit CPU, ROM, RAM, a 10-bit A/D converter, serial ports,
flexible timers, a pulse-width modulator (PWM), and I/O ports.

FEATURES

• Program memory space : 64K bytes
Internal ROM : 48K bytes

• Data memory space : 64K bytes
Internal RAM : 1.5K bytes

• High-speed execution

Minimum instruction execution time : 167ns (@24MHz)

• Powerful instruction set : Instruction set superior in orthogonal matrix

• Abundant addressing modes : Register addressing

• I/O port

Analog input port : 1 port ¥ 10 bits
Input-output port : 7 ports ¥ 8 bits, 1 port ¥ 3 bits
(Each bit can be assigned to input or output.)

• Flexible timers

Free run counters : 19-bit ¥ 1, 16-bit ¥ 1
19-bit CAP with a divider : 4
16-bit double buffer RTO : 4
16-bit RTO/PWM : 2
16-bit CAP/RTO : 2

• 8-bit general timer : 1
8-bit event counter : 1

• 16-bit PWM : 4
Input clock divider : 2

• Serial ports

UART mode with BRG : 1
Synchronous/UART switchable mode
with BRG : 1

• 10-bit A/D converter : 10 channels

8/500 CPU core.

8/16-bit data transfer instructions
8/16-bit arithmetic instructions
Multiplication and division operation instructions
Bit manipulation instructions
Bit logic operation instructions
ROM table reference instructions

Page addressing
Pointing register indirect addressing
Stack addressing
Immediate value addressing

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¡ Semiconductor MSM66507/66P507

• Transition detector : 6

• Watchdog timer : 1

• Interrupts

Nonmaskable : 1
Maskable : Internal 28/external 2
(4-level priority can be set)

• ROM window function

• Standby modes

HALT mode
STOP mode

• Package

84-pin plastic QFJ (PLCC) (QFJ84-P-S115-1.27-B) (Product name: MSM66507-¥¥¥JS-B)

(Product name: MSM66P507-¥¥¥JS-B)
¥¥¥ indicates the code number.

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¡ Semiconductor MSM66507/66P507

BLOCK DIAGRAM

P2.0/RTO4

P2.5/RTO9
P2.6/FTM10
P3.0/FTM11A
P3.1/FTM11B

P3.3/FTM11D
P3.4/CAP0

P3.7/CAP3
P6.2/RXD1
P6.3/TXD1
P6.4/RXC1
P6.5/TXC1
P6.6/RXD0
P6.7/TXD0

P7.4/PWM0

P7.7/PWM3
AV

DD

V

REF

AGND
AI0

AI9
P4.0/ETMCK

P4.1/ECTCK
P4.2/TRNS0

P4.7/TRNS5
P6.0/INT0

P6.1/INT1
NMI

P7.3/CLKOUT

FLEXIBLE

TIMER

SERIAL

PORT

PWM

A/D

CONVERTER

EVENT
TIMER

TRANSITION
DETECTOR

INTERRUPT

PERIPHERAL

WDT

CONTROL
REGISTERS

CPU CORE

SSP
LRB

PSW
PC

MEMORY
CONTROL

POINTING R.

LOCAL R.

ALU CONTROL

ACC, etc.

INSTRUCTION

DECODER

SYSTEM CONTROL

RAM

1.5K BYTES

ROM

48K BYTES

EA

ALE

PSEN
RD/P7.1
WR/P7.0

WAIT/P7.2
AD0/P0.0

AD7/P0.7

A8/P1.0

A15/P1.7

PORT

CONTROL

OSC0

OSC1

RES

P0P1P2P3P4P5P6

P7

OE

ALU

BUS PORT CONTROL

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¡ Semiconductor MSM66507/66P507

PIN CONFIGURATION (TOP VIEW)

84-Pin Plastic QFJ (PLCC)

75

76

77

78

79

80

81

82

83

84

1

2

3

4

5

6

7

8

9

10

11

TRNS4/P4.6

TRNS5/P4.7

P5.0

P5.1

P5.2

NMI

RES

EA

V

DD

AV

DD

AI0

AI1

AI2

AI3

AI4

AI5

AI6

AI7

AI8

AI9

AGND

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P2.1/RTO5

P2.0/RTO4

OE

P1.7/A15

P1.6/A14

P1.5/A13

P1.4/A12

P1.3/A11

P1.2/A10

P1.1/A9

P1.0/A8

V

DD

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

P7.7/PWM3

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

P4.5/TRNS3
P4.4/TRNS2
P4.3/TRNS1
P4.2/TRNS0
P4.1/ECTCK
P4.0/ETMCK
P3.7/CAP3
P3.6/CAP2
P3.5/CAP1
P3.4/CAP0
GND
P3.3/FTM11D
P3.2/FTM11C
P3.1/FTM11B
P3.0/FTM11A
P2.7
P2.6/FTM10
P2.5/RTO9
P2.4/RTO8
P2.3/RTO7
P2.2/RTO6

V

REF

INT0/P6.0
INT1/P6.1

RXD1/P6.2

TXD1/P6.3

RXC1/P6.4

TXC1/P6.5

RXD0/P6.6

TXD0/P6.7

GND
OSC0
OSC1

ALE

PSEN

WR/P7.0

RD/P7.1

WAIT/P7.2

CLKOUT/P7.3

PWM0/P7.4
PWM1/P7.5
PWM2/P7.6

¡ Semiconductor MSM66507/66P507

PIN DESCRIPTION

Symbol Type Description

P0.0-P0.7/

AD0-AD7

P1.0-P1.7/

A8-A15

P2.0-P2.5/
RTO4-RTO9
P2.6/FTM10

P2.7

P3.0-P3.3/

FTM11A-FTM11D

P3.4-P3.7/
CAP0-CAP3

P4.0/ETMCK

P4.1/ECTCK

P4.2-P4.7/

TRNS0-TRNS5

P5.0-P5.2

I/O

I/O

I/O

I/O

I/O

I/O

P0: 8-bit Input-output port. Each bit can be assigned to input or output.
AD: When an external memory is used, these pins output the lower 8 bits of the
address. These pins also input or output the data.

P1: 8-bit Input-output port. Each bit can be assigned to input or output.
A: When an external memory is used, these pins output the upper 8 bits of the
address.

P2: 8-bit Input-output port. Each bit can be assigned to input or output.
RTO: Output pin for real time output
FTM10: Capture input pin or real time output pin

P3: 8-bit Input-output port. Each bit can be assigned to input or output.
FTM11A: Capture input pin or real time output pin
FTM11B-D: 4-port real time output pin
CAP : Capture input pin

P4: 8-bit Input-output port. Each bit can be assigned to input or output.
ETMCK: External clock input pin of 8-bit general timer
ECTCK: External clock input pin of 8-bit event counter
TRNS: Transition detector input pin

P5: 3-bit Input-output port. Each bit can be assigned to input or output.

P6.0/INT0

P6.1/INT1
P6.2/RXD1
P6.3/TXD1
P6.4/RXC1

P6.5/TXC1
P6.6/RXD0
P6.7/TXD0

P7.0/WR

P7.1/RD

P7.2/WAIT

P7.3/CLKOUT

P7.4-P7.7/

PWM0-PWM3

AI0-AI9 Analog signal input only pin for A/D converter

AV

DD

V

REF

AGND GND input pin for A/D converter

I/O

I/O

I

I

I

I

P6: 8-bit Input-output port. Each bit can be assigned to input or output.
INT0, 1: External interrupt request input pin
RXD1 : SCI1 Receiver data input pin
TXD1 : SCI1 Transmitter data output pin
RXC1 : SCI1 Receiver circuit clock pin
TXC1 : SCI1 Transmitter circuit clock pin
RXD0 : SCI0 Receiver data input pin
TXD0 : SCI0 Transmitter data output pin

P7: 8-bit Input-output port. Each bit can be assigned to input or output.

WR: Write strobe output pin for external data memory
RD: Road strobe output pin for external data memory

WAIT: CPU wait request input pin when accessing external data memory
CLKOUT: Output pin for supplying a clock to peripheral circuits
PWM: PWM output pin

Power supply input pin for A/D converter

Reference voltage input pin for A/D converter

OSC0 Basic clock oscillation pin

OSC1 Basic clock oscillation pin

I

O

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¡ Semiconductor MSM66507/66P507

PIN DESCRIPTION (Continued)

Symbol Type Description

ALE

O

Timing pulse output pin to latch the lower 8 bits of the address output from port
0 when the CPU accesses the external memory

PSEN Strobe pulse output pin to fetch to external program memory

OE

NMI Nonmaskable interrupt request input pin

RES

EA

V

DD

GND Ground pin

O

Normally, when P0, P1, and P7.4-P7.7 are in an output state and the OE pin is
"H" level, the ports go to a high impedance state. When OE pin is "L" level,

I

I

I

I

I

I

the ports output "H" or "L" level. However, when P0, P1, and P7.4-P7.7 are in
an input state, these ports are not under the influence of OE pin.

RESET input pin
Low-active reset input pin

Normally set to "H" level. If set to "L" level, the program memory goes to external
access mode and accesses external program memory.

Power supply pin

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¡ Semiconductor MSM66507/66P507

REGISTERS

Accumulator

Control Register (CR)

Program Status Word

Program Counter

Local Register Base

15 0

ACC

15 0

PSW

Bit 15 : Carry flag (CY)
Bit 14 : Zero flag (ZF)
Bit 13 : Half carry flag (HC)
Bit 12 : Data descriptor (DD)
Bit 11 : Sign flag (S)
Bit 10 : Master interrupt priority flag (MIP)
Bit 9 : Overflow flag (OV)
Bit 8 : Master interrupt enable flag (MIE)
Bit 7-3 : User flag
Bit 2-0 : System control base 2-0 (SCB2-0)

15 0

PC

LRB

System Stack Pointer

Pointing Register (PR)

Index Register 1
Index Register 2
Data pointer
User Stack Pointer

Local Register

SSP

15 0

X1
X2
DP

USP

7070
ER0
ER1

ER2
ER3

R1
R3
R5
R7

R0
R2
R4
R6

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¡ Semiconductor MSM66507/66P507

SFR

Address

[H]

0000
0001
0002
0003
0004

0005
0006
0007

0010
0011I
0012I

0014
0015I
0018I

001C
001DI

001EI
0020
0021
0022
0023
0024

0025I
0026
0027
0028
0029
002A
002B
002C
002DI
002E
002F

W

W

R

8/16-bit

Operation

8/16

8

Reset

FF
FF

Undefined

00
00
00
00

00

Halt

Name

System stack pointer

Local register base

Program status word

Accumlator
ROM window register

RAM ready control register
ROM ready control register ROMRDY FF
Stop code acceptor
Standby control register SBYCON C8
Peripheral control register PRPHF *

Watchdog timer WDT
TBC Clock dividing counter
TBC Clock dividing register TBCKDVR F0
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 0 mode register
Port 1 mode register
Port 2 mode register
Port 3 mode register
Port 4 mode register
Port 5 mode register
Port 6 mode register
Port 7 mode register

Symbol

SSP

LRBL

LRBH
PSWL
PSWH

ACCL

ACCH

ROMWIN
RAMRDY FF

STPACP "0"

TBCKDVC F0

P0 00
P1 00
P2 00
P3 00
P4 00

P5 F8
P6 00

P7 00
P0IO 00
P1IO 00
P2IO 00
P3IO 00
P4IO 00
P5IO F8
P6IO 00
P7IO 00

R/W

R/W

R/W

R/W 8/16

Note: A I mark in the address column shows that there is a bit that does not exist in its register.

* The initial values of PRPHF (SFR=18H) are as follows :

When RES pin is reset : VBFF (bit 6) is set to "1" and CKOUT1 and 0 are set to "0".
When reset by the WDT or BRK instruction or by operation code trap : VBFF (bit 6) keeps the
value just before reset and CKOUT 1 and 0 are set to "0". In any cases, the state of the OE pin
is read for OERD (bit 7).

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