E2E1027-27-Y4
¡ Semiconductor MSM66201/66P201/66207/66P207
¡ Semiconductor
This version: Jan. 1998
Previous version: Nov. 1996
MSM66201/66P201/66207/
66P207
OLMS-66K Series 16-Bit Microcontroller
GENERAL DESCRIPTION
The MSM66201/66207 is a high performance microcontroller that employs OKI original nX-8/
200 CPU core. This chip includes a 16-bit CPU, ROM, RAM, I/O ports, multifunction 16-bit
timers, 10-bit A/D converter, serial I/O port, and pulse width modulator (PWM). The
MSM66P201/66P207 is the OTP (One-Time Programmable) version of the MSM66201/66207.
FEATURES
• 64K address space for program memory : Internal ROM : MSM66201 16K bytes
MSM66207 32K bytes
• 64K address space for data memory : Internal RAM : MSM66201 512 bytes
MSM66207 1024 bytes
• High-speed execution
Minimum cycle for instruction : 400ns @ 10MHz
• Powerful instruction set : Instruction set superior in orthogonal matrix
8/16-bit data transfer instructions
8/16-bit arithmetic instructions
Multiplication and division operation instructions
Bit manipulation instructions
Bit logic instrucitons
ROM table reference instructions
• Abundant addressing modes : Register addressing
Page addressing
Pointing register indirect addressing
Stack addressing
Immediate value addressing
• I/O port
Input-output port : 5 ports ¥ 8 bits
(Each bit can be assigned to input or output)
Input port : 1 port ¥ 8 bits
• Built-in multifunctional 16-bit timer : 4
Following 4 modes can be set for each timer : Auto-reload timer mode
Clock output mode
Capture register mode
Real time output mode
• Serial port : 1 channel (Synchronous/UART switchable
mode with baud rate generators)
• 16-bit pulse width modulator : 2
• Watchdog timer
• Transition detector : 4
• 10-bit A/D converter : 8 channels
• Interrupts
Nonmaskable : 1
Maskable : Internal 16/external 2
• Stand-by function
STOP mode : Software clock stop mode
HALT mode : Software CPU stop mode
HOLD mode : Hardware CPU stop mode
1/30
¡ Semiconductor MSM66201/66P201/66207/66P207
• Package
64-pin plastic shrink DIP (SDIP64-P-750-1.78)
64-pin plastic QFP (QFP64-P-1414-0.80-BK)
68-pin plastic QFJ (PLCC) (QFJ68-P-S950-1.27)
64-pin ceramic piggyback (ADIP64-C-750-1.78)
* The piggyback type is used only for engineering samples.
: (MSM66201-¥¥¥SS) (MSM66P201-¥¥¥SS)
(MSM66207-¥¥¥SS) (MSM66P207-¥¥¥SS)
: (MSM66201-¥¥¥GSBK)(MSM66207¥¥¥GS-
BK)
: (MSM66201-¥¥¥JS) (MSM66P201-¥¥¥JS)
(MSM66207-¥¥¥JS) (MSM66P207-¥¥¥JS)
: (MSM66G207VS)
(¥¥¥ indicates the code number.)
2/30
¡ Semiconductor MSM66201/66P201/66207/66P207
BLOCK DIAGRAM
EA
READY
ALE
PSENRDWR
AD0/P0.0
AD7/P0.7
A8 /P1.0
A15/P1.7
SSP LRB
BUS P
*2
RAM
PSW
O
R
1024 ¥ 8 bits
T
C
O
N
CONT.
MEMORY
ALU
.
T
ROM
32K ¥ 8 bits
*1
IR
PC
RAP
DECODER
INSTRUCTION
*1 MSM66201 16K ¥ 8
PORT
*2 MSM66201 512 ¥ 8
P5
P4
P3
P2
P1
P0
HLDA/P2.5
HOLD/P2.4
R.
ALU CONT.
ACCUMULATOR
TEMPORARY
CONSTANTS
CONTROLLER
SYSTEM
FLT
RES
OSC1
OSC0
GND
V
DD
0–3
TIMER
P4.0/TM0CK
P4.1/TM1CK
P3.4/TM0IO
SERIAL
P3.7/TM3IO
P3.1/RXD
P3.0/TXD
PORT
P2.7/RXC
P2.6/TXC
TION D.
TRANSI-
P4.4/TRNS0
P4.7/TRNS3
A/D
REF
V
P5.0/AI 0
CONV.
AGND
P5.7/AI 7
0,1
PWM
NMI
P4.2/PWM0
P4.3/PWM1
CONT.
INTERRUPT
P3.2/INT0
P3.3/INT1
WDT
CONT.
PERIPHERAL
RESOUT
P2.3/CLKOUT
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¡ Semiconductor MSM66201/66P201/66207/66P207
PIN CONFIGURATION (TOP VIEW)
AD0/P0.0
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
A8/P1.0
A9/P1.1
A10/P1.2
A11/P1.3
A12/P1.4
A13/P1.5
A14/P1.6
A15/P1.7
P2.0
P2.1
P2.2
CLKOUT/P2.3
RESOUT P3.6/TM2IO
PSEN P3.4/TM0IO
READY P3.1/RXD
RES P2.6/TXC
OSC0 P2.5/HLDA
OSC1 P2.4/HOLD
GND NMI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
ALE P3.5/TM1IO
23
24
RD P3.3/INT1
25
WR P3.2/INT0
26
27
EA P3.0/TXD
28
FLT P2.7/RXC
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
DD
V
REF
AGND
P5.7/AI7
P5.6/AI6
P5.5/AI5
P5.4/AI4
P5.3/AI3
P5.2/AI2
P5.1/AI1
P5.0/AI0
P4.7/TRNS3
P4.6/TRNS2
P4.5/TRNS1
P4.4/TRNS0
P4.3/PWM1
P4.2/PWM0
P4.1/TM1CK
P4.0/TM0CK
P3.7/TM3IO
64-Pin Plastic Shrink DIP
4/30
¡ Semiconductor MSM66201/66P201/66207/66P207
PIN CONFIGURATION (TOP VIEW) (Continued)
DDVREF
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
6463626160595857565554
AGND
V
53 P5.7/AI7
52 P5.6/AI6
54 P5.5/AI5
50 P5.4/AI4
49 P5.3/AI3
A8/P1.0
A9/P1.1
A10/P1.2
A11/P1.3
A12/P1.4
A13/P1.5
A14/P1.6
A15/P1.7
P2.0
P2.1
P2.2
1
2
3
4
5
6
7
8
9
10
11
12CLKOUT/P2.3
13RESOUT
14ALE
15PSEN
16RD
1718192021222324252627
EA
WR
READY
FLT
RES
OSC0
OSC1
GND
NMI
HOLD/P2.4
28TXC/P2.6
29RXC/P2.7
HLDA/P2.5
30TXD/P3.0
31RXD/P3.1
48
P5.2/AI2
47
P5.1/AI1
46
P5.0/AI0
45
P4.7/TRNS3
44
P4.6/TRNS2
43
P4.5/TRNS1
42
P4.4/TRNS0
41
P4.3/PWM1
40
P4.2/PWM0
39
P4.1/TM1CK
38
P4.0/TM0CK
37 P3.7/TM3IO
36 P3.6/TM2IO
35 P3.5/TM1IO
34 P3.4/TM0IO
33 P3.3/INT1
32INT0/P3.2
64-Pin Plastic QFP
5/30
¡ Semiconductor MSM66201/66P201/66207/66P207
PIN CONFIGURATION (TOP VIEW) (Continued)
P5.2/AI2
P5.1/AI1
P5.0/AI0
P4.7/TRNS3
P4.6/TRNS2
P4.5/TRNS1
P4.4/TRNS0
P4.3/PWM1
P4.1/TM1CK
P4.0/TM0CKNCP3.7/TM3IO
6059585756555453525150494847464544
P3.6/TM2IO
P3.5/TM1IO
P3.4/TM0IO
P3.3/INT1
AI3/P5.3
AI4/P5.4
AI5/P5.5
AI6/P5.6
AI7/P5.7
AGND
V
REF
V
DD
V
DD
AD0/P0.0
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
61
62
63
64
65
66
67
68
P3.2/INT0
43
P3.1/RXD
42
P3.0/TXD
41
P2.7/RXC
40
P2.6/TXC
39
P2.5/HLDA
38
P2.4/HOLD
37
NMI
36
1
2
3
4
5
6
7
8
9
35
34
33
32
31
30
29
28
27
GND
GND
OSC1
OSC0
RES
FLT
EA
READY
WR
1011121314151617181920212223242526
A8/P1.0
A9/P1.1
A10/P1.2
A11/P1.3
A12/P1.4
A13/P1.5
A14/P1.6
A15/P1.7
NC P4.2/PWM0
P2.0
P2.1
P2.2
RESOUT
ALE
RD
PSEN
CLKOUT/P2.3
NC : No-connection pin
68-Pin Plastic QFJ (PLCC)
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¡ Semiconductor MSM66201/66P201/66207/66P207
PIN DESCRIPTION
Type DescriptionSymbol
P0.0–P0.7/
AD0–AD7
P1.0–P1.7/
A8–A15
P2.0–P2.2
P2.3/CLKOUT CLKOUT: Output pin for supplying a clock to peripheral circuits.
P2.4/HOLD
P2.5/HLDA
P2.6/T
C
X
P2.7/R
CR
X
D
P3.0/T
X
D
P3.1/R
X
P3.2/INT0 R
P3.3/INT1 INT: Interrupt request input pin.
P3.4/TM0IO
P3.5/TM1IO
P3.6/TM2IO
P3.7/TM3IO
I/O
I/O
I/O
I/O
P0: 8-bit input-output port. Each bit can be assigned to input or output.
AD: Outputs the lower 8 bits of program counter during external program memory fetch,
and receives the addressed instruction under the control of PSEN. This pin also
outputs the address and outputs or inputs data during an external data memory
access instruction, under the control of ALE, RD, and WR.
P1: 8-bit input-output port. Each bit can be assigned to input or output.
A: Outputs the upper 8 bits of program counter (PC
) during external program
8–15
memory fetch. This pin also outputs the upper 8 bits of address during external
data memory access instructions.
P2: 8-bit input-output port. Each bit can be assigned to input or output.
HOLD: Input pin to request the CPU to enter the hardware power-down state.
HLDA: HOLD ACKNOWLEDGE: the HLDA signal appears in response to the HOLD
signal and indicates that the CPU has entered the power-down state.
C: Transmitter clock input/output pin.
T
X
C: Receiver clock input/output pin.
X
P3: 8-bit input-output port. Each bit can be assigned to input or output.
TXD: Transmitter data output pin.
D: Receiver data input pin.
X
Falling edge trigger or level trigger is selectable.
TM0IO-TM3IO: One of the following signals is output or input.
• Clock at twice the frequency range of the 16-bit timer overflow
• Load trigger signal to the capture register input
• Setting value output
Whether the signal is input or output depends on the mode.
P4.0/TM0CK P4: 8-bit input-output port. Each bit can be assigned to input or output.
I/O
P4.1/TM1CK TM0CK, TM1CK: Clock input pins of timer 0, timer 1.
P4.2/PWM0
P4.3/PWM1
P4.4
– P4.7/
TRANS: Transition detector.
The input pins which sense the falling edge and set the flag.
PWM: 16-bit pulse-width modulator output pin.
TRANS0 –
TRANS3
P5.0 – P5.7/
AI0 –AI7
I
P5: 8-bit input port.
AI: Analog signal input pin for A/D converter.
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¡ Semiconductor MSM66201/66P201/66207/66P207
PIN DESCRIPTION (Continued)
Type DescriptionSymbol
RESOUT
O
Outputs "H" level in the case of internal reset.
Reset to"L" level by program.
ALE
PSEN Program Strobe Enable:
RD Output strobe activated during a bus read cycle.
WR Output strobe during a bus write cycle.
EA Normaly set to "H" level.
FLT If FLT is "H" level, ALE, WR, RD, PSEN are set to "H" level when reset.
RES RESET input pin.
OSC0
OSC1
NMI Non-maskable interrupt input pin (falling edge).
V
REF
AGND Ground for A/D converter.
V
DD
GND Ground.
O
O
O
O
IREADY Used when the CPU accesses low-speed peripherals.
I
I
I
I
O
I
—
—
—
—
Address Latch Enable:
Used to enable data onto the bus from the external data memory.
Used as write strobe to external data memory.
If set to "L" level, the CPU fetches the code from external program memory.
If FLT is set to "L", ALE, WR, RD, PSEN are set to floating level when reset.
Basic clock oscillation pin.
Basic clock oscillation pin.
Reference voltage input pin for A/D converter.
System power supply.
The timing pulse to latch the lower 8 bits of the address
output from port 0 when the CPU accesses the external
memory.
The strobe pulse to fetch to external program
memory.
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¡ Semiconductor MSM66201/66P201/66207/66P207
REGISTERS
Accumulator
15 0
ACC
Control Register (CR)
15 0
PSW
Bit 15 : Carry flag (CY)
Bit 14 : Zero flag (ZF)
Bit 13 : Half carry flag (HC)
Bit 12 : Data descriptor (DD)
Bit 8 : Master interrupt priority flag (MIP)
Bit 9,5,4: User flag (MIP)
Bit 2-0
: System control base 2-0 (SCB2-0)
15 0
PC
LRB
Pointing Register (PR)
Index Register 1
Index Register 2
Data Pointer
User Stack Pointer
Local Register
SSP
15 0
X1
X2
DP
USP
7070
ER0
ER1
ER2
R1
R3
R5
R0
R2
R4
ER3
R7
R6
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¡ Semiconductor MSM66201/66P201/66207/66P207
SFR
Address
(HEX)
0000
0001
0002
0003
0004I
0005I
0006
0007
0010I
0011
0012I
0013
0018
0019
001A
001B
001CI
0020
0021
0022
0023
0024
0025
0026I
0028
0029
002A
002C
002D
002E
002F
0030
0031
0032
0033
0034
0035
0036
0037
Name Symbol R/W
System stack printer
Local register base
Program status word
Accumulator
Standby control register
Watchdog timer
Peripheral control register
Stop code acceptor
Interrupt request register
Interrupt enable register
External Iinterrupt control register
Port 0 data register
Port 0 mode register
Port 1 data register
Port 1 mode register
Port 2 data register
Port 2 mode register
Port 2 secondary function control register
Port 3 data register
Port 3 mode register
Port 3 secondary function control register
Port 4 data register
Port 4 mode register
Port 4 secondary function control register
Port 5
Timer 0 counter
Timer 0 register
Timer 1 counter
Timer 1 register
SSP
(ASSP)
LRB
(ALRB)
PSWL
(APSW)
PSWH
ACC
SBYCON
WDT
PRPHF
STPACP
IRQ
IE
EXICON
P0
P0IO
P1
P1IO
P2
P2IO
P2SF
P3
P3IO
P3SF
P4
P4IO
P4SF
P5
TM0
TMR0
TM1
TMR1
8/16-bit
Operation
R/W
8/16
W
R/W
W
8/16
R/W
R
R/W 16
Reset
FFH
FFH
undefined
C8H
0CH
00H
00H
F8H
00H/WDT
8
is stopped
FDH
"0"
00H
00H
00H
00H
FCH
undefined
00H
undefined
00H
undefined
8
00H
07H
undefined
00H
00H
undefined
00H
00H
—
00H
00H
00H
00H
00H
00H
00H
00H
Note: A I mark in the address column indicates that there is a bit that does not exist in the
register.
10/30
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