OKI MSM514223B-60RS, MSM514223B-30RS, MSM514223B-40RS Datasheet
E2L0031-17-Y1
¡ Semiconductor MSM514223B
¡ Semiconductor
This version: Jan. 1998
Previous version: Dec. 1996
MSM514223B
262,263-Word ¥ 4-Bit Field Memory
DESCRIRTION
The OKI MSM514223B is a high performance 1-Mbit, 256K ¥ 4-bit, Field Memory. It is designed
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital
movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity
TVs and VTRs, exclusively. The MSM514223B is not designed for the other use or high end use
in medical systems, professional graphics systems which require long term picture, and data
storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen
and cascaded two MSM514223Bs make one frame of the screen: more than two MSM514223Bs
can be cascaded directly without any delay devices among the MSM514223Bs. (Cascading of
MSM514223B provides larger storage depth or a longer delay).
Each of the 4-bit planes has separate serial write and read ports that employ independent control
clocks to support asynchronous read and write operations. Different clock rates are also
supported that allow alternate data rates between write and read data streams.
The MSM514223B provides high speed FIFO, First-In First-Out, operation without external
refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the
users.
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial
access operation, so that serial read and/or write control clock can be halted high or low for any
duration as long as the power is on. Internal conflicts of memory access and refreshing
operations are prevented by special arbitration logic.
The MSM514223B's function is simple, and similar to a digital delay device whose delay-bitlength is easily set by reset timing. The delay length, number of read delay clocks between write
and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 4-bit enable high
speed first-bit-access with no clock delay just after the write or read reset timings.
The MSM514223B is similar in operation and functionality to OKI 1-Mbit Field Memory
MSM514221B besides direct cascade capability. (As for MSM514221B operation compatible 2Mbit Field Memory, OKI has MSM518221 as a sister device of MSM518222).
Additionally, the MSM514223B has write mask function or input enable function (IE), and readdata skipping function or output enable function (OE). The differences between write enable
(WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE
and RE can stop serial write/read address increments but IE and OE can not stop the increment
when write/read clocking is continuously applied to MSM514223B. The input enable (IE)
function allows the user to write into selected locations of the memory only, leaving the rest of
the memory contents unchanged. This facilitate data processing to display a "picture in picture"
on a TV screen.
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¡ Semiconductor MSM514223B
FEATURES
• Single power supply: 5 V ±10%
• 512 Rows ¥ 512 Column ¥ 4 bits
• Fast FIFO (First-in First-out) operation
• High speed asynchronous serial access
Read/Write cycle time 30 ns/40 ns/60 ns
Access time 25 ns/30 ns/50 ns
• Direct cascading capability
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Self refresh (No refresh control is required)
• Package:
18-pin 300 mil plastic DIP (DIP18-P-300-2.54-W1) (Product : MSM514223B-xxRS)
xx indicates speed rank.
PRODUCT FAMILY
Family Cycle Time (Min.)Access Time (Max.) Package
MSM514223B-30RS 30 ns25 ns
MSM514223B-40RS 40 ns30 ns 300 mil 18-pin DIP
MSM514223B-60RS 60 ns50 ns
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¡ Semiconductor MSM514223B
PIN CONFIGURATION (TOP VIEW)
IE
RSTW
SWCK
DIN0
DIN1
DIN2
DIN3
SS
1
2WE
3
4
5
6
7
8
9V
18
17
16
15
14
13
12
11
10 D
V
CC
OE
RE
RSTR
SRCK
D
OUT
D
OUT
D
OUT
OUT
0
1
2
3
18-Pin Plastic DIP
Pin Name Function
SWCK Serial Write Clock
SRCK Serial Read Clock
WE Write Enable
RE Read Enable
IE Input Enable
OE Output Enable
RSTW Write Reset Clock
RSTR Read Reset Clock
0 - 3 Data Input
D
IN
D
0 - 3 Data Output
OUT
V
CC
V
SS
Power Supply (5 V)
Ground (0 V)
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¡ Semiconductor MSM514223B
BLOCK DIAGRAM
D
(¥ 4)
OUT
Data-Out
Buffer (¥ 4)
120 Word
Sub-Register (¥ 4)
120 Word
Sub-Register (¥ 4)
OE
Serial Read Controller
512 Word Serial Read Register (¥ 4)
Read Line Buffer
Low-Half (¥ 4)
Write Line Buffer
Low-Half (¥ 4)
RE RSTR SRCK
Read Line Buffer
High-Half (¥ 4)
256 (¥ 4) 256 (¥ 4)
256K (¥ 4)
Memory
Array
256 (¥ 4) 256 (¥ 4)
Write Line Buffer
High-Half (¥ 4)
Decoder
X
Read/Write
and Refresh
Controller
Clock
Oscillator
Data-In
Buffer (¥ 4)
DIN (¥ 4)
512 Word Serial Write Register (¥ 4)
Serial Write Controller
WE RSTW SWCKIE
V
BB
Generator
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¡ Semiconductor MSM514223B
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset
operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 130 active write cycles, i.e.
SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time
is stored in the serial data registers attached to the DRAM array, an RSTW operation is required
after the last SWCK cycle.
Note that every write timing of MSM514223B is delayed by one clock compared with read
timings for easy cascading without any interface delay devices.
Write Reset : RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters
to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write
reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states
of WE and IE are ignored in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Data Inputs : DIN0 - 3
Write Clock : SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write
address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of
SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low
level disables the input and holds the internal write address pointer. There are no WE disable
time (low) and WE enable time (high) restrictions, because the MSM514223B is in fully static
operation as long as the power is on. Note that WE setup and hold times are referenced to the
rising edge of SWCK.
Input Enable : IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal
write address pointer is always incremented by cycling SWCK regardless of the IE level. Note
that IE setup and hold times are referenced to the rising edge of SWCK.
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