NXP Semiconductors ISP1562, ISP1563 User Manual
AN10050
Designing a Hi-Speed USB host PCI adapter using the
ISP1562, ISP1563
Rev. 04 — 1 November 2007 Application note
Document information
Info Content
Keywords isp1562; isp1563; usb; universal serial bus; host; pci adapter
Abstract This document contains a description of the ISP1562/3 application
schematics and the PCB design recommendations.
NXP Semiconductors
Designing a Hi-Speed USB host PCI adapter using ISP1562/63
Revision history
Rev Date Description
04 20071101 Fourth revision. Corrected typo in Section 4: it is 2.5 inches ± 0.1 inch, not ± 1 inch.
Last line of Section
03 20061212 Third revision. Updated Fig 6.
02 20060707 Second revision. Updated Section 5.
01 20051004 First release.
3.4.
AN10050
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Application note Rev. 04 — 1 November 2007 2 of 18
NXP Semiconductors
AN10050
Designing a Hi-Speed USB host PCI adapter using ISP1562/63
1. Introduction
The ISP1562 and the ISP1563 are Hi-Speed Universal Serial Bus (USB) host controllers
(HCs) that can be directly connected to a standard 32-bit, 33 MHz PCI bus. For the rest
of this document, they will be known as ‘ISP1562/3’. The ISP1562/3 complies with PCI
Local Bus Specification Rev. 2.2 and PCI Bus Power Management Interface
Specification Rev. 1.1. No additional logic is required to implement a complete Hi-Speed
USB host controller solution on Peripheral Component Interconnect (PCI).
Adapter cards based on the ISP1562/3 implement three functions: function 0 and
function 1 for OHCI1 and OHCI2, and function 2 for EHCI. According to PCI Local Bus
Specification, each physical PCI device may incorporate one to eight separate functions
(logical devices). Each function contains its own memory-mapped individually
addressable configuration space of 256 bytes, containing configuration registers.
The configuration registers of the ISP1562/3 are used by the system’s BIOS and the
operating system to detect the presence of the respective functions, that is, Vendor ID
(VID) and Product ID (PID), to determine the necessary resource requirements, that is,
memory and I/O space, interrupt lines, and so on, and for specific capabilities.
A set of on-chip ‘operational’ registers is also defined for each of the three host
controllers implemented in the ISP1562/3. The respective host controller device driver
interacts with these registers to implement the USB functionality and the legacy support.
A detailed description of configuration registers and operational registers can be found in
the ISP1562 and ISP1563 data sheets.
The ISP1562/3 implements two internal ‘power wells’, V
PCI V
= 3.3 V dedicated power source, which is present on the PCI connector (pin
AUX
A14) even when PCI V
asserted and activates the wake-up logic of the motherboard, even if the rest of the
system is powered down; for example, in S3
mainly to onboard (desktop) or mobile designs, but not applicable to PCI add-on cards
because the PCI +5 V, used for V
The ISP1562/3 may use PCI V
ISP1562/3 V
DDA_AUX
Management Event (PME#) logic connected to the ISP1562/3
For details on implementation of the PCB design, see Section
The power management capabilities enabled by using PCI V
to meet the governmental energy regulations that are becoming increasingly essential
worldwide: Energy Star/USA: 30 W standby, White Swan/Europe: 5 W standby, Blue
Angel/Europe: 5 W standby.
This document provides a description of the application schematics and the PCB design
recommendations.
2. ISP1562/3 initialization
The following sequence is required during the ISP1562/3 initialization, for correct
functionality:
1. Register HcRhDescriptorA = 902h. This means that bit PSM = 1b.
2. Register HcControl = 680h. This means that bits HCFS[1:0] = 10b (operational
mode).
and V
DD
= 3.3 V is off. This enables the ISP1562/3 PME# signal to be
CC
system standby mode. This is applicable
cold
, is also off during S3
BUS
to power its four internal transceivers connected to the
AUX
cold
.
, to benefit from the
DDX
(analog), and also the clock circuitry, port router, root hub and Power
V
CC(I/O)_AUX
(digital).
4.
allow system designers
AUX
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Application note Rev. 04 — 1 November 2007 3 of 18
NXP Semiconductors
AN10050
Designing a Hi-Speed USB host PCI adapter using ISP1562/63
3. Register HcRhStatus = 18000h. This implies that bit LPSC = 1b (port powered).
Microsoft Windows 2000, Windows XP and Linux drivers normally use this sequence.
The order of the steps may, however, be reversed in Windows CE default drivers so
changes are required for normal functionality.
3. Description of the application schematics
The schematics (see Section 5) contain a complete implementation of the ISP1562/3 and
allow testing of all its features in different types of design: PCI add-on card, onboard
design in standard desktop or mobile solution.
In the case of a standard PCI add-on card design, some simplifications to the schematics
can be done, as described here. Some features will not be normally used in a standard
PCI add-on card. For example: The legacy support, wake-up from S3
+5 V input for V
) and the alternative 48 MHz clock input. All these alternatives,
BUS
however, are included in the schematics and are described in this document.
3.1 Distribution of power sources and power management support
As shown in the schematics (see Section 5), a simple solution by using one jumper (JP1)
may be adopted to choose between PCI V
power source for the ISP1562/3. Power source PCI V
Local Bus Specification Revision 2.2. It allows powering an add-on card and generation
of the PME# signal, even if the system is in a deep power management state and PCI
V
is off. An alternative solution to using a jumper may be a simple circuit containing a
CC
pair of MOSFET transistors that allows to detect the presence of PCI V
automatic selection of the input voltage.
= 3.3 V or PCI V
CC
AUX
= 3.3 V as the main
AUX
= 3.3 V is introduced in PCI
(no external
cold
= 3.3 V and
AUX
Selection of PCI V
standard add-on card design. The other possible position of JP1 selects PCI V
for complete Power Management tests, including S3
= +3.3 V must be the default position of jumper JP1 in the case of a
CC
= 3.3 V
AUX
in the case of on-motherboard or
cold
notebook. Note that pins 3, 77, 98 and 100 of the ISP1562, and pins 6, 12 and 95 of the
ISP1563 are connected to the PCB V
CC(I/O)_AUX
power plane and pins 86 and 93 of the
ISP1562, and pins 104, 111, 120 and 128 of the ISP1563 are connected to the PCB
V
DDA_AUX
power plane. Each of these planes is separated from PCI V
by its own set of
AUX
inductors and decoupling capacitors.
Although most of the motherboards provide the PCI V
power management modes, including S3
simultaneously interrupted with PCI V
In certain standby modes (S3
), the devices connected to USB ports will not be
cold
, the PCI +5 V power supply is
cold
= +3.3 V.
CC
powered once the +5 V power is removed because the V
connectors is normally derived from the PCI +5 V power supply. Therefore, PCI V
power source in all system
AUX
voltage present on USB
BUS
AUX
is
not useful in the case of a standard PCI add-on card implementation for a system wakeup from S3
. It is, however, a very useful feature for onboard and mobile application
cold
designs because it allows additional considerable power savings and also wakes up the
system by using a USB device. The system wake-up from S3
, generated from a USB
cold
device, for example, USB mouse or USB keyboard, connected to the ISP1562/3 host
controller must be supported in system’s BIOS, hardware (a continuous +5 V must be
supplied to V
) and operating system drivers.
BUS
To be able to test the remote wake-up, especially, from those power management states
in which the +5 V power source on PCI is not present, for example, S3
, a special
cold
connector (J1) is added for an external +5 V source. Any external independent power
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Application note Rev. 04 — 1 November 2007 4 of 18
NXP Semiconductors
Designing a Hi-Speed USB host PCI adapter using ISP1562/63
supply that provides +5 V ± 5 % @ 2 A stabilized can be used. For example, a standard
hub power supply.
Note the distribution of pull-up resistors in the recommended schematics. For example,
to achieve correct functionality, it is recommended that you connect the pull-up resistors
placed on the PWEn_N and OCn_N input signals of the power switch, for example,
MIC2026, to DV
+3.3 V and +5 V are off. The ‘fault flag’ pins (OCn_N) of MIC2026 are open-drain and
require the presence of pull-up resistors. A 100 nF capacitor is used on each OCn_N
signal to prevent false fault conditions.
CLKRUN# is implemented in the ISP1562 on pin 42 and in the ISP1563 on pin 52. This
signal is targeted mainly for mobile system designs. CLKRUN is an I/O pin. It is used by
the system to safely turn-off the PCI CLK for power saving, with acknowledgment from
the ISP1562/3 according to a predefined protocol. In the case of the PCI adapter card
design, CLKRUN# must always be LOW because it is not present in the PCI connector.
CLKRUN# may directly be connected to GND. For details on CLKRUN# function, refer to
PCI Mobile Design Guide Version 1.1.
NET, maintaining a good condition of these signals even when
AUX
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3.2 Input clock: applies only to the ISP1563
You can use either of the following as clock input:
• A 12 MHz crystal; the default recommended solution for best ElectroMagnetic
Interference (EMI) results.
• A 48 MHz oscillator; this may be a useful alternative, typically, in the case of onmotherboard design.
Both solutions for the input clock are shown in the schematics.
To use a 48 MHz clock as input, connect the clock signal to the ISP1563 pin 86 (XTAL1),
pin 87 (XTAL2) can be left open, and pin 121 (SEL48M) must be pulled up as shown in
the schematics.
In an add-on card configuration, normally, the 12 MHz crystal is used. In such a case,
oscillators OSC2 and R45 are not necessary. Also, pin 121 (SEL48M) must directly be
connected to GND. Another possibility is using a 12 MHz clock as an input. In this case,
the 12 MHz-clock signal is directly connected to the ISP1563 pin 86 (XTAL1). This is
similar to the case in which the 48 MHz clock is used; however, the ISP1563 pin 121
must still be connected to GND.
3.3 Selecting the number of ports: applies only to the ISP1563
The selection of the number of ports, 2 or 4, is done using the SEL2PORTS signal
(ISP1563 pin 5). It must be pulled to LOW, that is, connected to GND, for normal use of
all four ports. If SEL2PORTS is HIGH, only two ports, that is, port 1 and port 2, are
enabled; one port from each OHCI will be used in this case for performance
improvement. Details regarding the power consumption and possible power savings in a
two-port configuration can be found in the ISP1563 data sheet.
3.4 Subsystem vendor ID and subsystem device ID
The ISP1562/3 allows loading of the Subsystem Vendor ID (VID) and the Subsystem
Device ID (DID) for both EHCI and OHCI from an external EEPROM. Loading of these
values in the configuration registers of the ISP1562/3 will occur only if a value of 15h is
found in byte 7 of the EEPROM. The necessary signals, I
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Application note Rev. 04 — 1 November 2007 5 of 18
2
C-bus clock and I2C-bus data,
NXP Semiconductors
Designing a Hi-Speed USB host PCI adapter using ISP1562/63
are defined on pins 96 (SCL) and 97 (SDA) of the ISP1562, and pins 122 (SCL) and 123
(SDA) of the ISP1563, respectively. When not in use, these signals must be connected to
ground using a pull-down resistor, typically 10 kΩ.
AN10050
3.5 Legacy support: applies only to the ISP1563
Legacy signals, IRQ1, IRQ12, A20OUT, KBIRQ1, MUIRQ12 and SMI#, are not normally
used on a PCI add-on card design. In this case, the MUIRQ12 and KBIRQ1 input signals
must be connected to GND. The other signals that are mentioned in this category (that
are outputs) can be left open.
Details on legacy signals and a block diagram showing correct connection of these
signals in the case of onboard design can be found in ISP1563 Eval Board User Manual
(UM10066).
3.6 Overcurrent protection
The ISP1562/3 implements the digital overcurrent protection scheme.
The recommended solution to implement an external overcurrent protection is a standard
power switch with integrated overcurrent detection, such as:
• LM3526 and MIC2526 (2 ports), or
• LM3544 (4 ports).
The overcurrent protection logic of the ISP1562/3 uses the following two pins for each
USB port:
• PWEn_N: It is used to enable or disable the respective external port power switch.
For example, MIC2526 and LM3526.
• OCn_N: It is an input on which a fault condition on the respective USB port is
signaled to the ISP1562/3 by the external port power-switching device.
The fault condition that is usually signaled by an external power-switching device can be
an overcurrent or a thermal shutdown. The port power-switching integrated devices
commonly implement a delay of 1 ms to 3 ms to prevent false OC_N reporting because
of inrush currents, when plugging a USB device.
Once a fault condition is received, it will be detected by the operating system and the
respective device driver will disable the port power switch by programming the Port
Power (PP) bit in the PORTSC register. This device driver is the OHCI driver in the case
of an Original USB device to create the fault condition, or the EHCI driver in the case of a
Hi-Speed USB device to create the overcurrent condition. This is according to the USB
port allocation at the moment when the OC# signal was asserted.
A possible alternative is to use a resettable fuse on each port. This has the advantage of
simplicity. It, however, does not inform the operating system of the fault condition and,
therefore, no message is generated to inform the user. The resettable fuse will continue
to protect the port by switching ‘on or off’ as long as the overcurrent condition persists.
A possible enhancement of this scheme is connecting V
ISP1562/3 to detect the OCn_N condition, the first time V
appear on the OCn_N pin.
Using only an external PMOS transistor for overcurrent protection is not possible
because the ISP1562/3 does not implement the analog overcurrent protection (not
measuring the current through the transistor).
to the OCn_N input of the
BUS
is cut-off a LOW level will
BUS
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Application note Rev. 04 — 1 November 2007 6 of 18
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