NXP Semiconductors TDA8752B, Triple high-speed Analog-to-Digital Converter 110 Msps TDA8752B User Manual

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TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Rev. 03 — 21 July 2000

Product specification

1. General description

The TDA8752B is a triple 8-bit ADC with controllable amplifiers and clamps for the digitizing of large bandwidth RGB signals.

The clamp level, the gain and all other settings are controlled via a serial interface (either I2C-bus or 3-wire serial bus, selected via a logic input).

The IC also includes a PLL that can be locked to the horizontal line frequency and generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics applications. An external clock can also be input to the ADC.

It is possible to set the TDA8752B serial bus address to four different values, when several TDA8752B ICs are used in a system, by means of the I2C-bus interface (for example, two ICs used in an odd/even configuration).

2. Features

Triple 8-bit ADC

Sampling rate up to 110 Msps

IC controllable via a serial interface, which can be either I2C-bus or 3-wire serial bus, selected via a TTL input pin

IC analog voltage input from 0.4 to 1.2 V (p-p) to produce a full-scale ADC input of 1 V (p-p)

Three clamps for programming a clamping code between -63.5 and +64 in steps of 1¤2 LSB for RGB signals, and from +120 to +136 in steps of 1¤2 LSB for YUV signals

Three controllable amplifiers: gain controlled via the serial interface to produce a full-scale resolution of 1¤2 LSB peak-to-peak

Amplifier bandwidth of 250 MHz

Low gain variation with temperature

PLL controllable via the serial interface to generate the ADC clock which can be locked to a line frequency of 15 to 280 kHz

Integrated PLL divider

Programmable phase clock adjustment cells

Internal voltage regulators

TTL compatible digital inputs and outputs

Chip enable high-impedance ADC output

Philips Semiconductors

TDA8752B

 

Triple high-speed Analog-to-Digital Converter 110 Msps

Power-down mode

Possibility to use up to four ICs in the same system when using the I2C-bus interface, or more when using the 3-wire serial bus interface

1.1 W power dissipation.

3. Applications

RGB high-speed digitizing

LCD panels drive

LCD projection systems

VGA and higher resolutions

Using two ICs in parallel, a higher display resolution can be obtained: 200 MHz pixel frequency.

4.Quick reference data

Table 1: Quick reference data

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

 

 

VCCA

analog supply voltage

for R, G and B channels

4.75

5.0

5.25

V

 

 

VDDD

logic supply voltage

for I2C-bus and 3-wire

4.75

5.0

5.25

V

 

 

 

serial bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCD

digital supply voltage

 

4.75

5.0

5.25

V

 

 

VCCO

output stages supply voltage

for R, G and B channels

4.75

5.0

5.25

V

 

 

VCCA(PLL)

analog PLL supply voltage

 

4.75

5.0

5.25

V

 

 

VCCO(PLL)

output PLL supply voltage

 

4.75

5.0

5.25

V

 

 

ICCA

analog supply current

 

120

mA

 

 

IDDD

logic supply current

for I2C-bus and 3-wire

1.0

mA

 

 

ICCD

digital supply current

 

40

mA

 

 

ICCO

output stages supply current

fclk = 110 MHz; ramp input

26

mA

 

 

ICCA(PLL)

analog PLL supply current

 

28

mA

 

 

ICCO(PLL)

output PLL supply current

 

5

mA

 

 

fclk

clock frequency

 

110

MHz

 

 

fref(PLL)

PLL reference clock

 

15

280

kHz

 

 

frequency

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fVCO

VCO output clock frequency

 

12

110

MHz

 

 

INL

DC integral non-linearity

from analog input to digital

±0.5

±1.5

LSB

 

 

 

output; full-scale; ramp

 

 

 

 

 

 

 

 

input; fclk = 110 MHz

 

 

 

 

 

 

DNL

DC differential non-linearity

from analog input to digital

±0.5

±1.0

LSB

 

 

 

output; full-scale; ramp

 

 

 

 

 

 

 

 

input; fclk = 110 MHz

 

 

 

 

 

 

Gamp/ T

amplifier gain stability as a

Vref = 2.5 V with

200

ppm/°C

 

 

function of temperature

100 ppm/°C maximum

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

amplifier bandwidth

3 dB; Tamb = 25 °C

250

MHz

 

 

tset

settling time of the ADC block

input signal settling

6

ns

 

 

plus AGC

time <1 ns; Tamb = 25 °C

 

 

 

 

 

 

9397 750 07338

 

 

 

 

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

2 of 38

 

Philips Semiconductors

 

 

 

 

 

TDA8752B

 

 

 

 

 

Triple high-speed Analog-to-Digital Converter 110 Msps

Table 1: Quick reference data…continued

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

 

Conditions

Min

Typ

Max

Unit

 

 

DRPLL

PLL divider ratio

 

 

100

4095

 

 

 

Ptot

total power dissipation

 

fclk = 110 MHz; ramp input

1.1

W

 

 

jPLL(rms)

maximum PLL phase jitter

fref = 66.67 kHz;

112

ps

 

 

(RMS value)

 

fclk = 110 MHz

 

 

 

 

 

 

 

5. Ordering information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 2:

Ordering information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type number

Package

 

 

 

 

 

 

Sampling

 

 

 

 

 

 

 

 

 

 

 

frequency (MHz)

 

 

 

 

Name

Description

 

 

Version

 

 

 

 

 

 

 

 

 

 

TDA8752BH/8

QFP100

plastic quad flat package; 100 leads (lead length

 

SOT317-2 110

 

 

 

 

 

 

1.95 mm); body 14 × 20 × 2.8 mm

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

3 of 38

Philips Semiconductors

TDA8752B

 

Triple high-speed Analog-to-Digital Converter 110 Msps

6. Block diagram

 

VCCA(R) VCCA(B) VCCO(R) VCCO(B) VCCA(PLL)

CLP

AGNDG

VSSD

OGNDG AGNDPLL

DGND

 

 

VCCA(G)

VDDD

VCCO(G)

VCCD

VCCO(PLL) AGNDR

AGNDB

OGNDR

OGNDB

OGNDPLL

 

 

11

19

27

40

79

69

59

95

99

85

89

13

21

29

41

70

60

48

96

82

86

 

RAGC

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

RCLP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RGAINC

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

RBOT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RIN

12

 

 

 

 

 

 

 

 

CLAMP

 

 

 

 

 

 

 

 

71 to 78

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R0 to R7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RDEC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MUX

 

 

 

 

 

 

 

 

 

 

 

OUTPUTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vref

3

 

 

 

 

 

 

 

 

 

 

 

 

ADC

 

 

 

 

 

45

ROR

 

 

 

 

 

 

 

RED CHANNEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GAGC

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

GCLP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

GGAINC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GBOT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GIN

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

61 to 68

G0 to G7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

 

 

 

 

 

 

 

GREEN CHANNEL

 

 

 

 

 

 

 

 

 

GDEC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

46

GOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

87

OE

 

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

BAGC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BCLP

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23

BGAINC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BBOT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIN

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

49, 52 to 58

B0 to B7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

 

 

 

 

 

BLUE CHANNEL

 

 

 

 

 

 

 

 

47

BDEC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

36

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

84

 

35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKADCO

TCK

 

 

 

 

HSYNCI

 

 

TDA8752B

 

 

 

 

 

 

 

 

83

34

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKBO

ADD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

81

 

ADD1

SERIAL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKAO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

38

INTERFACE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80

SEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKREFO

42

I2C-BUS

 

 

 

 

REGULATOR

 

 

 

 

 

 

 

 

 

 

SCL

 

OR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

39

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

92

 

SDA

3-WIRE

 

 

 

 

 

 

 

 

 

 

PLL

 

 

 

 

 

CKEXT

37

 

 

 

 

I2C-bus; 1-bit

 

 

 

 

 

 

 

 

 

 

 

91

DIS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INV

32

 

 

 

 

(Hlevel)

 

 

 

 

 

 

 

 

 

 

 

 

 

93

I2C/3W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COAST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

94

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKREF

 

1, 5, 30, 31, 43 , 44

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50, 51, 100

 

 

90

 

 

 

4

2

 

88

 

97

98

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FCE467

 

 

n.c.

 

 

 

HSYNC

 

 

DEC1

DEC2

PWDWN

CP

CZ

 

 

 

 

 

 

Fig 1.

Block diagram.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

4 of 38

Philips Semiconductors

TDA8752B

 

Triple high-speed Analog-to-Digital Converter 110 Msps

 

CLP

 

RAGC

 

 

RCLP

 

CLAMP

 

 

 

 

 

 

 

 

 

 

 

VP

CONTROL

 

 

 

 

 

 

 

 

 

 

 

150

 

 

 

DAC

 

 

 

 

CLKADC

 

 

RIN

 

 

 

 

 

 

 

8

 

 

 

 

 

 

Vref

MUX

AGC

 

ADC

REGISTER

ROR

 

3 kΩ

VCCAR

 

 

I2C-bus: 8 bits (Or)

8

 

 

 

OUTPUTS

 

 

 

 

 

R0 to R7

 

 

 

 

 

8

 

 

45 kΩ

 

 

D

 

OE

 

DAC

 

 

D ≥ R

 

 

 

 

 

 

R

8

RBOT

 

5

 

 

1

 

 

 

 

 

 

 

 

 

 

7

 

 

REGISTER

 

1

REGISTER

 

 

FINE GAIN ADJUST

 

COARSE GAIN ADJUST

 

 

 

 

 

 

I2C-bus: 5 bits (Fr)

 

 

I2C-bus: 7 bits (Cr)

 

 

 

 

 

 

I2C-BUS

 

 

 

 

 

 

 

FCE468

 

 

RGAINC

 

 

 

 

 

HSYNCI

 

 

 

 

 

Fig 2. Red channel diagram.

 

 

 

 

 

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

5 of 38

 

Philips Semiconductors

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDA8752B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Triple high-speed Analog-to-Digital Converter 110 Msps

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CZ

CP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COAST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKEXT

 

INV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CZ

CP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C-bus; 1 bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Vlevel)

 

 

 

 

loop filter

 

 

 

 

 

 

12 to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKREF

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C-bus;

 

 

 

 

 

 

100 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

 

 

 

 

 

 

3 bits (Z)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0°/180°

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

edge selector

FREQUENCY

 

 

 

 

 

 

 

 

 

VCO

 

 

 

 

 

 

 

MUX

 

 

 

 

 

 

 

 

 

 

CKADCO

 

 

I2C-bus;

 

 

 

DETECTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 bit

 

 

 

I2C-bus; 5 bits

 

 

 

 

 

I2C-bus;

phase selector A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Edge)

 

 

 

 

 

 

 

2 bits (Vco)

I2C-bus;

 

 

 

 

 

 

 

 

 

CLKADC

 

 

 

 

 

(Ip, Up, Do)

 

 

 

 

I2C-bus;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 bits (Pa)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 bit (Cka)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIV N (100 to 4095)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MUX

 

 

 

 

 

 

CKBO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C-bus; 12 bits (Di)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

phase selector B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-bus;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 bit (Ckb)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C-bus; 5 bits (Pb)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NCKBO

 

 

 

 

 

MUX

 

 

 

 

 

 

CKAO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C-

bus;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 bit (Ckab)

 

 

 

 

 

CKREFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYNCHRO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FCE465

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fig 3. PLL diagram.

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

6 of 38

Philips Semiconductors

TDA8752B

 

Triple high-speed Analog-to-Digital Converter 110 Msps

7.Pinning information

7.1Pinning

n.c. 1

DEC2 2

Vref 3

DEC1 4

n.c. 5

RAGC 6

RBOT 7

RGAINC 8

RCLP 9

RDEC 10

VCCA(R) 11

RIN 12

AGNDR 13 GAGC 14

GBOT 15

GGAINC 16

GCLP 17

GDEC 18

VCCA(G) 19 GIN 20

AGNDG 21 BAGC 22

BBOT 23

BGAINC 24

BCLP 25

BDEC 26

VCCA(B) 27 BIN 28

AGNDB 29 n.c. 30

 

 

CCA(PLL)

 

 

 

 

PLL

CCD

CKREF

 

COAST

 

CKEXT

 

 

 

HSYNC

 

 

 

PWDWN

 

 

 

 

 

CCO(PLL)

CKADCO

 

 

 

PLL

 

 

n.c.

 

CZ

 

CP

 

AGND

 

 

 

INV

 

 

CLP

 

 

OE

 

DGND

 

 

CKBO

 

OGND

 

CKAO

 

V

 

 

V

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

100

 

99

 

98

 

97

 

96

 

95

 

94

 

93

 

92

 

91

 

90

 

89

 

88

 

87

 

86

 

85

 

84

 

83

 

82

 

81

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDA8752BH

31

 

32

 

33

 

34

 

35

 

36

 

37

 

38

 

39

 

40

 

41

 

42

 

43

 

44

 

45

 

46

 

47

 

48

 

49

 

50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

n.c.

 

C/3W

 

ADD1

 

ADD2

 

TCK

 

TDO

 

DIS

 

SEN

 

SDA

 

DDD

SSD

SCL

 

n.c.

 

n.c.

 

ROR

 

GOR

 

BOR

 

B

B0

 

n.c.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OGND

 

 

I

 

 

 

 

 

 

 

 

V

V

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80

CKREFO

 

VCCO(R)

79

 

78

R7

 

R6

77

 

R5

76

 

R4

75

 

R3

74

 

R2

73

 

R1

72

 

R0

71

 

OGNDR

70

 

69

VCCO(G)

 

68

G7

 

G6

67

 

G5

66

 

G4

65

 

G3

64

 

G2

63

 

G1

62

 

G0

61

 

OGNDG

60

 

59

VCCO(B)

 

58

B7

 

B6

57

 

B5

56

 

B4

55

 

B3

54

 

B2

53

 

B1

52

 

n.c.

51

FCE469

Fig 4. Pin configuration.

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

7 of 38

Philips Semiconductors

 

TDA8752B

 

 

 

 

 

Triple high-speed Analog-to-Digital Converter 110 Msps

7.2 Pin description

 

 

 

Table 3:

Pin description

 

 

 

 

 

 

 

 

 

Symbol

Pin

Description

 

 

n.c.

1

not connected

 

 

 

 

 

 

DEC2

2

main regulator decoupling input 2

 

 

 

 

 

 

Vref

3

gain stabilizer voltage reference input

 

 

DEC1

4

main regulator decoupling input 1

 

 

 

 

 

 

n.c.

5

not connected

 

 

 

 

 

 

RAGC

6

red channel AGC output

 

 

 

 

 

 

RBOT

7

red channel ladder decoupling input (BOT)

 

 

 

 

 

 

RGAINC

8

red channel gain capacitor input

 

 

 

 

 

 

RCLP

9

red channel gain clamp capacitor input

 

 

 

 

 

 

RDEC

10

red channel gain regulator decoupling input

 

 

 

 

 

 

VCCA(R)

11

red channel gain analog power supply

 

 

RIN

12

red channel gain analog input

 

 

 

 

 

 

AGNDR

13

red channel gain analog ground

 

 

GAGC

14

green channel AGC output

 

 

 

 

 

 

GBOT

15

green channel ladder decoupling input (BOT)

 

 

 

 

 

 

GGAINC

16

green channel gain capacitor input

 

 

 

 

 

 

GCLP

17

green channel gain clamp capacitor input

 

 

 

 

 

 

GDEC

18

green channel gain regulator decoupling input

 

 

 

 

 

 

VCCA(G)

19

green channel gain analog power supply

 

 

GIN

20

green channel gain analog input

 

 

 

 

 

 

AGNDG

21

green channel gain analog ground

 

 

BAGC

22

blue channel AGC output

 

 

 

 

 

 

BBOT

23

blue channel ladder decoupling input (BOT)

 

 

 

 

 

 

BGAINC

24

blue channel gain capacitor input

 

 

 

 

 

 

BCLP

25

blue channel gain clamp capacitor input

 

 

 

 

 

 

BDEC

26

blue channel gain regulator decoupling input

 

 

 

 

 

 

VCCA(B)

27

blue channel gain analog power supply

 

 

BIN

28

blue channel gain analog input

 

 

 

 

 

 

AGNDB

29

blue channel gain analog ground

 

 

n.c.

30

not connected

 

 

 

 

 

 

n.c.

31

not connected

 

 

 

 

 

 

 

 

 

 

32

selection input between I2C-bus (active HIGH) and 3-wire

 

I2C/3W

 

 

 

 

 

 

serial bus (active LOW)

 

 

 

 

 

 

ADD1

33

I2C-bus address control input 1

 

 

ADD2

34

I2C-bus address control input 2

 

 

TCK

35

scan test mode input (active HIGH)

 

 

 

 

 

 

TDO

36

scan test output

 

 

 

 

 

 

DIS

37

I2C-bus and 3-wire serial bus disable control input (disable at

 

 

 

 

 

HIGH level)

 

 

 

 

 

 

SEN

38

select enable for 3-wire serial bus input (see Figure 10)

 

 

 

 

 

 

 

9397 750 07338

 

 

 

 

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

8 of 38

Philips Semiconductors

 

TDA8752B

 

 

 

Triple high-speed Analog-to-Digital Converter 110 Msps

 

Table 3: Pin description…continued

 

 

 

 

 

Symbol

Pin

Description

 

 

SDA

39

I2C-bus/3-wire serial bus data input

 

 

VDDD

40

logic I2C-bus/3-wire serial bus digital power supply

 

 

VSSD

41

logic I2C-bus/3-wire serial bus digital ground

 

 

SCL

42

I2C-bus/3-wire serial bus clock input

 

 

n.c.

43

not connected

 

 

 

 

 

 

n.c.

44

not connected

 

 

 

 

 

 

ROR

45

red channel ADC output bit out of range

 

 

 

 

 

 

GOR

46

green channel ADC output bit out of range

 

 

 

 

 

 

BOR

47

blue channel ADC output bit out of range

 

 

 

 

 

 

OGNDB

48

blue channel ADC output ground

 

 

B0

49

blue channel ADC output bit 0 (LSB)

 

 

 

 

 

 

n.c.

50

not connected

 

 

 

 

 

 

n.c.

51

not connected

 

 

 

 

 

 

B1

52

blue channel ADC output bit 1

 

 

 

 

 

 

B2

53

blue channel ADC output bit 2

 

 

 

 

 

 

B3

54

blue channel ADC output bit 3

 

 

 

 

 

 

B4

55

blue channel ADC output bit 4

 

 

 

 

 

 

B5

56

blue channel ADC output bit 5

 

 

 

 

 

 

B6

57

blue channel ADC output bit 6

 

 

 

 

 

 

B7

58

blue channel ADC output bit 7 (MSB)

 

 

 

 

 

 

VCCO(B)

59

blue channel ADC output power supply

 

 

OGNDG

60

green channel ADC output ground

 

 

G0

61

green channel ADC output bit 0 (LSB)

 

 

 

 

 

 

G1

62

green channel ADC output bit 1

 

 

 

 

 

 

G2

63

green channel ADC output bit 2

 

 

 

 

 

 

G3

64

green channel ADC output bit 3

 

 

 

 

 

 

G4

65

green channel ADC output bit 4

 

 

 

 

 

 

G5

66

green channel ADC output bit 5

 

 

 

 

 

 

G6

67

green channel ADC output bit 6

 

 

 

 

 

 

G7

68

green channel ADC output bit 7 (MSB)

 

 

 

 

 

 

VCCO(G)

69

green channel ADC output power supply

 

 

OGNDR

70

red channel ADC output ground

 

 

R0

71

red channel ADC output bit 0 (LSB)

 

 

 

 

 

 

R1

72

red channel ADC output bit 1

 

 

 

 

 

 

R2

73

red channel ADC output bit 2

 

 

 

 

 

 

R3

74

red channel ADC output bit 3

 

 

 

 

 

 

R4

75

red channel ADC output bit 4

 

 

 

 

 

 

R5

76

red channel ADC output bit 5

 

 

 

 

 

 

R6

77

red channel ADC output bit 6

 

 

 

 

 

 

R7

78

red channel ADC output bit 7 (MSB)

 

 

 

 

 

 

VCCO(R)

79

red channel ADC output power supply

 

9397 750 07338

 

 

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

9 of 38

Philips Semiconductors

 

 

 

 

 

TDA8752B

 

 

 

 

Triple high-speed Analog-to-Digital Converter 110 Msps

 

Table 3: Pin description…continued

 

 

 

 

 

Symbol

Pin

Description

 

 

CKREFO

80

reference output clock re-synchronized horizontal pulse

 

 

 

 

 

 

CKAO

81

PLL clock output 3 (in phase with reference output clock

 

 

 

 

CKAO or

 

 

 

 

 

 

 

 

 

CKBO)

 

 

 

 

 

 

OGNDPLL

82

PLL digital ground

 

 

CKBO

83

PLL clock output 2

 

 

 

 

 

 

CKADCO

84

PLL clock output 1 (in phase with internal ADC clock)

 

 

 

 

 

 

VCCO(PLL)

85

PLL output power supply

 

 

DGND

86

digital ground

 

 

 

 

 

 

 

 

 

 

 

87

output enable; active LOW (when

 

is HIGH, the outputs are

 

OE

OE

 

 

 

 

in high-impedance)

 

 

 

 

 

 

PWDWN

88

power-down control input (device is in Power-down mode

 

 

 

 

when this pin is HIGH)

 

 

 

 

 

 

CLP

89

clamp pulse input (clamp active HIGH)

 

 

 

 

 

 

HSYNC

90

horizontal synchronization input pulse

 

 

 

 

 

 

INV

91

PLL clock output inverter command input (invert when HIGH)

 

 

 

 

 

 

CKEXT

92

external clock input

 

 

 

 

 

 

COAST

93

PLL coast command input

 

 

 

 

 

 

CKREF

94

PLL reference clock input

 

 

 

 

 

 

VCCD

95

digital power supply

 

 

AGNDPLL

96

PLL analog ground

 

 

CP

97

PLL filter input

 

 

 

 

 

 

CZ

98

PLL filter input

 

 

 

 

 

 

VCCA(PLL)

99

PLL analog power supply

 

 

n.c.

100

not connected

 

 

 

 

 

 

 

 

 

 

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

10 of 38

Philips Semiconductors

TDA8752B

 

Triple high-speed Analog-to-Digital Converter 110 Msps

8. Functional description

This triple high-speed 8-bit ADC is designed to convert RGB signals, coming from an analog source, into digital data used by a LCD driver (pixel clock up to 200 MHz when using 2 ICs).

8.1 IC analog video inputs

The video inputs are internally DC polarized. These inputs are AC coupled externally.

8.2 Clamps

Three independent parallel clamping circuits are used to clamp the video input signals on the black level and to control the brightness level. The clamping code is programmable between code -63.5 and +64 and from +120 to +136 in steps of 1¤2 LSB. The programming of the clamp value is achieved via an 8-bit DAC. Each clamp must be able to correct an offset from ±0.1 V to ±10 mV within 300 ns, and correct the total offset in 10 lines.

The clamps are controlled by an external TTL positive going pulse (pin CLP). The drop of the video signal is <1 LSB.

Normally, the circuit operates with a 0 code clamp, corresponding to the 0 ADC code. This clamp code can be changed from -63.5 to +64 as represented in Figure 5, in steps of 1¤2 LSB. The digitized video signal is always between code 0 and code 255 of the ADC. It is also possible to clamp from code 120 to code 136 corresponding to 120 ADC code to 136 ADC code. Then clamping on code 128 of the ADC is possible.

255

 

 

digitized

 

 

video

 

= 120 to 136

signal

code 64

 

 

clamp

 

code 0

 

programming

 

code −63.5

 

 

video signal

CLP

FCE471

Fig 5. Clamp definition.

8.3 Variable gain amplifiers

Three independent variable gain amplifiers are used to provide, to each channel, a full-scale input range signal to the 8-bit ADC. The gain adjustment range is designed so that for an input range varying from 0.4 to 1.2 V (p-p), the output signal corresponds to the ADC full-scale input of 1 V (p-p).

To ensure that the gain does not vary over the whole operating temperature range, an external supplied reference voltage Vref = 2.5 V (DC), with a maximum variation of 100 ppm/°C, is used to calibrate the gain at the beginning of each video line before the clamp pulse.

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

11 of 38

Philips Semiconductors

TDA8752B

 

Triple high-speed Analog-to-Digital Converter 110 Msps

The calibration of the gains is done using the following principle.

From the reference voltage Vref a reference signal of 0.156 V (p-p) (1¤16Vref) is generated internally. During the synchronization part of the video line, the multiplexer,

controlled by the TTL synchronization signal (HSYNCI, coming from HSYNC;

see Figure 1) with a width equal to one of the video synchronization signals (e.g. the signal coming from a synchronization separator), is switched between the two amplifiers.

The output of the multiplexer is either the normal video signal or the 0.156 V reference signal (during HSYNC).

The corresponding ADC outputs are then compared to a preset value loaded in a register. Depending on the result of the comparison, the gain of the variable gain amplifiers is adjusted (coarse gain control; see Figure 2 and 6). The three 7-bit registers receive data via a serial interface to enable the gain to be programmed.

The preset value loaded in the 7-bit register is chosen between approximately

67 codes to ensure the full-scale input range (see Figure 6). A contrast control can be achieved using these registers. In this case care should be taken to stay within the allowed code range (32 to 99).

A fine correction using three 5-bit DACs, also controlled via the serial interface, is used to fine tune the gain of the three channels (fine gain control; see Figure 2 and 7) and to compensate the channel-to-channel gain mismatch.

With a full-scale ADC input, the resolution of the fine register corresponds to 1¤2 LSB peak-to-peak variation.

To use these gain controls correctly, it is recommended to fix the coarse gain (to have a full-scale ADC input signal) to within 4 LSB and then adjust it with the fine gain. The gain is adjusted during HSYNC. During this time the output signal is not related to the amplified input signal. The outputs, when the coarse gain system is stable, are related to the programmed coarse code (see Figure 6).

NCOARSE

 

 

 

ADC output

 

code

 

 

 

code

 

 

 

 

 

 

 

127

 

 

 

255

 

 

G(max)

 

G(min)

 

coarse

 

99

 

 

 

227

register

 

 

 

 

 

 

value

 

 

 

 

 

 

(67 codes)

32

 

 

 

160

 

 

 

 

 

 

 

0

 

 

 

128

 

 

Vref

0.2

0.6

Vi (p-p)

 

 

0.156 =

 

 

16

 

 

2

 

 

 

 

 

 

 

 

 

 

 

FCE472

Fig 6. Coarse gain control.

9397 750 07338

© Philips Electronics N.V. 2000. All rights reserved.

Product specification

Rev. 03 — 21 July 2000

12 of 38

+ 26 hidden pages