NXP Semiconductors CBT3126 User Manual

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CBT3126

Quad FET bus switch

Rev. 04 — 12 October 2009

Product data sheet

1. General description

The CBT3126 is a quad FET bus switch with independent line switches. Each switch is disabled when the associated Output Enable (OE) input is LOW.

The CBT3126 is characterized for operation from 40 °C to +85 °C.

2. Features

nStandard ’126-type pinout

nMultiple package options

n5 Ω switch connection between two ports

nTTL-compatible input levels

nMinimal propagation delay through the switch

nLatch-up protection exceeds 500 mA per JEDEC standard JESD78 class II level A

nESD protection:

uHBM JESD22-A114E exceeds 2000 V

uMM JESD22-A115-A exceeds 200 V

uCDM JESD22-C101C exceeds 1000 V

nSpecified from 40 °C to +85 °C

3.Ordering information

Table 1. Ordering information

Type number

Temperature range

Package

 

 

 

 

Name

Description

Version

CBT3126D

40 °C to +85 °C

SO14

plastic small outline package; 14 leads;

SOT108-1

 

 

 

 

 

body width 3.9 mm

 

 

 

 

 

 

CBT3126DB

40 °C to +85 °C

SSOP14

plastic shrink small outline package; 14 leads;

SOT337-1

 

 

 

 

 

body width 5.3 mm

 

 

 

 

 

 

CBT3126PW

40 °C to +85 °C

TSSOP14

plastic thin shrink small outline package; 14 leads;

SOT402-1

 

 

 

 

 

body width 4.4 mm

 

 

 

 

 

 

 

 

CBT3126DS

40 °C to +85 °C

SSOP16

[1]

 

plastic shrink small outline package; 16 leads;

SOT519-1

 

 

 

 

 

 

body width 3.9 mm; lead pitch 0.635 mm

 

 

 

 

 

 

 

 

[1]Also known as QSOP16.

NXP Semiconductors

CBT3126

 

Quad FET bus switch

4. Functional diagram

1OE

1A 1B

2OE

2A 2B

3OE

3A 3B

4OE

4A 4B

001aaj023

Fig 1. Logic symbol

1A

2

 

 

 

3

1B

1

 

 

 

 

 

 

1OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

6

 

2A

 

 

2B

4

 

 

 

 

 

 

2OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

8

3B

3A

 

 

10

 

 

 

 

 

 

3OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

11

4B

4A

 

 

 

 

 

13

 

 

 

 

 

 

4OE

 

 

 

 

 

001aaj024

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin numbers are for the 14 pin packages.

Fig 2. Logic diagram

5.Pinning information

5.1Pinning

 

 

 

CBT3126

 

 

 

 

 

 

 

 

 

 

1OE

1

 

 

14

VCC

 

 

 

 

 

 

CBT3126

 

 

 

 

 

 

 

 

 

 

1A

2

 

 

13

4OE

 

 

CBT3126

 

 

 

 

 

 

 

 

 

 

 

n.c.

1

16

VCC

 

 

 

 

 

 

 

 

 

 

1B

3

 

 

12

4A

1OE

1

14

VCC

1OE

2

15

4OE

2OE

4

 

 

11

4B

1A

2

13

4OE

1A

3

14

4A

 

 

1B

3

12

4A

1B

4

13

4B

 

 

 

 

 

 

2A

5

 

 

10

3OE

2OE

4

11

4B

2OE

5

12

3OE

2B

6

 

 

9

3A

2A

5

10

3OE

2A

6

11

3A

 

 

2B

6

9

3A

2B

7

10

3B

 

 

 

 

 

 

GND

7

 

 

8

3B

GND

7

8

3B

GND

8

9

n.c.

 

 

 

001aaj111

 

 

 

 

001aaj025

 

 

 

001aaj026

 

 

 

 

 

 

 

 

 

 

 

 

Fig 3.

Pin configuration

 

 

Fig 4.

 

Pin configuration

 

Fig 5.

 

Pin configuration

 

 

SOT108-1 (SO14)

 

 

 

 

SOT337-1 (SSOP14) and

 

 

SOT519-1 (SSOP16)

 

 

 

 

 

 

 

 

 

SOT402-1 (TSSOP14)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.2 Pin description

Table 2. Pin description

Symbol

Pin

 

Description

 

SOT108-1 SOT337-1 and SOT402-1

SOT519-1

 

1OE to 4OE

1, 4, 10, 13

2, 5, 12, 15

output enable input

 

 

 

 

1A to 4A,

2, 5, 9, 12

3, 6, 11, 14

A input/output

 

 

 

 

1B to 4B

3, 6, 8, 11

4, 7, 10, 13

B output/input

CBT3126_4

 

 

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 12 October 2009

2 of 13

NXP Semiconductors

 

CBT3126

 

 

 

 

Quad FET bus switch

Table 2.

Pin description …continued

 

 

 

 

 

 

 

Symbol

 

Pin

 

Description

 

 

SOT108-1 SOT337-1 and SOT402-1

SOT519-1

 

GND

7

8

ground (0 V)

 

 

 

 

VCC

14

16

positive supply voltage

n.c.

-

1, 9

not connected

 

 

 

 

 

6. Functional description

Table 3. Function selection

H = HIGH voltage level; L = LOW voltage level.

Inputs

Switch

nOE

 

L

nA to nB disconnected

 

 

H

nA to nB connected

 

 

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

 

Min

Max

Unit

VCC

supply voltage

 

 

0.5

+7.0

V

VI

input voltage

 

[1]

0.5

+7.0

V

 

 

ISW

switch current

continuous current through each switch

 

-

128

mA

IIK

input clamping current

VI < 0 V

 

50

-

mA

Tstg

storage temperature

 

 

65

+150

°C

Ptot

total power dissipation

Tamb = 40 °C to +125 °C

[2]

 

 

 

 

 

 

 

 

 

SO14 package

[3]

-

500

mW

 

 

 

 

 

 

 

 

 

 

 

 

SSOP14 and SSOP16 package

[4]

-

500

mW

 

 

 

 

 

 

 

 

 

 

 

 

TSSOP14 package

[4]

-

500

mW

 

 

 

 

 

 

 

 

 

 

[1]The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[2]The package thermal impedance is calculated from JESD51-7.

[3]For SO14 package; Ptot derates linearly with 8 mW/K above 70 °C.

[4]For SSOP14, SSOP16 and TSSOP14 packages; Ptot derates linearly with 5.5 mW/K above 70 °C.

8. Recommended operating conditions

Table 5. Operating conditions

All unused control inputs of the device must be held at VCC or GND to ensure proper device operation.

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

 

4.5

5.5

V

VIH

HIGH-level input voltage

 

2.0

-

V

VIL

LOW-level input voltage

 

-

0.8

V

Tamb

ambient temperature

operating in free-air

40

+85

°C

CBT3126_4

 

 

 

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 12 October 2009

3 of 13

NXP Semiconductors

 

 

 

 

CBT3126

 

 

 

 

 

Quad FET bus switch

9. Static characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 6.

Static characteristics

 

 

 

 

 

 

 

Tamb = 40 °C to +85 °C.

 

 

 

 

 

 

 

Symbol

Parameter

Conditions

 

Min

Typ

[1]

Max

Unit

 

VIK

input clamping voltage

VCC = 4.5 V; II = 18 mA

-

-

 

1.2

V

Vpass

pass voltage

VI = VCC = 5.0 V; ISW = 100 μA

-

3.8

 

-

V

II

input leakage current

VCC = 5.5 V; VI = GND or 5.5 V

-

-

 

±1

μA

ICC

supply current

VCC = 5.5 V; ISW = 0 mA;

-

-

 

3

μA

 

 

VI = VCC or GND

 

 

 

 

 

 

ICC

additional supply current

control pins; per input;

[2]

-

-

 

2.5

mA

 

 

 

 

VCC = 5.5 V; one input at 3.4 V,

 

 

 

 

 

 

 

 

other inputs at VCC or GND

 

 

 

 

 

 

CI

input capacitance

control pins; VI = 3 V or 0 V

-

1.7

 

-

pF

Cio(off)

off-state input/output capacitance

VO = 3 V or 0 V; nOE = VCC

-

3.4

 

-

pF

RON

ON resistance

VCC = 4.0 V

[3]

 

 

 

 

 

 

 

 

 

 

 

 

VI = 2.4 V; II = 15 mA

-

16

 

22

Ω

 

 

VCC = 4.5 V

 

 

 

 

 

 

 

 

VI = 0 V; II = 64 mA

-

5

 

7

Ω

 

 

VI = 0 V; II = 30 mA

-

5

 

7

Ω

 

 

VI = 2.4 V; II = 15 mA

-

10

 

15

Ω

[1]All typical values are measured at VCC = 5 V; Tamb = 25 °C.

[2]This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

[3]Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is determined by the lowest voltage of the two (A or B) terminals.

10. Dynamic characteristics

Table 7. Dynamic characteristics

Tamb = 40 °C to +85 °C; VCC = 4.5 V to 5.5 V; for test circuit see Figure 8.

Symbol

Parameter

Conditions

 

 

Min

Max

Unit

tpd

propagation delay

nA to nB or nB to nA; see Figure 6

[1][2]

-

0.25

ns

 

 

ten

enable time

nOE to nA or nB; see Figure 7

[2]

1.6

4.5

ns

 

 

tdis

disable time

nOE to nA or nB; see Figure 7

[2]

1.0

5.4

ns

 

 

[1]This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance).

[2]tPLH and tPHL are the same as tpd; tPZL and tPZH are the same as ten; tPLZ and tPHZ are the same as tdis.

CBT3126_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 12 October 2009

4 of 13

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