NXP Semiconductors TFA9812 User Manual

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TFA9812

BTL stereo Class-D audio amplifier with I 2S input

Rev. 02 — 22 January 2009

Preliminary data sheet

1. General description

The TFA9812 is a high-efficiency Bridge Tied Load (BTL) stereo Class-D audio amplifier with a digital I2S audio input. It is available in a HVQFN48 package with exposed die paddle. The exposed die paddle technology enhances the thermal and electrical performances of the device.

The TFA9812 features digital sound processing and audio power amplification. It supports I2C control mode and Legacy mode. In Legacy mode I2C involvement is not needed because the key features are controlled by hardware pin connections.

A continuous time output power of 2 × 12 W (RL = 8 Ω, VDDP = 15 V) is supported without an external heat sink. Due to the implementation of a programmable thermal foldback even for high supply voltages, higher ambient temperatures, and/or lower load impedances, the device operates without sound interrupting behavior.

TFA9812 is designed in such a way that it starts up easily (no special power-up sequence required). It features various soft and hard impact protection mechanisms to ensure an application that is both user friendly and robust.

A modulation technique is applied for the TFA9812, which supports common mode choke approach (1 common mode choke only per BTL amplifier stage). This minimizes the number of external components.

2.Features

2.1General features

n3.3 V and 8 V to 20 V external power supply

nHigh efficiency and low power dissipation

nSpeaker outputs fully short circuit proof across load, to supply lines and ground

nPop noise free at power-up/power-down and sample rate switching

nLow power Sleep mode

nOvervoltage and undervoltage protection on the 8 V to 20 V power supply

nUndervoltage protection on the 3.3 V power supply

nOvercurrent protection (no audible interruptions)

nOverdissipation protection

nThermally protected and programmable thermal foldback

nClock error protection

nI2C mode control or Legacy mode (i.e. no I2C) control

nFour different I2C addresses supported

nInternal Phase-Locked Loop (PLL) without using external components

NXP Semiconductors

TFA9812

 

BTL stereo Class-D audio amplifier with I 2S input

nNo high system clock required (PLL is able to lock on BCK)

nNo external heat sink required

n5 V tolerant digital inputs

nSupports dual coil inductor application

nEasy application and limited external components required

2.2DSP features

nDigital parametric 10-band equalizer

nDigital volume control per channel

nSelectable +24 dB gain boost

nAnalog interface to digital volume control in Legacy mode

nDigital clip level control

nSoft and hard mute

nThermal foldback threshold temperature control

nDe-emphasis

nOutput power limiting control

nPolarity switch

nFour Pulse Width Modulation (PWM) switching frequency settings

2.3Audio data input interface format support

nMaster or slave Master Clock (MCLK), Bit Clock (BCK) and Word Select (WS) signals

nPhilips I2S, standard I2S

nJapanese I2S, Most Significant Bit (MSB) justified

nSony I2S, Least Significant Bit (LSB) justified

nSample rates from 8 kHz to 192 kHz

3.Applications

nDigital-in Class-D audio amplifier applications

nCRT and flat-panel television sets

nFlat-panel monitors

nMultimedia systems

nWireless speakers

nDocking stations for MP3 players

TFA9812_2

© NXP B.V. 2009. All rights reserved.

Preliminary data sheet

Rev. 02 — 22 January 2009

2 of 66

NXP Semiconductors

TFA9812

 

BTL stereo Class-D audio amplifier with I 2S input

4. Quick reference data

Table 1. Quick reference table

Unless specified otherwise, VDDA = VDDP = 12 V, VSSP1 = VSSP2 = 0 V, VDDA(3V3) = VDDD(3V3) = 3.3 V, VSS1 = VSS2 = REFD = REFA = 0 V, Tamb = 25 °C, RL = 8 Ω, fi = 1 kHz, fs = 44.1 kHz, fsw = 400 kHz, 24-bit I2S input data, MCLK clock mode, typical application diagram (Figure 13).

Symbol

Parameter

Conditions

 

Min

Typ

Max

Unit

General

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDA

analog supply

 

 

8

12

20

V

 

voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDP

power supply

 

 

8

12

20

V

 

voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDA(3V3)

analog supply

 

 

3.0

3.3

3.6

V

 

voltage (3.3 V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDD(3V3)

digital supply

 

 

3.0

3.3

3.6

V

 

voltage (3.3 V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IP

supply current

soft mute mode, with load,

[1]

-

38

45

mA

 

 

 

filter and snubbers

 

 

 

 

 

 

 

connected

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

sleep mode

[1]

-

160

270

μA

 

 

 

 

 

 

 

 

 

 

 

IDDA(3V3)

analog supply

operating mode

 

 

 

 

 

 

current (3.3 V)

 

 

 

 

 

 

 

I2S slave mode

 

-

2

4

mA

 

 

I2S master mode

 

-

4

6

mA

 

 

sleep mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDA = VDDP = 12 V

 

-

120

-

μA

 

 

VDDA = VDDP = 1 V

 

-

40

70

μA

IDDD(3V3)

digital supply

operating mode

 

 

 

 

 

 

current (3.3 V)

 

 

 

 

 

 

 

I2S slave mode

 

-

15

25

mA

 

 

I2S master mode

 

-

25

40

mA

 

 

sleep mode;

 

-

4

30

μA

 

 

DATA = WS = BCK =

 

 

 

 

 

 

 

MCLK = 0 V

 

 

 

 

 

 

 

 

Po(RMS)

RMS output power

Continuous time output power per channel; THD = 10 %;

 

 

RL = 8 Ω

 

 

 

 

 

 

 

VDDA = VDDP = 12 V

 

-

8.3

-

W

 

 

VDDA = VDDP = 13.5 V

 

-

10

-

W

 

 

VDDA = VDDP = 15 V

 

-

12

-

W

 

 

Short time (10 s) output power per channel; THD = 10 %;

 

 

RL = 8 Ω

 

 

 

 

 

 

 

VDDA = VDDP = 17 V

 

-

15

-

W

ηpo

output power

RL = 8 Ω; Po(RMS) = 8.3 W

 

-

88

-

%

 

efficiency

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[1]IP is the current through the analog supply voltage (VDDA) pin added to the current through the power supply voltage (VDDP) pin.

TFA9812_2

© NXP B.V. 2009. All rights reserved.

Preliminary data sheet

Rev. 02 — 22 January 2009

3 of 66

NXP Semiconductors

 

TFA9812

 

 

BTL stereo Class-D audio amplifier with I 2S input

5. Ordering information

 

 

 

 

Table 2. Ordering information

 

 

 

 

 

 

Type number

Package

 

 

 

Name

Description

Version

TFA9812HN

HVQFN48

plastic thermal enhanced very thin quad flat package; no leads;

SOT619-8

 

 

48 terminals; body 7 × 7 × 0.85 mm

 

 

 

 

 

TFA9812_2

© NXP B.V. 2009. All rights reserved.

Preliminary data sheet

Rev. 02 — 22 January 2009

4 of 66

sheet data Preliminary

2009 January 22 — 02 .Rev

66 of 5

2 TFA9812

6. Block diagram

 

 

 

 

TEST1

 

TEST2

 

 

 

AVOL

 

 

VDDD(3V3)

VDDA(3V3)

VDDA

 

 

 

 

 

 

 

 

 

7

 

43

 

 

 

32

 

 

 

40

 

3

6

 

 

 

 

15

BOOT1P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18, 19

VDDP

 

 

 

PHASED

 

 

 

REGISTER

ADC

 

 

 

 

 

 

 

 

 

DRIVER

 

 

 

 

 

LOCKED

 

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH

 

 

 

 

 

LOOP

 

 

 

HEX 01

 

 

 

 

 

TFA9812

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16, 17

OUT1P

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTALIN

1

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

DRIVER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW

10, 11

VSSP2

 

XTALOUT

2

OSCILLATOR

 

PROTECTION

1

 

0

CSEL

 

 

 

 

 

 

 

 

 

 

LP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PWM

 

 

 

STAB1

 

 

 

 

 

 

 

UFP

 

 

 

 

 

 

 

 

 

 

 

 

 

25

BOOT1N

 

MCLK

47

 

 

 

 

 

 

 

 

 

 

 

 

CONTROLLER

 

 

 

 

 

 

OFP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDP

 

 

 

 

 

 

IBP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

THERMAL

 

 

 

 

 

 

DRIVER

 

 

 

 

 

 

 

 

 

 

 

 

FOLDBACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23, 24

OUT1N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRIVER

 

 

 

BCK 46

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW

26, 27

VSSP1

 

 

 

 

 

VOLUME

 

INTER-

 

 

 

 

 

 

 

 

 

 

 

 

WS 45

SERIAL

 

10-BAND

 

 

 

 

 

 

 

 

 

 

 

 

 

28

STAB1

 

 

CONTROL

 

POLATION

GAIN

POWER

 

 

 

 

 

 

 

 

AUDIO

PARAMETRIC

 

 

 

 

 

 

 

 

 

 

 

AND SOFT

 

 

 

LIMITER

 

 

 

 

 

 

 

 

DATA 44

INTERFACE

 

EQUALIZER

 

FILTER AND

 

 

 

 

 

 

22

BOOT2P

 

 

 

MUTE

DE-EMPHASIS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRIVER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH

20, 21

OUT2P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRIVER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW

VSSP2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

POWERUP

31

 

 

 

 

 

 

 

 

 

 

 

 

 

PWM

 

 

 

STAB2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROLLER

 

 

 

12

BOOT2N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENABLE

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GAIN

34

 

 

PROTECTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CSEL

35

 

 

 

 

 

 

 

 

 

 

 

 

 

DRIVER

 

 

 

 

 

OVP

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13, 14

OUT2N

 

ADSEL2/PLIM2

36

CONTROL

 

UVP

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

INTERFACE

OCP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADSEL1/PLIM1

37

 

 

 

 

 

REFERENCES

 

 

LOGIC

 

 

 

 

 

 

 

 

 

OTP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCL/SFOR

38

 

 

 

 

 

 

 

 

 

 

 

 

DRIVER

 

 

 

 

 

ODP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW

VSSP2

 

 

 

 

 

 

WP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

©

SDA/MS

39

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

STAB2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.B NXP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29

 

30

41

 

42

 

4

 

5

 

 

8

 

48

 

 

2009 .V

 

 

 

 

DIAG

 

CDELAY

STABD

 

REFD

STABA

REFA

EXPOSED DIE PADDLE

V

SS1

V

SS2

 

010aaa217

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rights All

Fig 1. TFA9812 block diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Semiconductors NXP

I with amplifier audio D-Class stereo BTL

TFA9812

inputS

2

 

NXP Semiconductors

TFA9812

 

BTL stereo Class-D audio amplifier with I 2S input

Figure 1 shows the block diagram of the TFA9812. For a detailed description of the audio signal path see Section 8.1.

7.Pinning information

7.1Pinning

 

V

MCLK

BCK

WS

DATA

TEST2

REFD

STABD

V

SDA/MS

SCL/SFOR

ADSEL1/PLIM1

terminal 1

SS2

 

 

 

 

 

 

 

DDD(3V3)

 

 

 

index area

48

47

46

45

44

43

42

41

40

39

38

37

 

XTALIN

1

 

 

 

 

 

 

 

 

 

 

 

XTALOUT

2

 

 

 

 

 

 

 

 

 

 

 

VDDA(3V3)

3

 

 

 

 

 

 

 

 

 

 

 

STABA

4

 

 

 

 

 

 

 

 

 

 

 

REFA

5

 

 

 

 

 

 

 

 

 

 

 

VDDA

6

 

 

 

TFA9812HN

 

 

 

 

TEST1

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS1

8

 

 

 

 

 

 

 

 

 

 

 

STAB2

9

 

 

 

 

 

 

 

 

 

 

 

VSSP2

10

 

 

 

 

 

 

 

 

 

 

 

VSSP2

11

 

 

 

 

 

 

 

 

 

 

 

BOOT2N

12

 

 

 

 

 

 

 

 

 

 

 

 

13

14

15

16

17

18

19

20

21

22

23

24

 

OUT2N

OUT2N

BOOT1P

OUT2P

OUT1P

DDP

DDP

OUT1P

OUT1P

BOOT1P

OUT1N

OUT1N

 

V

V

Transparent top view

Fig 2. Pin configuration, transparent top view

36

ADSEL2/PLIM2

35

CSEL

34

GAIN

33

ENABLE

32

AVOL

31

POWERUP

30

CDELAY

29

DIAG

28

STAB1

27

VSSP1

26

VSSP1

25

BOOT1N

 

010aaa218

 

Table 3.

Pinning description TFA9812

 

Pin

Symbol

Type

Description

1

XTALIN

I

Crystal oscillator input

 

 

 

 

 

2

XTALOUT

O

Crystal oscillator output

 

 

 

 

 

 

3

VDDA(3V3)

P

Analog supply voltage (3.3 V)

4

STABA

O

1.8 V analog stabilizer output

 

 

 

 

 

5

REFA

P

Analog reference voltage

 

 

 

 

 

 

6

VDDA

P

Analog supply voltage (8 V to 20 V)

 

7

TEST1

I

Test signal input 1. For test purposes only (connect to VSS)

 

8

VSS1

P

PCB ground reference

9

STAB2

O

Decoupling of internal 11 V regulator for channel 2 drivers

 

 

 

 

 

 

10

VSSP2

P

Negative power supply voltage for channel 1 and channel 2

 

11

VSSP2

P

Negative power supply voltage for channel 1 and channel 2

12

BOOT2N

O

Bootstrap high-side driver negative PWM output channel 2

 

 

 

 

 

13

OUT2N

O

Negative PWM output channel 2

TFA9812_2

 

 

© NXP B.V. 2009. All rights reserved.

Preliminary data sheet

Rev. 02 — 22 January 2009

6 of 66

NXP Semiconductors

 

 

TFA9812

 

 

 

 

BTL stereo Class-D audio amplifier with I 2S input

 

Table 3.

Pinning description TFA9812 …continued

 

 

 

 

 

 

Pin

Symbol

Type

Description

14

OUT2N

O

Negative PWM output channel 2

 

 

 

 

 

15

BOOT1P

O

Bootstrap high-side driver positive PWM output channel 1

 

 

 

 

 

16

OUT1P

O

Positive PWM output channel 1

 

 

 

 

 

17

OUT1P

O

Positive PWM output channel 1

 

 

 

 

 

 

18

VDDP

P

Positive power supply voltage (8 V to 20 V)

 

19

VDDP

P

Positive power supply voltage (8 V to 20 V)

20

OUT2P

O

Positive PWM output channel 2

 

 

 

 

 

21

OUT2P

O

Positive PWM output channel 2

 

 

 

 

 

22

BOOT2P

O

Bootstrap high-side driver positive PWM output channel 2

 

 

 

 

 

23

OUT1N

O

Negative PWM output channel 1

 

 

 

 

 

24

OUT1N

O

Negative PWM output channel 1

 

 

 

 

 

25

BOOT1N

O

Bootstrap high-side driver negative PWM output channel 1

 

 

 

 

 

 

26

VSSP1

P

Negative power supply voltage for channel 1 and channel 2

 

27

VSSP1

P

Negative power supply voltage for channel 1 and channel 2

28

STAB1

O

Decoupling of internal 11 V regulator for channel 1 drivers

 

 

 

 

 

29

DIAG

O

Fault mode indication output (open-drain pin)

 

 

 

 

 

30

CDELAY

I

Timing reference

 

 

 

 

 

31

POWERUP

I

Power-up pin to switch between Sleep and other operational

 

 

 

 

modes

 

 

 

 

 

32

AVOL

I

Analog volume control (Legacy mode)

 

 

 

 

 

33

ENABLE

I

Enable input to switch between 3-state and other

 

 

 

 

operational modes

 

 

 

 

 

34

GAIN

I

Gain selection input to select between 0 dB and +24 dB

 

 

 

 

gain (Legacy mode)

 

 

 

 

 

35

CSEL

I

Control selection input to select between Legacy mode

 

 

 

 

(no I2C bus control) and I2C bus control

36

ADSEL2/PLIM2

I

Address selection in I2C mode input 2, power limiter

 

 

 

 

selection input 2 in Legacy mode

 

 

 

 

 

37

ADSEL1/PLIM1

I

Address selection in I2C mode input 1, power limiter

 

 

 

 

selection input 1 in Legacy mode

 

 

 

 

 

38

SCL/SFOR

I

I2C bus clock input in I2C mode, I2S serial data format

 

 

 

 

selection input in Legacy mode

 

 

 

 

 

39

SDA/MS

I/O

I2C bus data input and output in I2C mode, master/slave

 

 

 

 

selection input in Legacy mode

 

 

 

 

 

 

40

VDDD(3V3)

P

Digital supply voltage (3.3 V)

41

STABD

O

1.8 V digital stabilizer output

 

 

 

 

 

42

REFD

P

Digital reference voltage

 

 

 

 

 

 

43

TEST2

I

Test signal input 2; for test purposes only (connect to VSS)

 

44

DATA

I

I2S bus data input

45

WS

I/O

I2S bus word select input (I2S slave mode) or output (I2S

 

 

 

 

master mode)

 

 

 

 

 

46

BCK

I/O

I2S bus bit clock input (I2S slave mode) or output (I2S

 

 

 

 

master mode)

TFA9812_2

 

 

© NXP B.V. 2009. All rights reserved.

Preliminary data sheet

Rev. 02 — 22 January 2009

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NXP Semiconductors

 

 

TFA9812

 

 

 

 

BTL stereo Class-D audio amplifier with I 2S input

 

Table 3.

Pinning description TFA9812 …continued

 

 

 

 

 

 

Pin

Symbol

Type

Description

47

MCLK

I/O

Master clock input (I2S slave mode) or output (I2S master

 

 

 

 

mode)

 

 

 

 

 

48

VSS2

P

PCB ground reference

 

Exposed

-

P

PCB ground reference

 

die-paddle

 

 

 

 

 

 

 

 

8.Functional description

8.1General

The TFA9812 is a high-efficiency stereo BTL Class-D amplifier with a digital I2S audio input. It supports all commonly used I2S formats.

Figure 1 shows the functional block diagram, which includes the key function blocks of the TFA9812. In the digital domain the audio signal is processed and converted to a pulse width modulated signal using BD modulation. A BTL configured power comparator carries out power amplification.

The audio signal processing path is as follows:

1.The Digital Audio Input (DAI) block translates the I2S (-like) input signal into a standard internal stereo audio stream.

2.The 10-band parametric equalizer can optionally equalize the stereo audio stream. Both channels have separate equalization streams. It can be used for speaker transfer curve compensation to optimize the audio performance of applied speakers.

3.Volume control in the TFA9812 is done by attenuation. The attenuation depends on the volume control settings and the thermal foldback value. Soft mute is also arranged at this part. In Legacy mode the volume control is done by an on-board Analog-to-Digital Converter (ADC) which measures the analog voltage on pin 32.

4.The interpolation filter interpolates from 1 fs to the PWM controller sample rate (2048 fs at 44.1 kHz) by cascading FIR filters.

5.The gain block can boost the signal with 0 dB or +24 dB. Four specific gain settings are also provided in this block. These specific gain settings are related to maximum clip levels of < 0.5 %, 10 %, 20 % or 30 % THD at the TFA9812 output. These maximum clip levels are only valid with the gain boost set to 0 dB and a 0 dBFS input signal.

6.The power limiter limits the maximum output signal of the TFA9812. The power limiter settings are 0 dB, 1.5 dB, 3 dB, and 4.5 dB. This function can be used to reduce the maximum output power delivered to the speakers at a fixed supply voltage and speaker impedance.

7.The PWM controller block transforms the audio signal into a BD-modulated PWM signal. The BD-modulation provides a high signal-to-noise performance and eliminates clock jitter noise.

8.Via four differential comparators the PWM signals are amplified by two BTL power output stages. By default the left audio signal is connected to channel 1 and the right audio signal to channel 2.

TFA9812_2

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Preliminary data sheet

Rev. 02 — 22 January 2009

8 of 66

NXP Semiconductors

TFA9812

 

BTL stereo Class-D audio amplifier with I 2S input

The block control defines the operational control settings of the TFA9812 in line with the actual I2C settings and the pin-controlled settings.

The PLL block creates the system clock and can take the I2S BCK, the MCLK or an external crystal as reference source.

The following protections are built into the TFA9812:

Thermal Foldback (TF)

OverTemperature Protection (OTP)

OverCurrent Protection (OCP)

OverVoltage Protection (OVP)

UnderVoltage Protection (UVP)

Window Protection (WP)

Lock Protection (LP)

UnderFrequency Protection (UFP)

OverFrequency Protection (OFP)

Invalid BCK Protection (IBP)

DC-blocking

ElectroStatic Discharge (ESD)

8.2Functional modes

8.2.1Control modes

The two control modes of the TFA9812 are I2C and legacy.

In I2C mode the I2C format control is enabled.

In Legacy mode a pin-based subset of the control options is available. The control settings for features which are not available in Legacy mode are set to the default I2C register settings.

The control mode is selected via pin CSEL as shown in Table 4.

Table 4. Control mode selection

CSEL Pin value

Control mode

0

Legacy (no I2C)

1

I2C

In the functional descriptions below the control for the various functions will be described for each control mode. Section 9.6 summarizes the support given by each control mode for the various TFA9812 functions.

8.2.2Key operating modes

There are six key operating modes:

In Sleep mode the voltage supplies are present, but power consumption for the whole device is reduced to the minimum level. The output stages in Sleep mode are 3-state and I2C communication is disabled.

TFA9812_2

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Preliminary data sheet

Rev. 02 — 22 January 2009

9 of 66

NXP Semiconductors

TFA9812

 

BTL stereo Class-D audio amplifier with I 2S input

In Soft mute mode the I2S input signal is overruled with a soft mute.

In Legacy control mode the analog input pin AVOL controls Soft mute mode.

In I2C control mode I2C control can be used to enable an automatic soft mute function. See also Section 8.5.3.

In Hard mute mode the PWM controller is overruled with a 50 % duty cycle square pulse. The Hard mute mode is only available in I2C control mode.

In Operating mode the TFA9812 amplifies the I2S audio input signal in line with the actual control setting.

In 3-state mode the output stages are switched off.

Fault mode is entered when a fault condition is detected by one or more of the protection mechanisms implemented in the TFA9812. In Fault mode the actual device configuration depends on the fault detected: see Section 8.7 for more information. Fault mode is for a subset of the faults flagged on the DIAG output pin. When the DIAG pin is flagged the output stages will be forced to enter 3-state mode. In Sleep mode the DIAG pin will not flag fault modes.

Table 5.

Operational mode selection

 

 

 

 

 

 

Pin:

 

 

 

DIAG Output

Operational mode

 

 

 

 

 

selected:

POWERUP

ENABLE

CSEL

AVOL

 

 

 

 

 

 

0

-

-

-

floating

Sleep mode

 

 

 

 

 

 

1

-

-

-

0 / floating

Fault mode (enabled by

 

 

 

 

 

system)

[1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

-

floating

Soft mute mode (in I2C

 

 

 

 

 

control mode)

[2]

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

0

< 0.8 V

floating

Soft mute (in Legacy control

 

 

 

 

 

mode)

 

 

 

 

 

 

1

0

-

-

floating

3-state mode

 

 

 

 

 

 

1

1

-

-

floating

Operational mode

 

 

 

 

 

 

 

 

 

 

[1]Clocking faults do not trigger DIAG output.

[2]Under these conditions soft mute still has to be enabled by the appropriate I2C setting.

8.2.3I2S master/slave modes and MCLK/BCK clock modes

The I2S interface can be set in master or in slave.

In I2S master mode the PLL locks to the output signal of the internal crystal oscillator circuit which uses an external crystal. The BCK, WS and MCLK signals are generated by the TFA9812. On the MCLK pin the TFA9812 delivers a master clock running at the crystal frequency.

In I2S slave mode the PLL can lock to:

The external MCLK signal on the MCLK pin called MCLK clock mode.

The I2S input BCK signal on the BCK pin called BCK clock mode.

The I2S master or slave mode can be selected:

In I2C control mode by selecting the right I2C setting.

In legacy control mode by selecting the right setting on the SDA/MS pin.

TFA9812_2

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Preliminary data sheet

Rev. 02 — 22 January 2009

10 of 66

NXP Semiconductors

 

 

TFA9812

 

 

 

BTL stereo Class-D audio amplifier with I 2S input

 

Table 6. I2S master/slave mode selection

 

 

 

 

Pin value

 

Clock mode

I2S mode

 

CSEL

SDA/MS

 

 

 

 

0

0

legacy

slave

 

 

 

 

 

0

1

legacy

master

 

 

 

 

 

 

 

 

1

-

I2C

slave or master

[1]

 

 

[1]Under these conditions the mode is enabled by the appropriate I2C setting.

In I2S slave mode selection between BCK and MCLK clock modes is automatic.

MCLK clock mode is given higher priority than BCK. If the MCLK clock is judged valid by the protection circuit then MCLK clock mode is enabled. BCK clock mode is enabled when the MCLK clock is invalid (e.g. not available) and the BCK clock is judged valid by the protection circuit (see Section 8.7.11).

Table 7 shows the supported crystal frequencies in I2S master mode.

Table 8 shows the supported MCLK frequencies in MCLK mode (I2S slave mode).

Table 9 shows the supported BCK frequencies in BCK mode (I2S slave mode).

Table 7.

Valid crystal frequencies in I2S master mode

 

Control mode

fs (kHz)

Crystal frequency (MHz)

I2C

 

8, 16, 32, 64, 128

8.192

 

 

11.025, 22.05, 44.1, 88.2,

11.2896

 

 

176.4

 

 

 

 

 

 

 

12, 24, 48, 96, 192

12.288

 

 

 

 

Legacy

 

32

8.192

 

 

 

 

 

 

44.1

11.2896

 

 

 

 

 

 

48

12.288

 

 

 

Table 8.

Valid MCLK frequencies in I2S slave mode

 

Control mode

fs (kHz)

MLCK frequency (MHz)

I2C

 

8, 16, 32, 64, 128

8.192

 

 

 

12.288

 

 

 

 

 

 

32

18.432 (576 fs)

 

 

11.025, 22.05, 44.1, 88.2,

11.2896

 

 

176.4

 

 

 

16.9344

 

 

 

 

 

 

 

 

 

44.1

25.4016 (576 fs)

 

 

12, 24, 48, 96, 192

12.288

 

 

 

 

 

 

 

18.432

 

 

 

 

 

 

48

27.648 (576 fs)

TFA9812_2

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Preliminary data sheet

Rev. 02 — 22 January 2009

11 of 66

NXP Semiconductors

 

 

 

 

TFA9812

 

 

 

BTL stereo Class-D audio amplifier with I 2S input

 

Table 8.

Valid MCLK frequencies in I2S slave mode

 

 

Control mode

fs (kHz)

MLCK frequency (MHz)

 

Legacy

 

32

 

 

8.192

 

 

 

 

 

 

 

 

 

 

 

 

 

12.288

 

 

 

 

 

 

 

 

 

 

 

 

 

18.432 (576 fs)

 

 

 

44.1

 

 

11.2896

 

 

 

 

 

 

 

 

 

 

 

 

 

16.9344

 

 

 

 

 

 

 

 

 

 

 

 

 

25.4016 (576 fs)

 

 

 

48

 

 

12.288

 

 

 

 

 

 

 

 

 

 

 

 

 

18.432

 

 

 

 

 

 

 

 

 

 

 

 

 

27.648 (576 fs)

 

Table 9.

Valid BCK frequencies in I2S slave mode

 

 

Control mode

fs (kHz)

BCK (x fs input)

 

I2C

 

8 to 192

[1]

 

32 fs

 

 

 

 

 

 

8 to 192

[1]

 

48 fs

 

 

 

 

 

 

 

8 to 192

[1]

 

64 fs

 

 

 

 

 

Legacy

 

32, 44.1, 48

32 fs

 

 

 

32, 44.1, 48

48 fs

 

 

 

32, 44.1, 48

64 fs

[1]The valid sample frequencies are shown in Section 9.5.7.

TFA9812_2

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Preliminary data sheet

Rev. 02 — 22 January 2009

12 of 66

NXP Semiconductors

TFA9812

 

BTL stereo Class-D audio amplifier with I 2S input

8.3 Power-up/power-down

 

 

 

external

 

 

 

voltage

 

 

 

supplies

 

 

 

POWERUP

 

 

 

 

pin

 

 

 

ENABLE

 

 

 

 

pin

 

 

 

 

I2C

 

 

 

available

 

 

 

soft mute

 

 

 

setting in

 

 

 

I2C mode

 

 

 

AVOL pin

 

 

 

in Legacy

 

 

 

 

mode

 

 

 

 

PWM

 

 

 

outputs

 

 

 

Operating

 

 

 

mode active

 

 

 

 

twake

td(on)

td(mute_off)

td(soft_mute)

 

 

 

 

010aaa219

Fig 3.

Power-up/power-down timing

 

 

8.3.1Power-up

Figure 3 and Table 10 describe the power-up timing while Table 11 shows the pin control for initiating a power-up reset.

Table 10. Power-up/power-down timing

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

twake

wake-up

I2C control

-

4

-

ms

 

time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

td(on)

turn-on

-

 

 

70

-

135

ms

 

delay time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

td(mute_off)

mute off

-

 

 

-

-

128/fs

s

 

delay time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

td(soft_mute)

Soft mute

I2C control

-

-

128/fs

s

 

delay time

 

 

 

 

 

 

 

 

legacy

-

15

-

ms

 

 

 

 

control

[1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[1]Mute in Legacy mode is controlled by AVOL pin.

TFA9812_2

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Preliminary data sheet

Rev. 02 — 22 January 2009

13 of 66

NXP Semiconductors

TFA9812

 

BTL stereo Class-D audio amplifier with I 2S input

In I2C control mode communication is enabled after 4 ms. The preferred I2C settings can be made within 66 ms before the PLL starts running. Finally, the output stages are enabled and the audio level is increased via a demute sequence if mute has previously been disabled.

Remark: In I2C mode soft mute is enabled by default. It can be disabled at any time while I2C communication is valid. In order to prevent audio clicks volume control (default setting is 0 dB) should be set before soft mute is disabled.

Remark: For a proper start-up in I2S master mode and I2C mode the following sequence should be followed:

1.The I2S master setting should be set and keep the default sample rate setting active.

2.Next, another sample rate setting than the default one should be selected.

3.Finally, when the default sample rate is used the default sample rate setting should be selected again.

8.3.2Power-down

Figure 3 includes the power-down timing while Table 11 shows the pin control for enabling power-down.

Table 11. Power-up/power-down selection

Power-up pin

Description

value

 

 

 

0

Power-down (Sleep mode)

 

 

1

Power-up

 

 

Putting the TFA9812 into power-down is equivalent to enabling Sleep mode

(see Section 8.2.2). This mode is entered immediately and no additional clock cycles are required.

In order to prevent audible clicks, soft mute should be enabled at least Td(soft_mute) seconds before enabling Sleep mode.

The specified low current and power conditions in Table 1 are valid within 10 μs after enabling Sleep mode.

8.4Digital audio data input

8.4.1Digital audio data format support

The TFA9812 supports a commonly used range of I2S and I2S-like digital audio data input formats. These are listed in Table 12.

Table 12. Supported digital audio data formats

 

BCK frequency

Interface format (MSB first)

Supported in I2C

Supported in Legacy

 

 

 

control mode

control mode

 

 

 

 

 

 

32 fs

I2S up to 16-bit data

yes

yes

 

32 fs

MSB-justified 16-bit data

yes

yes

 

32 fs

LSB-justified 16-bit data

yes

yes

 

48 fs

I2S up to 24-bit data

yes

yes

 

48 fs

MSB-justified up to 24-bit data

yes

yes

TFA9812_2

 

 

© NXP B.V. 2009. All rights reserved.

Preliminary data sheet

Rev. 02 — 22 January 2009

14 of 66

NXP Semiconductors

 

 

TFA9812

 

 

BTL stereo Class-D audio amplifier with I 2S input

 

Table 12. Supported digital audio data formats

 

 

 

 

 

 

 

 

BCK frequency

Interface format (MSB first)

Supported in I2C

Supported in Legacy

 

 

 

control mode

control mode

 

 

 

 

 

 

48 fs

LSB-justified 16-bit data

yes

no

 

48 fs

LSB-justified 18-bit data

yes

no

 

48 fs

LSB-justified 20-bit data

yes

no

 

48 fs

LSB-justified 24-bit data

yes

yes

 

64 fs

I2S up to 24-bit data

yes

yes

 

64 fs

MSB-justified up to 24-bit data

yes

yes

 

64 fs

LSB-justified 16-bit data

yes

no

 

64 fs

LSB-justified 18-bit data

yes

no

 

64 fs

LSB-justified 20-bit data

yes

no

 

64 fs

LSB-justified 24-bit data

yes

no

Remark: Only MSB-first formats are supported.

WS

 

 

LEFT

 

 

 

 

 

 

 

 

RIGHT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

3

 

 

 

 

1

 

2

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

MSB

B2

 

 

 

 

 

 

MSB

B2

 

 

MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2S-BUS FORMAT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WS

 

 

LEFT

 

 

 

 

 

 

 

 

RIGHT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

3

 

 

 

 

 

 

 

1

2

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

MSB

B2

 

 

 

 

 

LSB

MSB

B2

 

 

LSB

MSB

B2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB-JUSTIFIED FORMAT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WS

 

 

 

 

 

 

LEFT

 

 

 

 

 

 

 

 

 

 

 

 

RIGHT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

15

2

1

 

 

 

 

 

 

 

 

 

16

15

2

1

BCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

 

 

 

 

MSB

B2

B15

LSB

 

 

 

 

 

 

 

 

 

MSB

B2

B15

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB-JUSTIFIED FORMAT 16 BITS

 

 

 

 

 

 

 

 

 

 

 

 

WS

 

 

 

 

 

 

LEFT

 

 

 

 

 

 

 

 

 

 

 

 

RIGHT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

17

16

15

2

1

 

 

 

 

 

 

 

18

17

16

15

2

1

BCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

MSB

B2

B3

B4

B17

LSB

 

 

 

 

 

 

 

MSB

B2

B3

B4

B17

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB-JUSTIFIED FORMAT 18 BITS

 

 

 

 

 

 

 

 

 

 

 

 

WS

 

 

 

 

 

 

LEFT

 

 

 

 

 

 

 

 

 

 

 

 

RIGHT

 

 

 

 

 

 

 

 

 

 

 

 

 

20

19

 

18

17

16

15

2

1

 

 

 

 

 

20

19

18

17

16

15

2

1

BCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

MSB

B2

B3

B4

B5

B6

B19

LSB

 

 

 

 

 

MSB

B2

B3

B4

B5

B6

B19

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB-JUSTIFIED FORMAT 20 BITS

 

 

 

 

 

 

 

 

 

 

 

 

WS

 

 

 

 

 

 

LEFT

 

 

 

 

 

 

 

 

 

 

 

 

RIGHT

 

 

 

 

 

 

 

 

 

24

23

22

21

20

19

 

18

17

16

15

2

1

 

24

23

22

21

20

19

18

17

16

15

2

1

BCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

MSB

B2

B3

B4

B5

B6

B7

B8

B9

B10

B23

LSB

MSB

B2

B3

B4

B5

B6

B7

B8

B9

B10

B23

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB-JUSTIFIED FORMAT 24 BITS

 

 

 

 

 

 

 

 

 

 

010aaa458

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fig 4.

Serial interface input and output formats

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TFA9812_2

© NXP B.V. 2009. All rights reserved.

Preliminary data sheet

Rev. 02 — 22 January 2009

15 of 66

NXP Semiconductors

TFA9812

 

BTL stereo Class-D audio amplifier with I 2S input

In I2C control mode the following sample frequency fs can be used: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz, 176.4 kHz or 192 kHz. The I2C control for fs selection can be found in

Section 9.5.7.

In Legacy control mode the following sample frequencies (fs) can be used: 32 kHz,

44.1 kHz or 48 kHz.

8.4.2Digital audio data format control

The BCK-to-WS and MCLK-to-WS frequency ratios are automatically detected, so no control settings need to be configured for these.

In I2C control mode all the formats listed in Table 12 are supported. The appropriate I2C controls for selecting the supported formats can be found in Section 9. In the Legacy control mode only a subset of the supported formats can be used. These are shown in Table 12 and the required pin control is given in Table 13.

See Section 8.2.1 for details of how to enable Legacy control mode.

Table 13. Digital audio data format selection in Legacy control mode

SCL/SFOR pin value

Interface formats (MSB-first)

0

I2S

1

MSB-justified

 

 

8.5Digital signal-processing features

8.5.1Equalizer

8.5.1.1Equalizer options

The equalizer function can be bypassed and the equalizer can be configured to either a 5-band or 10-band function. These settings are for both audio channels simultaneously.

There are 20 bands in the equalizer. These are distributed as follows:

Bands A1 to A5 are bands 1 to 5 of output 1 (used in 5-band and 10-band configuration).

Bands B1 to B5 are bands 1 to 5 of output 2 (used in 5-band and 10-band configuration).

Bands C1 to C5 are bands 6 to 10 of output 1 (used in 10-band configuration only).

Bands D1 to D5 are bands 6 to 10 of output 2 (used in 10-band configuration only).

In I2C control mode each band can be configured separately using I2C register settings.

In Legacy control mode the equalizer is bypassed.

8.5.1.2Equalizer band function

The shape of each parametric equalizer band is determined by the three filter parameters:

(Relative) center frequency w = 2p( f c ¤ f s ) .

Quality factor Q.

Gain factor G.

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In the above equation fc is the center frequency and fs is the sample frequency.

The definition of the quality factor is the center frequency divided by the 3 dB bandwidth, see Equation 1. In parametric equalizers this is only valid when the gain is set very small (-30 dB).

 

 

f 1:

20

10

æ A f 1ö

= 3dB f c > f 1

 

 

 

log ç--------÷

 

f c

 

 

 

è A f cø

(1)

Q = -----------------;

 

 

 

f 2

f

1

20

10

æ A f 2ö

= 3dB , f 2 > f c

 

 

f 2:

 

log ç--------÷

 

 

 

 

 

è A f cø

 

Each band filter can be programmed to perform a band-suppression (G < 1) or a band-amplification (G > 1) function around the center frequency.

Each band of the TFA9812 equalizer has a second-order Regalia-Mitra all-pass filter structure. The structure is shown in Figure 5.

+

 

½

 

+

 

Y(z)

+

 

X(z) s

K0/2

A(z)

 

 

010aaa406

Fig 5. Regalia filter flow-diagram

The transfer function of this all-pass filter is shown in Equation 2:

H (z) = 1 ¤ 2 × (1 + A(z)) + K 0 ¤ 2 × (1 A(z))

(2)

A(z) is the second-order filter structure. The transfer function of A(z) is shown in

Equation 3:

K

1

+ K 2

× (1 + K 1 ) × Z 1 + Z 2

A(z) = --------------------------------------------------------------------------------

 

 

 

(3)

1 + K 2 × (1 + K 1 ) × Z 1

+ K 1 × Z 2

The relationship between the programmable parameters K0, K1, and K2 and the filter parameters G, w, Q is shown in Equation 4 and Equation 5.

Use Equation 4 to calculate band suppression (G < 1) functions.

K 0 = G

 

K 1 = cos w

(4)

K 2 = (2Q × G sin w) ¤ (2Q × G + sin w)

G < 1

 

Use Equation 5 to calculate band amplification (G ³ 1) functions.

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BTL stereo Class-D audio amplifier with I 2S input

K 0 = G

 

 

 

 

K 1 = cos w

 

(5)

K 2 = (2Q sin w) ¤ (2Q + sin w)

 

G ³ 1

 

 

The ranges of the TFA9812 parametric equalizer settings for each band are:

The Gain, G is from -30 dB to +12 dB.

The center frequency, fc is from 0.0004 * fs to 0.49 * fs.

The quality factor Q is from 0.001 to 8.

Using I2C control, filter coefficients need to be entered for each filter stage to configure it as desired.

Figure 6, Figure 7 and Figure 8 show some of the possible transfer functions of the equalizer bands. The relations are symmetrical for the suppression and amplification functions. A skewing effect can be observed for the higher frequencies.

Different configurations are available for the same filter transfer function, thus allowing optimum numerical noise performance. The binary filter configuration parameters t1 and t2 control the actual configuration and should be chosen according to Equation 6.

t

1 =

0

w<=p ¤ 2

 

æ1

w>p ¤ 2

 

 

 

 

è

 

(6)

 

 

 

æ0

k2>=0

 

t2

 

 

 

= ç1

k2<0

 

 

 

 

è

 

 

A maximum of 12 dB amplification per equalizer stage can be achieved with respect to the input signal. Each band of the equalizer is provided with a -6 dB amplification, so in order to prevent numerical clipping for some filter settings with over 6 dB of amplification, band filters can be scaled by 0 dB or -6 dB. For optimum numerical noise performance steps of -6 dB amplification should be applied to the highest possible sections that are still within scale signal processing safeguards. Band filters can be scaled with the binary parameters listed in Table 14.

Table 14. Equalizer scale factor coding

s

scale factor (dB)

0

0

 

 

1

6

 

 

8.5.1.3Equalizer band control

For compact representation with positive signed parameters, parameters k1’ and k2’ are introduced in Equation 7.

The parameters k0, k1', k2', t1, t2 and s must be combined in two 16-bit control words, word1 and word2, and must fit within the representation given in Table 15. Parameters k1' and k2' are unsigned floating-point representations in Equation 8.

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TFA9812

 

 

 

 

 

 

 

 

BTL stereo Class-D audio amplifier with I 2S input

 

k1¢

æ1 k

1

 

 

t1

= 1

 

 

 

 

 

 

 

= ç

 

 

 

t1

= 0

 

 

 

 

 

 

 

 

è1 + k1

 

 

 

 

 

(7)

 

 

æ1 k

 

 

 

t2

= 0

 

 

 

 

 

 

k2¢

2

 

 

 

 

 

 

 

 

 

= ç

 

 

 

t2

= 1

 

 

 

 

 

 

 

 

è1 + k2

 

 

 

 

 

 

 

kx

= M × 2E

 

M < 1

 

 

 

 

 

 

 

(8)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In Equation 8, M is the unsigned mantissa and E the negative signed exponent. For

 

 

example, in word2 bits [14:8] = [0111 010] represent k2' = (7/2

4

) ´ 2

2

1

.

 

 

 

= 1.09375 10

 

Table 15. Equalizer control word construction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Word

 

 

 

Section

Data

 

 

 

 

 

 

word1

 

 

 

15

 

t1

 

 

 

 

 

 

word1

 

 

 

[14:4]

11 mantissa bits of k1

 

 

 

 

 

 

word1

 

 

 

[3:0]

Four exponent bits of k1

 

 

 

 

 

 

word2

 

 

 

15

 

t2

 

 

 

 

 

 

word2

 

 

 

[14:11]

Four mantissa bits of k2

 

 

 

 

 

 

word2

 

 

 

[10:8]

Three exponents bits of k2

 

 

 

 

 

 

word2

 

 

 

[7:1]

k0

 

 

 

 

 

 

word2

 

 

 

0

 

s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Section 9.5.4 shows the I2C address locations of the controls for various bands of the equalizer.

010aaa222

12

Q1 = 0.27

Gain

(dB)

Q2 = 0.61

8

Q3 = 1.65

4

0

101 102 103 104 105 Frequency (Hz)

Fig 6. Transfer functions for several quality factors Q

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010aaa223

12

Gain

(dB)

8

4

0

102

103

104

105

101

Frequency (Hz)

Fig 7. Transfer functions for several center frequencies fc

010aaa224

12

Gain

(dB)

6

 

 

 

 

0

 

 

 

 

-6

 

 

 

 

-12

102

103

104

105

101

Frequency (Hz)

Fig 8. Transfer functions for several gain factors G

8.5.2Digital volume control

In I2C control mode both audio channels have separate digital volume control. In Legacy control mode the volume control of both channels is common and the volume control setting depends on the supply voltage on the pin AVOL (32).

8-bit volume control is available per channel. This is dB-linear down to 124 dB in steps of 0.5 dB. The last step of the volume control is mute.

Table 16 shows the various settings and their related channel suppression:

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