NXP 74HC595BQ, 74HC595D, 74HC595DB, 74HC595N, 74HC595PW Schematics

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state

Rev. 6 — 12 December 2011 Product data sheet

1. General description

The 74HC595; 74HCT595 are high-speed Si-gate CMOS device s and ar e pin co mpatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7A.

The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The registers have separate clocks.

Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset ( active LOW) for all 8 shif t register st ages. The
storage register has 8 parallel 3-state bus driver output s. Data in the storage register
appears at the output whenever the output enable input (OE

2. Features and benefits

8-bit serial input



 8-bit serial or parallel output
 Storage register with 3-state outputs
 Shift register with direct clear
 100 MHz (typical) shift out frequency
 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V
 Multiple package options
 Specified from 40 C to +85 C and from 40 C to +125 C

3. Applications

Serial-to-parallel data conversion



 Remote control holding register

) is LOW.

NXP Semiconductors

mna554

3-STATE OUTPUTS

8-BIT STORAGE REGISTER

8-STAGE SHIFT REGISTER

Q

0

Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q7S

14

151234567

9

D

S

SHCP

STCP

OE

11
10

12

13

MR

4. Ordering information

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches;

3-state

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC595N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT595N
74HC595D 40 C to +125 C SO16 plastic small outline package; 16 leads;
74HCT595D

body width 3.9 mm

74HC595DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
74HCT595DB

body width 5.3 mm

74HC595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
74HCT595PW

body width 4.4 mm

74HC595BQ 40C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
74HCT595BQ

very thin quad flat package; no leads; 16 terminals;
body 2.5  3.5  0.85 mm

SOT109-1

SOT338-1

SOT403-1

SOT763-1

5. Functional diagram

Fig 1. Functional diagram

74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 6 — 12 December 2011 2 of 24

NXP Semiconductors

OEMR

9

15

1
2
3
4
5
6
7

1310

14

11 12

mna552

Q1

Q0

Q2
Q3
Q4
Q5
Q6
Q7

Q7S

D

S

STCP

SHCP

mna553

15

9

1
2
3
4
5
6
7

1D 2D

C1/

10
11

14

C2

12

13

EN3

SRG8

R

3

STAGE 0 STAGES 1 TO 6 STAGE 7

FF0

DCPQ

R

LATCH

DCPQ

FF7

DCPQ

R

LATCH

DCPQ

mna555

DQ

Q

1 Q2 Q3 Q4 Q5 Q6 Q7

Q7S

Q

0

DS

STCP

SHCP

OE

MR

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches;

Fig 2. Logic symbol Fig 3. IEC logic symbol

3-state

Fig 4. Logic diagram

74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 6 — 12 December 2011 3 of 24

NXP Semiconductors

74HC595

74HCT595

Q1 V

CC

Q2 Q0

Q3 DS

Q4 OE

Q5 STCP

Q6 SHCP

Q7 MR

GND Q7S

001aao241

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

74HC595

74HCT595

Q1 V

CC

Q2 Q0
Q3 DS
Q4 OE
Q5 STCP
Q6 SHCP
Q7 MR

GND Q7S

001aao242

1
2
3
4
5
6
7
8

10

9

12
11

14
13

16
15

6. Pinning information

6.1 Pinning

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches;

3-state

Fig 5. Pin configuration DIP16, SO16 Fig 6. Pin configuration SSOP16, TSSOP16

74HC595

74HCT595

terminal 1

index area

2 15

Q2 Q0

3 14

Q3 DS

4

Q4 OE

5 12

Q5 STCP

6 11

Q6 SHCP

7 10

Q7 MR

Transparent top view

Q1
1

GND

8

GND

CC

V
16

13

(1)

9

001aao243

Q7S

(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or

mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.

Fig 7. Pin configuration for DHVQFN16

74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 6 — 12 December 2011 4 of 24

NXP Semiconductors

8-bit serial-in, serial or parallel-out shift register with output latches;

6.2 Pin description

Table 2. Pin description

Symbol Pin Description

Q1 1 parallel data output 1
Q2 2 parallel data output 2
Q3 3 parallel data output 3
Q4 4 parallel data output 4
Q5 5 parallel data output 5
Q6 6 parallel data output 6
Q7 7 parallel data output 7
GND 8 ground (0 V)
Q7S 9 serial data output
MR
SHCP 11 shift register clock input
STCP 12 storage register clock input
OE
DS 14 serial data input
Q0 15 parallel data output 0
V

CC

10 master reset (active LOW)

13 output enable input (active LOW)

16 supply voltage

74HC595; 74HCT595

3-state

7. Functional description

Table 3. Function table

Control Input Output Function
SHCP STCP OE MR DS Q7S Qn

X X L L X L NC a LOW-level on MR
X  L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state
 X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all

X  L H X NC QnS contents of shift register stages (internal QnS) are transferred to

L H X Q6S QnS contents of shift register shifted throug h ; pre vi o us contents of the

[1] H = HIGH voltage state;

L = LOW voltage state;
 = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.

[1]

only affects the shift registers

shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).

the storage register and parallel output stages

shift register is transferred to the storage register and the parallel
output stages

74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 6 — 12 December 2011 5 of 24

NXP Semiconductors

SHCP

DS

STCP

MR

OE

Q0

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches;

3-state

Z-state

Q1

Q6

Q7

Q7S

Z-state

Z-state

Z-state

mna556

Fig 8. Timing diagram

8. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

V
I

IK

I

OK

I

O

I

CC

I

GND

T
P

CC

stg

tot

supply voltage 0.5 +7 V
input clamping current VI < 0.5 V or VI>VCC+ 0.5 V - 20 mA
output clamping current VO< 0.5 V or VO > VCC + 0.5 V - 20 mA
output current VO= 0.5 V to (VCC+0.5V)

supply current - 70 mA
ground current 70 - mA
storage temperature 65 +150 C
total power dissipation

DIP16 package
SO16 package
SSOP16 package
TSSOP16 package
DHVQFN16 package

pin Q7S - 25 mA
pins Qn - 35 mA

[1]

- 750 mW

[2]

- 500 mW

[3]

- 500 mW

[3]

- 500 mW

[4]

- 500 mW

[1] For DIP16 package: P
[2] For SO16 package: P
[3] For SSOP16 and TSSOP16 packages: P
[4] For DHVQFN16 package: P

74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 6 — 12 December 2011 6 of 24

derates linearly with 12 mW/K above 70 C.

tot

derates linearly with 8 mW/K above 70 C.

tot

derates linearly with 5.5 mW/K above 60 C.

tot

derates linearly with 4.5 mW/K above 60 C.

tot

NXP Semiconductors

8-bit serial-in, serial or parallel-out shift register with output latches;

9. Recommended operating conditions

74HC595; 74HCT595

3-state

Table 5. Recommended operating conditions

Symbol Parameter Conditions 74HC595 74HCT595 Unit

Min Typ Max Min Typ Max

V

CC

V

I

V

O

t/V input transition rise and

T

amb

supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
input voltage 0 - V
output voltage 0 - V

= 2.0 V - - 625 - - - ns/V

V

fall rate

CC

= 4.5 V - 1.67 139 - 1.67 139 ns/V

V

CC

= 6.0 V - - 83 - - - ns/V

V

CC

CC
CC

0-VCCV
0-VCCV

ambient temperature 40 +25 +125 40 +25 +125 C

10. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit

74HC595

V

IH

HIGH-level
input voltage

V

IL

LOW-level
input voltage

V

OH

HIGH-level
output voltage

Min Typ Max Min Max

VCC= 2.0 V 1.5 1.2 - 1.5 - V

V

= 4.5 V 3.15 2.4 - 3.15 - V

CC

= 6.0 V 4.2 3.2 - 4.2 - V

V

CC

VCC= 2.0 V - 0.8 0.5 - 0.5 V

= 4.5 V - 2.1 1.35 - 1.35 V

V

CC

= 6.0 V - 2.8 1.8 - 1.8 V

V

CC

VI=VIHor V

IL

all outputs

= 20 A; VCC= 2.0 V 1.9 2.0 - 1.9 - V

I

O

= 20 A; VCC= 4.5 V 4.4 4.5 - 4.4 - V

I

O

= 20 A; VCC= 6.0 V 5.9 6.0 - 5.9 - V

I

O

Q7S output

= 4mA; VCC= 4.5 V 3.84 4.32 - 3.7 - V

I

O

= 5.2 mA; VCC= 6.0 V 5.34 5.81 - 5.2 - V

I

O

Qn bus driver outputs

= 6mA; VCC= 4.5 V 3.84 4.32 - 3.7 - V

I

O

= 7.8 mA; VCC= 6.0 V 5.34 5.81 - 5.2 - V

I

O

74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 6 — 12 December 2011 7 of 24

NXP Semiconductors

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches;

3-state

Table 6. Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max

V

OL

LOW-level
output voltage

VI=VIHor V

IL

all outputs

=20A; VCC= 2.0 V - 0 0.1 - 0.1 V

I

O

=20A; VCC= 4.5 V - 0 0.1 - 0.1 V

I

O

=20A; VCC= 6.0 V - 0 0.1 - 0.1 V

I

O

Q7S output

=4mA; VCC= 4.5 V - 0.15 0.33 - 0.4 V

I

O

=5.2mA; VCC= 6.0 V - 0.16 0.33 - 0.4 V

I

O

Qn bus driver outputs

=6mA; VCC= 4.5 V - 0.15 0.33 - 0.4 V

I

O

=7.8mA; VCC= 6.0 V - 0.16 0.33 - 0.4 V

I

O

I

I

input leakage

VI=VCCor GND; VCC=6.0V - - 1.0 - 1.0 A

current

I

OZ

OFF-state
output current

I

CC

C

I

supply current VI=VCCor GND; IO=0A;

input

VI=VIHor VIL; VCC=6.0V;

VO=VCCor GND

=6.0V

V

CC

--5.0 - 10 A

- - 80 - 160 A

-3.5- - -pF

capacitance

74HCT595

V

IH

HIGH-level

VCC= 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V

input voltage

V

IL

LOW-level

VCC= 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V

input voltage

V

OH

HIGH-level
output voltage

VI=VIHor VIL; VCC=4.5V

all outputs

= 20 A 4.4 4.5 - 4.4 - V

I

O

Q7S output

= 4 mA 3.84 4.32 - 3.7 - V

I

O

Qn bus driver outputs

= 6 mA 3.7 4.32 - 3.7 - V

I

O

V

OL

LOW-level
output voltage

VI=VIHor VIL; VCC=4.5V

all outputs

=20A - 0 0.1 - 0.1 V

I

O

Q7S output

= 4.0 mA - 0.15 0.33 - 0.4 V

I

O

Qn bus driver outputs

= 6.0 mA - 0.16 0.33 - 0.4 V

I

O

I

I

input leakage

VI=VCCor GND; VCC=5.5V - - 1.0 - 1.0 A

current

74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 6 — 12 December 2011 8 of 24