NXP 74HC14BQ, 74HC14D, 74HC14DB, 74HC14N, 74HC14PW Schematics

74HC14; 74HCT14

Hex inverting Schmitt trigger

Rev. 6 — 19 September 2012 Product data sheet

1. General description

The 74HC14; 74HCT14 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.

The 74HC14; 74HCT14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

2. Features and benefits

 Low-power dissipation  ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V  Multiple package options  Specifie d from 40 C to +85 C and from 40 C to +125 C

3. Applications

 Wave and pulse shapers  Astable multivibrators  Monostable multivibrators

NXP Semiconductors

mna204

1A 1Y

1

2

2A 2Y

3

4

3A 3Y

5

6

4A 4Y

9

8

5A 5Y

11

10

6A 6Y

13

12

8

9

10

11

001aac497

12

13

2

1

4

3

6

5

mna025

A

Y

4. Ordering information

74HC14; 74HCT14

Hex inverting Schmitt trigger

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC14N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HCT14N 74HC14D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 74HCT14D

3.9 mm

74HC14DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body 74HCT14DB

width 5.3 mm

74HC14PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; 74HCT14PW

body width 4.4 mm

74HC14BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very 74HCT14BQ

thin quad flat package; no leads; 14 terminals; body 2.5  3 0.85 mm

SOT108-1

SOT337-1

SOT402-1

SOT762-1

5. Functional diagram

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram

(one Schmitt trigger)

Product data sheet Rev. 6 — 19 September 2012 2 of 21

NXP Semiconductors

14

1A V

CC

1Y 6A 2A 6Y 2Y 5A 3A 5Y 3Y 4A

GND 4Y

001aac498

1 2 3 4 5 6 7

8

10

9

12 11

14 13

001aac499

14

GND

(1)

Transparent top view

3Y 4A

3A 5Y

2Y 5A

2A 6Y

1Y 6A

GND

4Y

1A

V

CC

6 9

5 10

4 11

3 12

2 13

7

8

1

14

terminal 1

index area

74HC14; 74HCT14

Hex inverting Schmitt trigger

6. Pinning information

6.1 Pinning

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as a supply pin or input.

Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14

6.2 Pin description

Table 2. Pin description

Symbol Pin Description

1A to 6A 1, 3, 5, 9, 11, 13 data input 1 1Y to 6Y 2, 4, 6, 8, 10, 12 data output 1 GND 7 ground (0 V) V

CC

14 supply voltage

7. Functional description

Table 3. Function table

Input Output nA nY

LH HL

[1] H = HIGH voltage level;

L = LOW voltage level.

[1]

Product data sheet Rev. 6 — 19 September 2012 3 of 21

NXP Semiconductors

8. Limiting values

74HC14; 74HCT14

Hex inverting Schmitt trigger

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

V I

IK

I

OK

I

O

I

CC

I

GND

T P

CC

stg tot

supply voltage 0.5 +7 V input clamping current VI < 0.5 V or VI>VCC+0.5 V output clamping current VO< 0.5 V or VO>VCC+0.5V

[1]

- 20 mA

[1]

- 20 mA output current 0.5 V < VO < VCC+0.5V - 25 mA supply current - 50 mA ground current 50 - mA storage temperature 65 +150 C total power dissipation

[2]

DIP14 package - 750 mW SO14, (T)SSOP14 and

- 500 mW

DHVQFN14 packages

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP14 package: P

For SO14 package: P For (T)SSOP14 packages: P For DHVQFN14 packages: P

derates linearly with 12 mW/K above 70 C.

tot

derates linearly with 8 mW/K above 70 C.

tot

derates linearly with 5.5 mW/K above 60 C.

tot

derates linearly with 4.5 mW/K above 60 C.

tot

9. Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC14 74HCT14 Unit

V

CC

V

I

V

O

T

amb

supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - V output voltage 0 - V ambient temperature 40 +25 +125 40 +25 +125 C

Min Typ Max Min Typ Max

CC CC

0-VCCV 0-VCCV

Product data sheet Rev. 6 — 19 September 2012 4 of 21

NXP Semiconductors

10. Static characteristics

74HC14; 74HCT14

Hex inverting Schmitt trigger

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions T

= 25 C T

amb

to +85 C

Min Typ Max Min Max Min Max

74HC14

V

OH

HIGH-level output voltage

V

OL

LOW-level output voltage

I

input leakage

VI= VT+ or V

T

IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

= 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

I

O

= 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

I

O

= 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

I

O

= 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

I

O

VI= VT+ or V

T

IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

= 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

I

O

= 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

I

O

= 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

I

O

= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

I

O

VI = VCC or GND; VCC=6.0V - - 0.1 - 1.0 - 1.0 A

current

I

CC

C

I

supply current VI = VCC or GND; IO=0A;

=6.0V

V

CC

input

--2.0- 20 - 40A

-3.5- - - - - pF

capacitance

74HCT14

V

OH

HIGH-level output voltage

V

OL

LOW-level output voltage

I

input leakage

VI= VT+ or VT; VCC = 4.5 V

= 20 A 4.4 4.5 - 4.4 - 4.4 - V

I

O

= 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

I

O

VI= VT+ or VT; VCC = 4.5 V

= 20 A; - 0 0.1 - 0.1 - 0.1 V

I

O

= 4.0 mA; - 0.15 0.26 - 0.33 - 0.4 V

I

O

VI = VCC or GND; VCC=5.5V - - 0.1 - 1.0 - 1.0 A

current

I

I

CC

supply current VI=VCCor GND; IO = 0 A;

=5.5V

V

CC

additional supply current

per input pin; VI=VCC 2.1 V; other pins

--2.0- 20 - 40A

- 30 108 - 135 - 147 A

at VCCor GND; IO=0A;

= 4.5 V to 5.5 V

V

CC

C

I

input

-3.5- - - - - pF

capacitance

= 40 C

T

= 40 C

amb

to +125 C

Unit

Product data sheet Rev. 6 — 19 September 2012 5 of 21

NXP Semiconductors

11. Dynamic characteristics

74HC14; 74HCT14

Hex inverting Schmitt trigger

Table 7. Dynamic characteristics

GND = 0 V; CL=50pF; for test circuit see Figure 7.

Symbol Parameter Conditions T

Min Typ Max Max

74HC14

t

pd

propagation delay nA to nY; see Figure 6

[1]

VCC = 2.0 V - 41 125 155 190 ns

= 4.5 V - 15 25 31 38 ns

V

CC

= 5.0 V; CL=15pF - 12 - - - ns

V

CC

= 6.0 V - 12 21 26 32 ns

V

CC

t

transition time see Figure 6

[2]

VCC = 2.0 V - 19 75 95 110 ns

= 4.5 V - 7 15 19 22 ns

V

CC

= 6.0 V - 6 13 15 19 ns

V

CC

C

PD

power dissipation

per package; VI=GNDtoV

CC

[3]

-7- - -pF

capacitance

74HCT14

t

pd

propagation delay nA to nY; see Figure 6

[1]

VCC = 4.5 V - 20 34 43 51 ns

= 5.0 V; CL=15pF - 17 - - - ns

V

CC

t

C

PD

transition time VCC = 4.5 V; see Figure 6 power dissipation

capacitance

per package;

=GNDtoVCC 1.5 V

V

I

[2]

- 7 15 19 22 ns

[3]

-8- - -pF

= 25 C T

amb

= 40 C to

amb

+125 C

(85 C)

Unit

Max

(125 C)

[1] tpd is the same as t

is the same as t

[2] t

t

[3] C

Product data sheet Rev. 6 — 19 September 2012 6 of 21

is used to determine the dynamic power dissipation (PD in W):

PD

P f

i

f

o

C V N = number of inputs switching;

 (C

 V

D=CPD

= input frequency in MHz; = output frequency in MHz;

= output load capacitance in pF;

L

= supply voltage in V;

CC

L

CC

2

 V

 fo) = sum of outputs.

CC

and t

PHL

THL

2

 fi N+ (CL V

and t

TLH

PLH

.

2

 fo) where:

CC

NXP Semiconductors

mna722

t

PLH

t

PHL

V

M

V

M

90 %

10 %

V

M

V

M

nY output

nA input

V

I

GND

V

OH

V

OL

t

TLH

t

THL

001aah768

t

W

t

W

t

r

t

r

t

f

V

M

V

I

negative

pulse

GND

V

I

positive

pulse

GND

10 %

90 %

10 %

V

M

V

M

V

M

t

f

V

CC

DUT

R

T

V

I

V

O

C

L

G

12. Waveforms

Measurement points are given in Table 8.

and VOH are typical voltage output levels that occur with the output load.

V

OL

Fig 6. Input to output propagation delays

74HC14; 74HCT14

Hex inverting Schmitt trigger

Table 8. Measurement points

Type Input Output

V

M

74HC14 0.5V

CC

V

M

0.5V

CC

V

X

0.1V

74HCT14 1.3 V 1.3 V 0.1V

CC CC

V

Y

0.9V

CC CC

Fig 7. Load circuitry for measuring switching times

Product data sheet Rev. 6 — 19 September 2012 7 of 21

Test data is given in Table 9. Definitions test circuit:

= termination resistance should be equal to output impedance Zo of the pulse generator.

R

T

C

= load capacitance including jig and probe capacitance.

L