Numonyx M45PE80 Technical data
8 Mbit, low voltage, Page-Erasable Serial Flash memory
with byte alterability and a 50 MHz SPI bus interface
Features
■ SPI bus compatible serial interface
■ 50 MHz clock rate (maximum)
■ 2.7 V to 3.6 V single supply voltage
■ 8 Mbit of Page-Erasable Flash memory
■ Page size: 256 bytes:
– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)
■ Sector Erase (64 Kbytes)
■ Hardware Write protection of the bottom sector
(64 Kbytes)
■ Electronic signature
– JEDEC standard two-byte signature
(4014h)
■ Deep Power-down mode 1 µA (typical)
■ More than 100 000 Write cycles
■ More than 20 years’ data retention
■ Packages
– ECOPACK® (RoHS compliant)
M45PE80
VFQFPN8 (MP)
6 × 5 mm (MLP8)
SO8W (MW)
208 mils width
SO8N (MN)
150 mils width
December 2007 Rev 9 1/47
www.numonyx.com
1
Contents M45PE80
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S
2.5 Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W
2.7 V
2.8 V
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13
4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Active Power, Stand-by Power and Deep Power-Down modes . . . . . . . . 13
4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/47
M45PE80 Contents
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 22
6.7 Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.9 Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.10 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.12 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3/47
List of tables M45PE80
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Power-Up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. AC characteristics (25 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. AC characteristics (33 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. AC characteristics (50 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17. VFQFPN8 (MLP8)8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, mechanical data. . . . . . . . 42
Table 19. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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M45PE80 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 19
Figure 9. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 20
Figure 10. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 21
Figure 11. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Page Write (PW) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Page Erase (PE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Write Protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 23. Reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 25. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . 42
Figure 26. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 43
5/47
Summary description M45PE80
1 Summary description
The M45PE80 is a 8 Mbit (1 Mbit × 8 bit) Serial Paged Flash Memory accessed by a high
speed SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or
Page Program instruction. The Page Write instruction consists of an integrated Page Erase
cycle followed by a Page Program cycle.
The memory is organized as 16 sectors, each containing 256 pages. Each page is 256
bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1 048
576 bytes.
The memory can be erased a page at a time, using the Page Erase instruction, or a sector
at a time, using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers the M45PE80 in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.
Figure 1. Logic diagram
V
CC
D
C
S
W
Reset
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data Input Input
Q Serial Data Output Output
S Chip Select Input
Write Protect Input
W
Reset Input
Reset
M45PE80
V
SS
Q
AI06810B
V
CC
V
SS
6/47
Supply Voltage
Ground
M45PE80 Summary description
Figure 2. VFQFPN and SO connections
M45PE80
DQ
1
C
2
Reset
3
4
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
8
7
6
5
AI06811B
V
SS
V
CC
WS
7/47
Signal description M45PE80
2 Signal description
2.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the
device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip
Select (S
After Power-up, a falling edge on Chip Select (S
instruction.
) Low enables the device, placing it in the active power mode.
2.5 Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory.
When Reset (Reset
When Reset (Reset
output Q is high impedance:
If an internal operation (Write, Erase or Program cycle) is in progress when Reset (Reset
driven Low, the device enters the Reset mode and any on-going Write, Program or Erase
cycle is aborted. The addressed data may be lost.
) is driven High, the memory is in the normal operating mode.
) is driven Low, the device enters the Reset mode. In this mode, the
2.6 Write Protect (W)
) is required prior to the start of any
) is
This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is
connected to V
them from write, program and erase operations. When Write Protect (W
V
, the first 256 pages of memory behave like the other pages of memory.
CC
8/47
, causing the first 256 pages of memory to become read-only by protecting
SS
) is connected to
M45PE80 Signal description
2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
9/47
SPI modes M45PE80
3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus master and memory devices on the SPI bus
V
SS
V
CC
R
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SPI Bus Master
CS3 CS2 CS1
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SDO
SDI
SCK
Device
W
V
CC
HOLD
V
CQD
RR R
SPI Memory
S
CQD
SS
SPI Memory
S
Device
W
V
CC
HOLD
V
SS
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data Output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M45PE80 is not selected if the Bus Master leaves the S
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S
C do not become High at the same time, and so, that the t
line is pulled High while the C line is pulled Low (thus ensuring that S and
requirement is met). The
SHCH
typical value of R is 100 kΩ, assuming that the time constant R*C
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
CQD
S
V
CC
SPI Memory
Device
W
V
SS
HOLD
AI12836b
line in the high impedance
(Cp = parasitic
p
10/47
M45PE80 SPI modes
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5µs.
Figure 4. SPI modes supported
CPHA
CPOL
C
0
0
1
1
C
D
Q
MSB
MSB
AI01438B
11/47
Operating features M45PE80
4 Operating features
4.1 Sharing the overhead of modifying data
To write or program one (or more) data bytes, two instructions are required: Write Enable
(WREN), which is one byte, and a Page Write (PW) or Page Program (PP) sequence, which
consists of four bytes plus data. This is followed by the internal cycle (of duration t
To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to
256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at
a time, provided that they lie in consecutive addresses on the same page of memory.
4.2 An easy way to modify data
The Page Write (PW) instruction provides a convenient way of modifying data (up to 256
contiguous bytes at a time), and simply requires the start address, and the new data in the
instruction sequence.
PW
or tPP).
The Page Write (PW) instruction is entered by driving Chip Select (S
transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte,
and then driving Chip Select (S
bytes are written to the data buffer, starting at the address given in the third address byte
(A7-A0). When Chip Select (S
unchanged, bytes of the data buffer are automatically loaded with the values of the
corresponding bytes of the addressed memory page. The addressed memory page then
automatically put into an Erase cycle. Finally, the addressed memory page is programmed
with the contents of the data buffer.
All of this buffer management is handled internally, and is transparent to the user. The user
is given the facility of being able to alter the contents of the memory on a byte-by-byte basis.
For optimized timings, it is recommended to use the Page Write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few bytes (see Page Write (PW) and Ta bl e 1 4 : AC
characteristics (50 MHz operation)).
) High. While Chip Select (S) is being held Low, the data
) is driven High, the Write cycle starts. The remaining,
) Low, and then
12/47
M45PE80 Operating features
4.3 A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to 0 that had
previously been set to 1.
This might be:
● when the designer is programming the device for the first time
● when the designer knows that the page has already been erased by an earlier Page
Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a
fast stream of data, having first performed the erase cycle when time was available
● when the designer knows that the only changes involve resetting bits to 0 that are still
set to 1. When this method is possible, it has the additional advantage of minimizing the
number of unnecessary erase operations, and the extra stress incurred by each page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Page Program (PP)
and Table 14: AC characteristics (50 MHz operation)).
4.4 Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (t
Status Register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
, tPP, tPE, or tSE). The Write In Progress (WIP) bit is provided in the
PW
4.5 Reset
An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset
driving it High when V
has reached the correct voltage level, VCC(min).
CC
) Low during the Power-on process, and only
4.6 Active Power, Stand-by Power and Deep Power-Down modes
When Chip Select (S) is Low, the device is enabled, and in the Active Power mode.
When Chip Select (S
mode until all internal cycles have completed (Program, Erase, Write). The device then goes
in to the Stand-by Power mode. The device consumption drops to I
The Deep Power-down mode is entered when the specific instruction (the Enter Deep
Power-down Mode (DP) instruction) is executed. The device consumption drops further to
I
. The device remains in this mode until another specific instruction (the Release from
CC2
Deep Power-down Mode) is executed.
) is High, the device is disabled, but could remain in the Active Power
.
CC1
While in the Deep Power-down mode, the device ignores all Write, Program and Erase
instructions (see Deep Power-down (DP)). This can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.
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Operating features M45PE80
4.7 Status Register
The Status Register contains two status bits that can be read by the Read Status Register
(RDSR) instruction. See Section 6.4: Read Status Register (RDSR) for a detailed
description of the Status Register bits.
4.8 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M45PE80 boasts the following data protection mechanisms:
● Power-On Reset and an internal timer (t
inadvertent changes while the power supply is outside the operating specification.
● Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
– Reset (RESET
) driven Low
– Write Disable (WRDI) instruction completion
– Page Write (PW) instruction completion
– Page Program (PP) instruction completion
– Page Erase (PE) instruction completion
– Sector Erase (SE) instruction completion
● The Hardware Protected mode is entered when Write Protect (W) is driven Low,
causing the first 256 pages of memory to become read-only. When Write Protect (W
driven High, the first 256 pages of memory behave like the other pages of memory
● The Reset (Reset) signal can be driven Low to protect the contents of the memory
during any critical time, not just during Power-up and Power-down.
● In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions while
the device is not in active use.
) can provide protection against
PUW
) is
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M45PE80 Memory organization
5 Memory organization
The memory is organized as:
● 4096 pages (256 bytes each).
● 1 048 576 bytes (8 bits each)
● 16 sectors (512 Kbits, 65536 bytes each)
Each page can be individually:
● programmed (bits are programmed from 1 to 0)
● erased (bits are erased from 0 to 1)
● written (bits are changed to either 0 or 1)
The device is Page or Sector Erasable (bits are erased from 0 to 1).
Table 2. Memory organization
Sector Address range
15 F0000h FFFFFh
14 E0000h EFFFFh
13 D0000h DFFFFh
12 C0000h CFFFFh
11 B0000h BFFFFh
10 A0000h AFFFFh
9 90000h 9FFFFh
8 80000h 8FFFFh
7 70000h 7FFFFh
6 60000h 6FFFFh
5 50000h 5FFFFh
4 40000h 4FFFFh
3 30000h 3FFFFh
2 20000h 2FFFFh
1 10000h 1FFFFh
0 00000h 0FFFFh
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