Numonyx M45PE80 Technical data

8 Mbit, low voltage, Page-Erasable Serial Flash memory

with byte alterability and a 50 MHz SPI bus interface

Features

■ SPI bus compatible serial interface

■ 50 MHz clock rate (maximum)

■ 2.7 V to 3.6 V single supply voltage

■ 8 Mbit of Page-Erasable Flash memory

■ Page size: 256 bytes:

– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)

■ Sector Erase (64 Kbytes)

■ Hardware Write protection of the bottom sector

(64 Kbytes)

■ Electronic signature

– JEDEC standard two-byte signature

(4014h)

■ Deep Power-down mode 1 µA (typical)

■ More than 100 000 Write cycles

■ More than 20 years’ data retention

■ Packages

– ECOPACK® (RoHS compliant)

M45PE80

VFQFPN8 (MP)

6 × 5 mm (MLP8)

SO8W (MW)

208 mils width

SO8N (MN)

150 mils width

December 2007 Rev 9 1/47

www.numonyx.com

1

Contents M45PE80

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Chip Select (S

2.5 Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Write Protect (W

2.7 V

2.8 V

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SS

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13

4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.6 Active Power, Stand-by Power and Deep Power-Down modes . . . . . . . . 13

4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/47

M45PE80 Contents

6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.5 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.6 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 22

6.7 Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.9 Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.10 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.12 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

13 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3/47

List of tables M45PE80

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. Power-Up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 8. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 12. AC characteristics (25 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 13. AC characteristics (33 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 14. AC characteristics (50 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 15. Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 16. Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 17. VFQFPN8 (MLP8)8-lead Very thin Fine Pitch Quad Flat Package No lead,

6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, mechanical data. . . . . . . . 42

Table 19. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4/47

M45PE80 List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 19

Figure 9. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 20

Figure 10. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 21

Figure 11. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence

and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Page Write (PW) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14. Page Erase (PE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 15. Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 16. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 17. Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 30

Figure 18. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 21. Write Protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 22. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 23. Reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 25. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . 42

Figure 26. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 43

5/47

Summary description M45PE80

1 Summary description

The M45PE80 is a 8 Mbit (1 Mbit × 8 bit) Serial Paged Flash Memory accessed by a high

speed SPI-compatible bus.

The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or

Page Program instruction. The Page Write instruction consists of an integrated Page Erase

cycle followed by a Page Program cycle.

The memory is organized as 16 sectors, each containing 256 pages. Each page is 256

bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1 048

576 bytes.

The memory can be erased a page at a time, using the Page Erase instruction, or a sector

at a time, using the Sector Erase instruction.

In order to meet environmental requirements, Numonyx offers the M45PE80 in ECOPACK®

packages. ECOPACK® packages are Lead-free and RoHS compliant.

Figure 1. Logic diagram

V

CC

D

C

S

W

Reset

Table 1. Signal names

Signal name Function Direction

C Serial Clock Input

D Serial Data Input Input

Q Serial Data Output Output

S Chip Select Input

Write Protect Input

W

Reset Input

Reset

M45PE80

V

SS

Q

AI06810B

V

CC

V

SS

6/47

Supply Voltage

Ground

M45PE80 Summary description

Figure 2. VFQFPN and SO connections

M45PE80

DQ

1

C

2

Reset

3
4

1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.

8
7
6
5

AI06811B

V

SS

V

CC

WS

7/47

Signal description M45PE80

2 Signal description

2.1 Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).

2.2 Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the
device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip
Select (S

After Power-up, a falling edge on Chip Select (S
instruction.

) Low enables the device, placing it in the active power mode.

2.5 Reset (Reset)

The Reset (Reset) input provides a hardware reset for the memory.

When Reset (Reset

When Reset (Reset
output Q is high impedance:

If an internal operation (Write, Erase or Program cycle) is in progress when Reset (Reset
driven Low, the device enters the Reset mode and any on-going Write, Program or Erase
cycle is aborted. The addressed data may be lost.

) is driven High, the memory is in the normal operating mode.

) is driven Low, the device enters the Reset mode. In this mode, the

2.6 Write Protect (W)

) is required prior to the start of any

) is

This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is
connected to V
them from write, program and erase operations. When Write Protect (W
V

, the first 256 pages of memory behave like the other pages of memory.

CC

8/47

, causing the first 256 pages of memory to become read-only by protecting

SS

) is connected to

M45PE80 Signal description

2.7 VCC supply voltage

VCC is the supply voltage.

2.8 VSS ground

VSS is the reference for the VCC supply voltage.

9/47

SPI modes M45PE80

3 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:

● CPOL=0, CPHA=0

● CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:

● C remains at 0 for (CPOL=0, CPHA=0)

● C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. Bus master and memory devices on the SPI bus

V

SS

V

CC

R

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SPI Bus Master

CS3 CS2 CS1

1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

SDO

SDI

SCK

Device

W

V

CC

HOLD

V

CQD

RR R

SPI Memory

S

CQD

SS

SPI Memory

S

Device

W

V

CC

HOLD

V

SS

Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one

device is selected at a time, so only one device drives the Serial Data Output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M45PE80 is not selected if the Bus Master leaves the S
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S
C do not become High at the same time, and so, that the t

line is pulled High while the C line is pulled Low (thus ensuring that S and

requirement is met). The

SHCH

typical value of R is 100 kΩ, assuming that the time constant R*C
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.

CQD

S

V

CC

SPI Memory

Device

W

V

SS

HOLD

AI12836b

line in the high impedance

(Cp = parasitic

p

10/47

M45PE80 SPI modes

Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus

Master never leaves the SPI bus in the high impedance state for a time period shorter than
5µs.

Figure 4. SPI modes supported

CPHA

CPOL

C

0

0

1

1

C

D

Q

MSB

MSB

AI01438B

11/47

Operating features M45PE80

4 Operating features

4.1 Sharing the overhead of modifying data

To write or program one (or more) data bytes, two instructions are required: Write Enable
(WREN), which is one byte, and a Page Write (PW) or Page Program (PP) sequence, which
consists of four bytes plus data. This is followed by the internal cycle (of duration t

To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to
256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at
a time, provided that they lie in consecutive addresses on the same page of memory.

4.2 An easy way to modify data

The Page Write (PW) instruction provides a convenient way of modifying data (up to 256
contiguous bytes at a time), and simply requires the start address, and the new data in the
instruction sequence.

PW

or tPP).

The Page Write (PW) instruction is entered by driving Chip Select (S
transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte,
and then driving Chip Select (S
bytes are written to the data buffer, starting at the address given in the third address byte
(A7-A0). When Chip Select (S
unchanged, bytes of the data buffer are automatically loaded with the values of the
corresponding bytes of the addressed memory page. The addressed memory page then
automatically put into an Erase cycle. Finally, the addressed memory page is programmed
with the contents of the data buffer.

All of this buffer management is handled internally, and is transparent to the user. The user
is given the facility of being able to alter the contents of the memory on a byte-by-byte basis.

For optimized timings, it is recommended to use the Page Write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few bytes (see Page Write (PW) and Ta bl e 1 4 : AC

characteristics (50 MHz operation)).

) High. While Chip Select (S) is being held Low, the data

) is driven High, the Write cycle starts. The remaining,

) Low, and then

12/47

M45PE80 Operating features

4.3 A fast way to modify data

The Page Program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to 0 that had
previously been set to 1.

This might be:

● when the designer is programming the device for the first time

● when the designer knows that the page has already been erased by an earlier Page

Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a
fast stream of data, having first performed the erase cycle when time was available

● when the designer knows that the only changes involve resetting bits to 0 that are still

set to 1. When this method is possible, it has the additional advantage of minimizing the
number of unnecessary erase operations, and the extra stress incurred by each page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Page Program (PP)
and Table 14: AC characteristics (50 MHz operation)).

4.4 Polling during a Write, Program or Erase cycle

A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (t
Status Register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.

, tPP, tPE, or tSE). The Write In Progress (WIP) bit is provided in the

PW

4.5 Reset

An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset
driving it High when V

has reached the correct voltage level, VCC(min).

CC

) Low during the Power-on process, and only

4.6 Active Power, Stand-by Power and Deep Power-Down modes

When Chip Select (S) is Low, the device is enabled, and in the Active Power mode.

When Chip Select (S
mode until all internal cycles have completed (Program, Erase, Write). The device then goes
in to the Stand-by Power mode. The device consumption drops to I

The Deep Power-down mode is entered when the specific instruction (the Enter Deep
Power-down Mode (DP) instruction) is executed. The device consumption drops further to
I

. The device remains in this mode until another specific instruction (the Release from

CC2

Deep Power-down Mode) is executed.

) is High, the device is disabled, but could remain in the Active Power

.

CC1

While in the Deep Power-down mode, the device ignores all Write, Program and Erase
instructions (see Deep Power-down (DP)). This can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.

13/47

Operating features M45PE80

4.7 Status Register

The Status Register contains two status bits that can be read by the Read Status Register
(RDSR) instruction. See Section 6.4: Read Status Register (RDSR) for a detailed
description of the Status Register bits.

4.8 Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M45PE80 boasts the following data protection mechanisms:

● Power-On Reset and an internal timer (t

inadvertent changes while the power supply is outside the operating specification.

● Program, Erase and Write instructions are checked that they consist of a number of

clock pulses that is a multiple of eight, before they are accepted for execution.

● All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:

–Power-up
– Reset (RESET

) driven Low
– Write Disable (WRDI) instruction completion
– Page Write (PW) instruction completion
– Page Program (PP) instruction completion
– Page Erase (PE) instruction completion
– Sector Erase (SE) instruction completion

● The Hardware Protected mode is entered when Write Protect (W) is driven Low,

causing the first 256 pages of memory to become read-only. When Write Protect (W
driven High, the first 256 pages of memory behave like the other pages of memory

● The Reset (Reset) signal can be driven Low to protect the contents of the memory

during any critical time, not just during Power-up and Power-down.

● In addition to the low power consumption feature, the Deep Power-down mode offers

extra software protection from inadvertent Write, Program and Erase instructions while
the device is not in active use.

) can provide protection against

PUW

) is

14/47

M45PE80 Memory organization

5 Memory organization

The memory is organized as:

● 4096 pages (256 bytes each).

● 1 048 576 bytes (8 bits each)

● 16 sectors (512 Kbits, 65536 bytes each)

Each page can be individually:

● programmed (bits are programmed from 1 to 0)

● erased (bits are erased from 0 to 1)

● written (bits are changed to either 0 or 1)

The device is Page or Sector Erasable (bits are erased from 0 to 1).

Table 2. Memory organization

Sector Address range

15 F0000h FFFFFh

14 E0000h EFFFFh

13 D0000h DFFFFh

12 C0000h CFFFFh

11 B0000h BFFFFh

10 A0000h AFFFFh

9 90000h 9FFFFh

8 80000h 8FFFFh

7 70000h 7FFFFh

6 60000h 6FFFFh

5 50000h 5FFFFh

4 40000h 4FFFFh

3 30000h 3FFFFh

2 20000h 2FFFFh

1 10000h 1FFFFh

0 00000h 0FFFFh

15/47

Memory organization M45PE80

Figure 5. Block diagram

Reset

W

S

C

D

Q

Control Logic

Address Register

and Counter

Y Decoder

10000h

00000h

High Voltage

Generator

I/O Shift Register

256 Byte

Data Buffer

256 Bytes (Page Size)

FFFFFh

000FFh

Status

Register

First 256 Pages can
be made read-only

16/47

X Decoder

AI06812

M45PE80 Instructions

6 Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit
first.

Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S

) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of
Serial Clock (C).

The instruction set is listed in Ta bl e 3 .

Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read)
or Read Status Register (RDSR) instruction, the shifted-in instruction sequence is followed
by a data-out sequence. Chip Select (S
sequence is being shifted out.

In the case of a Page Write (PW), Page Program (PP), Page Erase (PE), Sector Erase (SE),
Write Enable (WREN), Write Disable (WRDI), Deep Power-down (DP) or Release from
Deep Power-down (RDP) instruction, Chip Select (S
boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S
must driven High when the number of clock pulses after Chip Select (S
an exact multiple of eight.

) can be driven High after any bit of the data-out

) must be driven High exactly at a byte

) being driven Low is

)

All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle
are ignored, and the internal Write cycle, Program cycle or Erase cycle continues
unaffected.

Table 3. Instruction set

Instruction Description

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDID Read Identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ

PW Page Write 0000 1010 0Ah 3 0 1 to 256

PP Page Program 0000 0010 02h 3 0 1 to 256

PE Page Erase 1101 1011 DBh 3 0 0

SE Sector Erase 1101 1000 D8h 3 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

Read Data Bytes at Higher
Speed

One-byte instruction

code

0000 1011 0Bh 3 1 1 to ∞

Address

bytes

Dummy

bytes

Data

bytes

RDP

Release from Deep
Power-down

1010 1011 ABh 0 0 0

17/47

Instructions M45PE80

6.1 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 6) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page
Program (PP), Page Erase (PE), and Sector Erase (SE) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (S
instruction code, and then driving Chip Select (S

Figure 6. Write Enable (WREN) instruction sequence

S

C

D

Q

6.2 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 7) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S
instruction code, and then driving Chip Select (S

The Write Enable Latch (WEL) bit is reset under the following conditions:

● Power-up

● Write Disable (WRDI) instruction completion

● Page Write (PW) instruction completion

● Page Program (PP) instruction completion

● Page Erase (PE) instruction completion

● Sector Erase (SE) instruction completion

21 34567

0

Instruction

High Impedance

) Low, sending the

) High.

AI02281E

) Low, sending the

) High.

Figure 7. Write Disable (WRDI) instruction sequence

S

C

D

Q

18/47

0

21 34567

Instruction

High Impedance

AI03750D

M45PE80 Instructions

6.3 Read Identification (RDID)

The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be
read, followed by two bytes of device identification. The manufacturer identification is
assigned by JEDEC, and has the value 20h for Numonyx. The device identification is
assigned by the device manufacturer, and indicates the memory type in the first byte (40h),
and the memory capacity of the device in the second byte (14h).

Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress. The Read Identification
(RDID) instruction should not be issued while the device is in Deep Power-down mode.

The device is first selected by driving Chip Select (S

) Low. Then, the 8-bit instruction code
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during
the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 8.

The Read Identification (RDID) instruction is terminated by driving Chip Select (S

) High at

any time during data output.

When Chip Select (S

) is driven High, the device is put in the Stand-by Power mode. Once in
the Stand-by Power mode, the device waits to be selected, so that it can receive, decode
and execute instructions.

Table 4. Read Identification (RDID) data-out sequence

Device Identification

Manufacturer Identification

Memory Type Memory Capacity

20h 40h 14h

Figure 8. Read Identification (RDID) instruction sequence and data-out sequence

S

21 3456789101112131415

0

C

Instruction

D

16 16 18 28 29 30 31

Q

High Impedance

Manufacturer Identification

MSB

Device Identification

15 1413 3210

MSB

AI06809

19/47

Instructions M45PE80

6.4 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In
Progress (WIP) bit before sending a new instruction to the device. It is also possible to read
the Status Register continuously, as shown in Figure 9.

The status bits of the Status Register are as follows:

6.4.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program
or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is
in progress.

6.4.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write, Program or Erase instruction is accepted.

Table 5. Status Register Format

b7 b0

0 0 0 0 0 0 WEL

1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is

automatically set and reset by the internal logic of the device).

(1)

WIP

(1)

Figure 9. Read Status Register (RDSR) instruction sequence and data-out

sequence

S

21 3456789101112131415

0

C

Instruction

D

Q

High Impedance

Status Register Out

7 6543210

MSB

Status Register Out

7 6543210

MSB

7

AI02031E

20/47

M45PE80 Instructions

6.5 Read Data Bytes (READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum
frequency f

The instruction sequence is shown in Figure 10.

The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.

, during the falling edge of Serial Clock (C).

R

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S
Select (S

) can be driven High at any time during data output. Any Read Data Bytes (READ)

) High. Chip

instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.

Figure 10. Read Data Bytes (READ) instruction sequence and data-out sequence

S

21 345678910 2829303132333435

0

C

Instruction 24-Bit Address

D

High Impedance

Q

1. Address bits A23 to A20 are Don’t Care.

23

MSB

2221 3210

76543 1 7

MSB

36 37 38

Data Out 1

39

Data Out 2

2

0

AI03748D

21/47

Instructions M45PE80

6.6 Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23­A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency f

The instruction sequence is shown in Figure 11.

The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S

) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.

Figure 11. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence

and data-out sequence

, during the falling edge of Serial Clock (C).

C

S

21 345678910 28293031

0

C

Instruction 24 BIT ADDRESS

23

D

High Impedance

Q

S

32 33 34 36 37 38 39 40 41 42 43 44 45 46

C

D

Q

765432 0

35

Dummy Byte

2221 3210

1

DATA OUT 1

765432 0

MSB

47

DATA OUT 2

7 6543210

1

MSB MSB

7

1. Address bits A23 to A20 are Don’t Care.

22/47

AI04006

M45PE80 Instructions

6.7 Page Write (PW)

The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch
(WEL).

The Page Write (PW) instruction is entered by driving Chip Select (S
instruction code, three address bytes and at least one data byte on Serial Data Input (D).
The rest of the page remains unchanged if no power failure occurs and the device is not
reset during the write cycle.

The Page Write (PW) instruction performs a page erase cycle even if only one byte is
updated.

If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the addressed page boundary roll over, and are written from the start address of the same
page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S
must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 12.

If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be written correctly within the same page. If less than
256 Data bytes are sent to device, they are correctly written at the requested addresses
without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the Page Write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few bytes (see Table 14: AC characteristics (50 MHz

operation)).

Chip Select (S
latched in, otherwise the Page Write (PW) instruction is not executed.

) must be driven High after the eighth bit of the last data byte has been

) Low, followed by the

)

As soon as Chip Select (S
is t

) is initiated. While the Page Write cycle is in progress, the Status Register may be

PW

read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.

A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed.

Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.

) is driven High, the self-timed Page Write cycle (whose duration

23/47

Instructions M45PE80

Figure 12. Page Write (PW) instruction sequence

S

21 345678910 2829303132333435

0

C

Instruction 24-Bit Address

D

S

4241 43 44 45 46 47 48 49 50 52 53 54 5540

C

Data Byte 2

D

765432 0

MSB MSB MSB

1

1. Address bits A23 to A20 are Don’t Care

2. 1 ≤ n ≤ 256

23

2221 3210

MSB

51

Data Byte 3 Data Byte n

765432 0

1

765432 0

MSB

765432 0

36 37 38

Data Byte 1

39

1

1

AI04045

24/47

M45PE80 Instructions

6.8 Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S
the instruction code, three address bytes and at least one data byte on Serial Data Input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the addressed page boundary roll over, and are programmed from the start address of the
same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select
(S

) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 13.

If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Table 14: AC

characteristics (50 MHz operation)).

Chip Select (S
latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (S
duration is t
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset.

) must be driven High after the eighth bit of the last data byte has been

) is driven High, the self-timed Page Program cycle (whose

) is initiated. While the Page Program cycle is in progress, the Status Register

PP

) Low, followed by

A Page Program (PP) instruction applied to a page that is Hardware Protected is not
executed.

Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.

25/47

Instructions M45PE80

Figure 13. Page Program (PP) instruction sequence

S

21 345678910 2829303132333435

0

C

Instruction 24-Bit Address

D

S

4241 43 44 45 46 47 48 49 50 52 53 54 5540

C

Data Byte 2

D

765432 0

MSB MSB MSB

1

1. Address bits A23 to A20 are Don’t Care

2. 1 ≤ n ≤ 256

23

2221 3210

MSB

51

Data Byte 3 Data Byte n

765432 0

1

765432 0

MSB

765432 0

36 37 38

Data Byte 1

39

1

1

AI04044

26/47

M45PE80 Instructions

6.9 Page Erase (PE)

The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can
be accepted, a Write Enable (WREN) instruction must previously have been executed. After
the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable
Latch (WEL).

The Page Erase (PE) instruction is entered by driving Chip Select (S

) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Page is a valid address for the Page Erase (PE) instruction. Chip Select (S

) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

Chip Select (S

) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip
Select (S

) is driven High, the self-timed Page Erase cycle (whose duration is tPE) is initiated.
While the Page Erase cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self­timed Page Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL) bit is reset.

A Page Erase (PE) instruction applied to a page that is Hardware Protected is not executed.

Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.

Figure 14. Page Erase (PE) instruction sequence

S

21 3456789 293031

0

C

Instruction

D

1. Address bits A23 to A20 are Don’t Care.

24 Bit Address

23 22 2 0

MSB

27/47

1

AI04046

Instructions M45PE80

6.10 Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (S

) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Sector (see Ta bl e 2 ) is a valid address for the Sector Erase (SE) instruction. Chip Select (S
must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S

) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S

) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a sector that contains a page that is Hardware
Protected is not executed.

Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.

Figure 15. Sector Erase (SE) instruction sequence

S

21 3456789 293031

0

C

)

Instruction

D

1. Address bits A23 to A20 are Don’t Care.

28/47

24 Bit Address

23 22 2 0

MSB

1

AI03751D

M45PE80 Instructions

6.11 Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ignores all Write, Program and Erase instructions.

Driving Chip Select (S

) High deselects the device, and puts the device in the Standby mode
(if there is no internal cycle currently in progress). But this mode is not the Deep Power­down mode. The Deep Power-down mode can only be entered by executing the Deep
Power-down (DP) instruction, to reduce the standby current (from I

CC1

to I

, as specified

CC2

in Ta bl e 1 1 ).

To exit from Deep Power-down mode, the Release from Deep Power-down (RDP)
instruction must be issued. No other instruction must be issued while

the device is in this mode.

The Deep Power-down mode automatically stops at Power-down, and the device always
Powers-up in the Standby mode.

The Deep Power-down (DP) instruction is entered by driving Chip Select (S
by the instruction code on Serial Data Input (D). Chip Select (S

) must be driven Low for the

) Low, followed

entire duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S

) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S
to I

and the Deep Power-down mode is entered.

CC2

) is driven High, it requires a delay of tDP before the supply current is reduced

Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.

Figure 16. Deep Power-down (DP) instruction sequence

S

t

21 345670

C

Instruction

D

29/47

DP

Stand-by Mode

Deep Power-down Mode

AI03753D

Instructions M45PE80

6.12 Release from Deep Power-down (RDP)

To exit from Deep Power-down mode, the Release from Deep Power-down (RDP)
instruction must be issued. No other instruction must be issued while the device is in this
mode.

The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S
Low, followed by the instruction code on Serial Data Input (D). Chip Select (S

) must be

driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 17.

The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S

) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven

Low, cause the instruction to be rejected, and not executed.

After Chip Select (S
Standby mode. Chip Select (S

) has been driven High, followed by a delay, t

) must remain High at least until this period is over. The

, the device is put in the

RDP

device waits to be selected, so that it can receive, decode and execute instructions.

Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Release from Deep Power-down (RDP) instruction sequence

S

t

21 345670

C

Instruction

D

RDP

)

High Impedance

Q

30/47

Deep Power-down Mode

Stand-by Mode

AI06807

M45PE80 Power-up and Power-down

7 Power-up and Power-down

At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V

● V

●

(min) at Power-up, and then for a further delay of t

CC

VSS at Power-down

A safe configuration is provided in Section 3: SPI modes.

To avoid data corruption and inadvertent write operations during power up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V
than the POR threshold value, V
respond to any instruction.

Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of t
elapsed after the moment that V
operation of the device is not guaranteed if, by this time, V
Write, Program or Erase instructions should be sent until the later of:

● t

● t

after VCC passed the VWI threshold

PUW

after VCC passed the VCC(min) level

VSL

These values are specified in Ta bl e 6 .

) until VCC reaches the correct value:

CC

VSL

– all operations are disabled, and the device does not

WI

rises above the VWI threshold. However, the correct

CC

is still below VCC(min). No

CC

is less

CC

PUW

has

If the delay, t
selected for READ instructions even if the t

As an extra protection, the Reset (Reset

, has elapsed, after VCC has risen above VCC(min), the device can be

VSL

delay is not yet fully elapsed.

PUW

) signal could be driven Low for the whole duration

of the Power-up and Power-down phases.

At Power-up, the device is in the following state:

● The device is in the Standby mode (not the Deep Power-down mode).

● The Write Enable Latch (WEL) bit is reset.

● The Write In Progress (WIP) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the V
device in a system should have the V

rail decoupled by a suitable capacitor close to the

CC

feed. Each

CC

package pins. (Generally, this capacitor is of the order of 100 nF).

At Power-down, when V
value, V

, all operations are disabled and the device does not respond to any instruction.

WI

drops from the operating voltage, to below the POR threshold

CC

(The designer needs to be aware that if a Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption can result.)

31/47

Power-up and Power-down M45PE80

Figure 18. Power-up timing

V

CC

VCC(max)

Program, Erase and Write Commands are Rejected by the Device

Chip Selection Not Allowed

VCC(min)

Reset State

of the

Device

V

WI

Table 6. Power-Up timing and VWI threshold

tVSL

tPUW

Read Access allowed Device fully

accessible

time

AI04009C

Symbol Parameter Min. Max. Unit

(1)

t

VSL

t

PUW

V

WI

1. These parameters are characterized only, over the temperature range –40°C to +85°C.

VCC(min) to S low 30 µs

(1)

Time delay before the first Write, Program or Erase instruction 1 10 ms

(1)

Write inhibit voltage 1.5 2.5 V

32/47

M45PE80 Initial delivery state

8 Initial delivery state

The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). All usable Status Register bits are 0.

9 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

T

T

LEAD

V

V

V

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx

ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS) 2002/95/EU.

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Storage temperature –65 150 °C

STG

Lead temperature during soldering See

Input and output voltage (with respect to Ground) –0.6 VCC + 0.6 V

IO

Supply voltage –0.6 4.0 V

CC

Electrostatic Discharge Voltage (Human Body Model)

ESD

(2)

–2000 2000 V

(1)

°C

33/47

DC and AC parameters M45PE80

10 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.

Table 8. Operating conditions

Symbol Parameter Min. Max. Unit

V

CC

T

A

Table 9. AC measurement conditions

Supply voltage 2.7 3.6 V

Ambient operating temperature –40 85 °C

Symbol Parameter Min. Max. Unit

C

Load capacitance 30 pF

L

Input rise and fall times 5 ns

Input pulse voltages 0.2VCC to 0.8V

Input and output timing reference voltages 0.3V

1. Output Hi-Z is defined as the point where data out is no longer driven.

to 0.7V

CC

CC

CC

Figure 19. AC measurement I/O waveform

Input Levels

0.8V

0.2V

Table 10. Capacitance

CC

CC

(1)

Input and Output

Timing Reference Levels

0.7V

CC

0.3V

CC

AI00825B

V

V

Symbol Parameter Test Condition Min. Max. Unit

C

OUT

C

1. Sampled only, not 100% tested, at T

Output capacitance (Q) V

Input capacitance (other pins) VIN = 0 V 6 pF

IN

=25°C and a frequency of 20MHz.

A

34/47

= 0 V 8 pF

OUT

M45PE80 DC and AC parameters

Table 11. DC characteristics

Symbol Parameter

I

Input leakage current ± 2 µA

LI

Output leakage current ± 2 µA

I

LO

Standby current

I

(Standby and Reset

CC1

modes)

I

I

I

I

V

V

V

Deep Power-down

CC2

current

Operating current

CC3

(FAST_READ)

Operating current (PW) S = V

CC4

Operating current (SE) S = V

CC5

V

Input low voltage – 0.5 0.3V

IL

Input high voltage 0.7V

IH

Output low voltage IOL = 1.6 mA 0.4 V

OL

Output high voltage IOH = –100 µA VCC–0.2 V

OH

Test condition

(in addition to those in Tabl e 8 )

S = VCC, V

= VCC, V

S

= VSS or V

IN

= VSS or V

IN

CC

CC

C = 0.1VCC / 0.9.VCC at 25 MHz,

Q = open

C = 0.1V

/ 0.9.VCC at 50 MHz,

CC

Q = open

CC

CC

Min. Max. Unit

50 µA

10 µA

6

mA

8

15 mA

15 mA

V

CC

CCVCC

+0.4 V

35/47

DC and AC parameters M45PE80

Table 12. AC characteristics (25 MHz operation)

Test conditions specified in Tab l e 8 and Tab l e 9

Symbol Alt. Parameter Min. Typ. Max. Unit

Clock Frequency for the following

f

C

f

R

(1)

t

CH

(1)

t

CL

t

SLCHtCSS

t

CHSL

t

DVCHtDSU

t

CHDXtDH

t

CHSH

t

SHCH

t

SHSLtCSH

t

SHQZ

t

CLQV

t

CLQX

t

SHRH

t

WHSL

t

SHWL

(2)

t

DP

t

RDP

t

PW

(3)

t

PP

t

PE

t

SE

1. tCH + tCL must be greater than or equal to 1/ f

2. Value guaranteed by characterization, not 100% tested in production.

3. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one

sequence including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤ 256)

f

instructions: FAST_READ, PW, PP, PE,

C

D.C. 25 MHz

SE, DP, RDP, WREN, WRDI, RDSR

Clock Frequency for READ instructions D.C. 20 MHz

t

Clock High Time 18 ns

CLH

t

Clock Low Time 18 ns

CLL

(2)

Clock Slew Rate

(peak to peak) 0.03 V/ns

S Active Setup Time (relative to C) 10 ns

S Not Active Hold Time (relative to C) 10 ns

Data In Setup Time 5 ns

Data In Hold Time 5 ns

S Active Hold Time (relative to C) 10 ns

S Not Active Setup Time (relative to C) 10 ns

S Deselect Time 200 ns

(2)

t

Output Disable Time 15 ns

DIS

tVClock Low to Output Valid 15 ns

t

Output Hold Time 0 ns

HO

Chip should have been deselected
before Reset is de-asserted

10 ns

Write Protect Setup Time 50 ns

Write Protect Hold Time 100 ns

S to Deep Power-down 3 μs

(2)

S High to Standby Mode 30 μs

Page Write Cycle Time (256 bytes) 11

(3)

Page Write Cycle Time (n bytes)

10.2+

n*0.8/256

Page Program Cycle Time (256 bytes) 1.2

Page Program Cycle Time (n bytes)

0.4+

n*0.8/256

Page Erase Cycle Time 10 20 ms

Sector Erase Cycle Time 1 5 s

C

25 ms

5ms

36/47

M45PE80 DC and AC parameters

Table 13. AC characteristics (33 MHz operation)

33 MHz only available for products marked since week 40 of 2005

Test conditions specified in Tab l e 8 and Tab l e 9

Symbol Alt. Parameter Min. Typ. Max. Unit

Clock frequency for the following
instructions: FAST_READ, PW, PP, PE,

f

C

f

C

SE, DP, RDID, RDP, WREN, WRDI,

D.C. 3 3 MHz

RDSR

f

R

(2)

t

CH

(2)

t

CL

Clock frequency for READ instructions D.C. 20 MHz

t

Clock High time 13 ns

CLH

t

Clock Low time 13 ns

CLL

(3)

Clock slew rate

(peak to peak)

0.03 V/ns

(1)

t

SLCHtCSS

t

CHSL

t

DVCHtDSU

t

CHDXtDH

t

CHSH

t

SHCH

t

SHSLtCSH

(3)

t

SHQZ

t

CLQV

t

CLQX

t

THSL

t

SHTL

(3)

t

DP

(3)

t

RDP

(4)

t

PW

(4)

t

PP

S active setup time (relative to C) 10 ns

S not active hold time (relative to C) 10 ns

Data In setup time 3 ns

Data In hold time 5 ns

S active hold time (relative to C) 5 ns

S not active setup time (relative to C) 5 ns

S deselect time 200 ns

t

Output Disable time 12 ns

DIS

tVClock Low to Output Valid 12 ns

t

Output hold time 0 ns

HO

Top Sector Lock setup time 50 ns

Top Sector Lock hold time 100 ns

S to Deep Power-down 3 μs

S High to Standby Power mode 30 μs

Page Write cycle time (256 bytes) 11

Page Write cycle time (n bytes)

10.2+

n*0.8/256

25 ms

Page Program cycle time (256 bytes) 1.2

Page Program cycle time (n bytes)

0.4+

n*0.8/256

5ms

t

PE

t

SE

1. Details of how to find the date of marking are given in Application Note, AN1995.

2. tCH + tCL must be greater than or equal to 1/ f

3. Value guaranteed by characterization, not 100% tested in production.

4. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one

sequence including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤ 256)

Page Erase cycle time 10 20 ms

Sector Erase cycle time 1 5 s

C

37/47

DC and AC parameters M45PE80

Table 14. AC characteristics (50 MHz operation)

50 MHz preliminary data for T9HX technology

(1)

(2)

Test conditions specified in Tabl e 8 and Table 9

Symbol Alt. Parameter Min. Typ. Max. Unit

Clock frequency for the following instructions:

f

C

f

FAST_READ, PW, PP, PE, SE, DP, RDP,

C

D.C. 50 MH z

WREN, WRDI, RDSR, RDID

f

R

(3)

t

CH

(3)

t

CL

t

SLCHtCSS

t

CHSL

t

DVC HtDSU

t

CHDX

t

CHSH

t

SHCH

t

SHSL

(4)

t

SHQZ

t

CLQV

t

CLQX

t

WHSL

t

SHWL

(4)

t

DP

(4)

t

RDP

(4)

t

RLRH

t

RHSLtREC

t

SHRH

(5)

t

PW

(5)

t

PP

t

PE

t

SE

1. Preliminary data.

2. Delivery of parts in T9HX process to start from June 2007.

+ tCL must be greater than or equal to 1/ f

3. t

CH

4. Value guaranteed by characterization, not 100% tested in production.

5. n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2,
int(17/8) = 3.

Clock frequency for READ instructions D.C. 33 MHz

t

Clock High time 9 ns

CLH

t

Clock Low time 9 ns

CLL

(4)

Clock slew rate

(peak to peak) 0.1 V/ns

S active setup time (relative to C) 5 ns

S not active hold time (relative to C) 5 ns

Data in setup time 2 ns

t

Data in hold time 5 ns

DH

S active hold time (relative to C) 5 ns

S not active setup time (relative to C) 5 ns

t

S deselect time 100 ns

CSH

t

Output disable time 8 ns

DIS

tVClock Low to Output Valid 8 ns

t

Output hold time 0 ns

HO

Write Protect setup time 50 ns

Write Protect hold time 100 ns

S to Deep Power-down 3 µs

S High to Standby mode 30 µs

t

Reset pulse width 10 µs

RST

Reset recovery time 3 µs

Chip should have been deselected before
Reset is de-asserted

10 ns

Page Write cycle time (256 bytes) 11 23 ms

Page Program cycle time (256 bytes) 0.8

3ms

Page Program cycle time (n bytes) int(n/8) × 0.025

Page Erase cycle time 10 20 ms

Sector Erase cycle time 1 5 s

C

38/47

M45PE80 DC and AC parameters

Figure 20. Serial input timing

tSHSL

S

tSLCH

C

tDVCH

tCHSHtCHSL

tSHCH

tCHCL

tCHDX

D

Q

MSB IN

High Impedance

Figure 21. Write Protect setup and hold timing

W

tWHSL

S

C

D

High Impedance

Q

tCLCH

LSB IN

AI01447C

tSHWL

AI07439

Figure 22. Output timing

S

C

tCLQV

tCLQX

Q

ADDR.LSB IN

D

tCLQX

tCLQV

tCH

tCL

LSB OUT

tQLQH
tQHQL

tSHQZ

AI01449e

39/47

DC and AC parameters M45PE80

Table 15. Reset conditions

Test conditions specified in Tab l e 8 and Ta b l e 9

Symbol Alt. Parameter Conditions Min. Typ. Max. Unit

(1)

t

RLRH

t

SHRH

1. Value guaranteed by characterization, not 100% tested in production.

Table 16. Timings after a Reset Low pulse

t

Reset Pulse Width 10 µs

RST

Chip Select High to
Reset High

Chip should have been
deselected before Reset is
de-asserted

(1)

10 ns

Test conditions specified in Tabl e 8 and Table 9

Symbol Alt. Parameter

While decoding an instruction

Conditions:

Reset pulse occurred

(2)

Min. Typ. Max. Unit

:
WREN, WRDI, RDID, RDSR,
READ, Fast_Read, PW, PP, PE,
SE, DP, RDP

Under completion of an Erase or
Program cycle of a PW, PP, PE, SE

t

RHSLtREC

Reset
Recovery
time

operation

Device deselected (S High) and in
Standby mode

1. All the values are guaranteed by characterization, and not 100% tested in production.

2. S remains Low while Reset is Low.

Figure 23. Reset ac waveforms

S

tRHSLtSHRH

Reset

tRLRH

30 µs

300 µs

0µs

40/47

AI06808

M45PE80 Package mechanical

11 Package mechanical

Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

6 × 5 mm, package outline

θ

aaa CA

A2

C

ddd

CAB

eE2

M

bbb

b

D2

L

70-ME

E

B

E1

aaa CB

A

2x

R1

0.10 CB

A1

A3

A

D

D1

0.10 CA

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 17. VFQFPN8 (MLP8)8-lead Very thin Fine Pitch Quad Flat Package No lead,

6 × 5 mm

, package mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

A 0.85 0.80 1.00 0.0335 0.0315 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.30 0.1575 0.1496 0.1693

e1.27– –0.0500– –

R1 0.10 0.00 0.0039 0.0000

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

Θ 12° 12°

aaa 0.15 0.0059

bbb 0.10 0.0039

ddd 0.05 0.0020

41/47

Package mechanical M45PE80

Figure 25. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package

outline

A2

b

e

D

N

1

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, mechanical

CP

E

E1

A

c

LA1 k

6L_ME

data

millimeters inches

Symbol

Typ Min Max Typ Min Max

A 2.50 0.098

A1 0.00 0.25 0.000 0.010

A2 1.51 2.00 0.059 0.079

b 0.40 0.35 0.51 0.016 0.014 0.020

c 0.20 0.10 0.35 0.008 0.004 0.014

CP 0.10 0.004

D 6.05 0.238

E 5.02 6.22 0.198 0.245

E1 7.62 8.89 0.300 0.350

e1.27– –0.050––

k 0° 10° 0° 10°

L 0.50 0.80 0.020 0.031

N8 8

42/47

M45PE80 Package mechanical

Figure 26. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline

h x 45˚

A2

b

e

D

8

1

1. Drawing is not to scale.

Table 19. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package

E1

A

ccc

E

A1

L

L1

c

0.25 mm

GAUGE PLANE

k

SO-A

mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

A1.750.069

A1 0.10 0.25 0.004 0.010

A2 1.25 0.049

b 0.28 0.48 0.011 0.019

c 0.17 0.23 0.007 0.009

ccc 0.10 0.004

D 4.90 4.80 5.00 0.193 0.189 0.197

E 6.00 5.80 6.20 0.236 0.228 0.244

E1 3.90 3.80 4.00 0.154 0.150 0.157

e1.27– –0.050– –

h 0.25 0.50 0.010 0.020

k 0°8° 0°8°

L 0.40 1.27 0.016 0.050

L1 1.04 0.041

43/47

Part numbering M45PE80

12 Part numbering

Table 20. Ordering information scheme

Example: M45PE80 – V MP 6 T G

Device Type

M45PE = Page-Erasable Serial Flash Memory

Device Function

80 = 8 Mbit (1 Mbit x 8)

Operating Voltage

V = V

Package

MW = SO8W (208 mils width)

MP = VFQFPN8 6 × 5 mm (MLP8)

MN = SO8N (150 mils width)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow

Option

blank = Standard Packing

T = Tape & Reel Packing

Plating Technology

P

= 2.7 to 3.6V

CC

(1)

or G = ECOPACK® (RoHS compliant)

1. Package available only in T9HX technology.

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device or when ordering parts operating at 50 MHz (0.11µm technology, process digit
“4”), please contact your nearest Numonyx Sales Office.

The category of second Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.

44/47

M45PE80 Reference

13 Reference

● AN1995: Serial Flash Memory Device Marking.

14 Revision history

Table 21. Document revision history

Date Version Changes

10-Feb-2003 1.0 Document written

02-Apr-2003 1.1 VFQFPN8 (MLP) package added

08-Apr-2003 1.2 Document promoted to Product Preview

05-May-2003 1.3 Document promoted to Preliminary Data

Description corrected of entering Hardware Protected mode (W

04-Jun-2003 1.4

26-Nov-2003 2.0

23-Jan-2004 3.0 SO16 pin-out corrected

28-May-2004 4.0

10-May-2005 5.0

4-Oct-2005 6.0

14-Feb-2006 7

driven, and cannot be left unconnected). Document Revision History for
05-May-2003 corrected.

(min) extended to –0.6V, and tPP(typ) improved to 1.2ms. Table of

V

IO

contents, SO16 package, warning about exposed paddle on MLP8, and
Pb-free options added. Change of naming for VDFPN8 package.
Document promoted to full datasheet

Soldering temperature information clarified for RoHS compliant devices.
Device Grade clarified

SO16 wide package replaced by SO8 wide package.

Active Power, Stand-by Power and Deep Power-Down modes, Read
Identification (RDID), Deep Power-down (DP), and Release from Deep
Power-down (RDP) descriptions updated.

Table 20: Ordering information scheme updated.
Figure 22: Output timing updated.

Added Table 13: AC characteristics (33 MHz operation). An easy way to

modify data, A fast way to modify data, Page Write (PW) and Page
Program (PP) sections updated to explain optimal use of Page Write and

Page Program instructions. Updated I

characteristics. Updated Table 20: Ordering information scheme

ECOPACK® information added.

X process technology added (see Section 2.5: Reset (Reset), Table 14:

Reset timings for U process technology devices and Tabl e 1 5 : R e s e t
timings for X process technology devices). MLP package renamed as

VFQFPN8, MLP silhouette modified on page 1. T

Table 7: Absolute maximum ratings.
Table 5: Status Register Format moved from Section 4.7: Status Register

to Section 6.4: Read Status Register (RDSR). Blank option removed
under Plating Technology in Table 20: Ordering information scheme.

values in Tabl e 1 1 : D C

CC3

removed from

LEAD

must be

45/47

Revision history M45PE80

Table 21. Document revision history

Date Version Changes

50 MHz frequency added, Table 14: AC characteristics (50 MHz

operation) added. Small text changes.
Section 2.5: Reset (Reset) updated. V

descriptions added.

Figure 3: Bus master and memory devices on the SPI bus modified and

explanatory text added.

15-Dec-2006 8

Behavior of WIP bit specified at Power-up in Section 7: Power-up and

Power-down.

max modified and T

V

IO

LEAD

ratings.
Table 15: Reset conditions and Table 16: Timings after a Reset Low

pulse updated.

SO8N package added (T9HX technology only), SO8W and VFQFPN8
package specifications updated (see Section 11: Package mechanical).

10-Dec-2007 9 Applied Numonyx branding.

added in Table 7: Absolute maximum

supply voltage and VSS ground

CC

46/47

M45PE80

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.

applications.

47/47