NSC DAC1020LCV, DAC1020LCN, DAC1020LJ, DAC1020LCVX Datasheet

TL/H/5689

DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter

DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter

May 1996

DAC1020/DAC1021/DAC1022
10-Bit Binary Multiplying D/A Converter
DAC1220/DAC1222
12-Bit Binary Multiplying D/A Converter

General Description

The DAC1020 and the DAC1220 are, respectively, 10 and
12-bit binary multiplying digital-to-analog converters. A de­posited thin film R-2R resistor ladder divides the reference
current and provides the circuit with excellent temperature
tracking characteristics (0.0002%/

§

C linearity error temper­ature coefficient maximum). The circuit uses CMOS current
switches and drive circuitry to achieve low power consump­tion (30 mW max) and low output leakages (200 nA max).
The digital inputs are compatible with DTL/TTL logic levels
as well as full CMOS logic level swings. This part, combined
with an external amplifier and voltage reference, can be
used as a standard D/A converter; however, it is also very
attractive for multiplying applications (such as digitally con­trolled gain blocks) since its linearity error is essentially in­dependent of the voltage reference. All inputs are protected
from damage due to static discharge by diode clamps to V

a

and ground.

This part is available with 10-bit (0.05%), 9-bit (0.10%), and
8-bit (0.20%) non-linearity guaranteed over temperature

(note 1 of electrical characteristics). The DAC1020,
DAC1021 and DAC1022 are direct replacements for the 10­bit resolution AD7520 and AD7530 and equivalent to the
AD7533 family. The DAC1220 and DAC1222 are direct re­placements for the 12-bit resolution AD7521 and AD7531
family.

Features

Y

Linearity specified with zero and full-scale adjust only

Y

Non-linearity guaranteed over temperature

Y

Integrated thin film on CMOS structure

Y

10-bit or 12-bit resolution

Y

Low power dissipation 10 mW@15V typ

Y

Accepts variable or fixed referenceb25VsV

REF

s

25V

Y

4-quadrant multiplying capability

Y

Interfaces directly with DTL, TTL and CMOS

Y

Fast settling timeÐ500 ns typ

Y

Low feedthrough errorÐ(/2 LSB@100 kHz typ

Equivalent Circuit Note. Switches shown in digital high state

TL/H/5689– 1

10-BIT D/A CONVERTERS

Ordering Information

Temperature Range 0§Cto70§C

b

40§Cto85§C

Non-

0.05% DAC1020LCN AD7520LN,AD7530LN DAC1020LCV DAC1020LIV

Linearity

0.10% DAC1021LCN AD7520KN,AD7530KN

0.20% DAC1022LCN AD7520JN,AD7530JN

Package Outline N16A V20A

12-BIT D/A CONVERTERS

Temperature Range 0§Cto70§C

b

40§Ctoa85§C

Linearity

Non-

0.05% DAC1220LCN AD7521LN,AD7531LN DAC1220LCJ AD7521LD,AD7531LD

0.20% DAC1222LCN AD7521JN,AD7531JN DAC1222LCJ AD7521JD,AD7531JD

Package Outline N18A J18A

Note. Devices may be ordered by either part number.

C

1996 National Semiconductor Corporation RRD-B30M96/Printed in U. S. A.

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Absolute Maximum Ratings (Note 5)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

V

a

to Gnd 17V

V

REF

to Gnd

g

25V

Digital Input Voltage Range V

a

to Gnd

DC Voltage at Pin 1 or Pin 2 (Note 3)

b

100 mV to V

a

Storage Temperature Range

b

65§Ctoa150§C

Lead Temperature (Soldering, 10 sec.)

Dual-In-Line Package (plastic) 260

§

C

Dual-In-Line Package (ceramic) 300

§

C

ESD Susceptibility (Note 4) 800V

Operating Ratings

Min Max Units

Temperature (T

A

)

DAC1020LIV, DAC1220LCJ,

DAC1222LCJ

b

40a85

§

C

DAC1020LCN, DAC1020LCV,

DAC1021LCN 0

a

70

§

C

DAC1022LCN, DAC1220LCN 0

a

70

§

C

DAC1222LCN 0

a

70

§

C

Electrical Characteristics (V

a

e

15V, V

REF

e

10.000V, T

A

e

25§C unless otherwise specified)

DAC1020, DAC1021,

DAC1220, DAC1222

Parameter Conditions DAC1022 Units

Min Typ Max Min Typ Max

Resolution 10 12 Bits

Linearity Error T

MIN

k

T

A

k

T

MAX

,

b

10VkV

REF

k

a

10V,
(Note 1) End Point Adjustment Only
(See Linearity Error in Definition of Terms)

10-Bit Parts DAC1020, DAC1220 0.05 0.05 % FSR
9-Bit Parts DAC1021 0.10 0.10 % FSR
8-Bit Parts DAC1022, DAC1222 0.20 0.20 % FSR

Linearity Error Tempco

b

10VsV

REF

s

a

10V, 0.0002 0.0002 % FS/§C
(Notes 1 and 2)

Full-Scale Error

b

10VsV

REF

s

a

10V, 0.3 1.0 0.3 1.0 % FS
(Notes 1 and 2)

Full-Scale Error Tempco T

MIN

k

T

A

k

T

MAX

, 0.001 0.001 % FS/§C

(Note 2)

Output Leakage Current T

MIN

s

T

A

s

T

MAX

I

OUT 1

All Digital Inputs Low 200 200 nA

I

OUT 2

All Digital Inputs High 200 200 nA

Power Supply Sensitivity All Digital Inputs High, 0.005 0.005 % FS/V

14VsV

a

s

16V, (Note 2),

(Figure 2)

V

REF

Input Resistance 10 15 20 10 15 20 kX

Full-Scale Current Settling R

L

e

100X from 0 to 99. 95%

Time FS

All Digital Inputs Switched 500 500 ns
Simultaneously

V

REF

Feedthrough All Digital Inputs Low, 10 10 mVp-p

V

REF

e

20 Vp-p@100 kHz
J Package (Note 4) 6 9 6 9 mVp-p
N Package 2 5 2 5 mVp-p

Output Capacitance

I

OUT 1

All Digital Inputs Low 40 40 pF
All Digital Inputs High 200 200 pF

I

OUT 2

All Digital Inputs Low 200 200 pF
All Digital Inputs High 40 40 pF

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Electrical Characteristics (V

a

e

15V, V

REF

e

10.000V, T

A

e

25§C unless otherwise specified) (Continued)

DAC1020, DAC1021,

DAC1220, DAC1222

Parameter Conditions DAC1022 Units

Min Typ Max Min Typ Max

Digital Input

(Figure 1)

Low Threshold T

MIN

k

T

A

k

T

MAX

0.8 0.8 V

High Threshold T

MIN

k

T

A

k

T

MAX

2.4 2.4 V

Digital Input Current T

MIN

s

T

A

s

T

MAX

Digital Input High 1 100 1 100 mA
Digital Input Low

b

50

b

200

b

50

b

200 mA

Supply Current All Digital Inputs High 0.2 1.6 0.2 1.6 mA

All Digital Inputs Low 0.6 2 0.6 2 mA

Operating Power Supply

(Figures 1 and 2)

5 15 5 15 V

Range

Note 1: V

REF

e

g

10V and V

REF

e

g

1V. A linearity error temperature coefficient of 0.0002% FS for a 45§C rise only guarantees 0.009% maximum change in

linearity error. For instance, if the linearity error at 25

§

C is 0.045% FS it could increase to 0.054% at 70§C and the DAC will be no longer a 10-bit part. Note,

however, that the linearity error is specified over the device full temperature range which is a more stringent specification since

it includes

the linearity error

temperature coefficient.

Note 2: Using internal feedback resistor as shown in

Figure 3

.

Note 3: Both I

OUT 1

and I

OUT 2

must go to ground or the virtual ground of an operational amplifier. If V

REF

e

10V, every millivolt offset between I

OUT 1

or I

OUT 2

,

0.005% linearity error will be introduced.

Note 4: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 5: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 6: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

JMAX

, iJA, and the ambient temepature, TA. The maximum

allowable power dissipation at any temperature is P

D

e

(T

JMAX

b

TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this

device, T

JMAX

e

125§C, and the typical junction-to-ambient thermal resistance of the J18 package when board mounted is 85§C/W. For the N18 package, iJAis

120

§

C/W, for the N16 this number is 125§C/W, and for the V20 this number is 95§C/W.

Typical Performance Characteristics

TL/H/5689– 2

FIGURE 1. Digital Input Threshold vs

Ambient Temperature

FIGURE 2. Gain Error Variation vs V

a

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Typical Applications

The following applications are also valid for 12-bit systems
using the DAC1220 and 2 additional digital inputs.

Operational Amplifier Bias Current (

Figure 3

)

The op amp bias current, Ib, flows through the 15k internal
feedback resistor. BI-FET op amps have low I

b

and, there-

fore, the 15k

c

Iberror they introduce is negligible; they are

strongly recommended for the DAC1020 applications.

V

OS

Considerations

The output impedance, R

OUT

, of the DAC is modulated by
the digital input code which causes a modulation of the op­erational amplifier output offset. It is therefore recommend­ed to adjust the op amp V

OS.ROUT

isE15k if more than 4

digital inputs are high; R

OUT

isE45k if a single digital input

is high, and R

OUT

approaches infinity if all inputs are low.

Operational Amplifier V

OS

Adjust (

Figure 3

)

Connect all digital inputs, A1 –A10, to ground and adjust the
potentiometer to bring the op amp V

OUT

pin to withing1

mV from ground potential. If V

REF

is less than 10V, a finer

V

OS

adjustment is required. It is helpful to increase the reso-

lution of the V

OS

adjust procedure by connectinga1kX
resistor between the inverting input of the op amp to
ground. After V

OS

has been adjusted, remove the 1 kX.

Full-Scale Adjust (

Figure 4

)

Switch high all the digital inputs, A1 –A10, and measure the
op amp output voltage. Use a 500X potentiometer, as
shown, to bring

ll

V

OUT

ll

to a voltage equal to V

REF

c

1023/1024.

SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER

Op Amp Family C

F

R

i

PV

W

Circuit Settling Circuit Small

Time, t

s

Signal BW

LF357 10 pF 2.4k 25k V

a

1.5 ms1M

LF356 22 pF

%

25k V

a

3 ms 0.5M

LF351 24 pF

%

10k V

b

4 ms 0.5M

LM741 0

%

10k V

b

40 ms 200 kHz

TL/H/5689– 3

V

OUT

eb

V

REF

#

A1

2

a

A2

4

a

A3

8

a

###

A10

1024

J

b

10VsV

REF

s

10V

0

s

V

OUT

s

b

1023

1024

V

REF

where A

N

e

1 if the ANdigital input is high

A

N

e

0 if the ANdigital input is low

FIGURE 3. Basic Connection: Unipolar or 2-Quadrant Multiplying

Configuration (Digital Attenuator)

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Typical Applications (Continued)

FIGURE 4. Full-Scale Adjust

FIGURE 5. Alternate Full-Scale Adjust: (Allows Increasing or Decreasing the Gain)

TL/H/5689– 4

V

OUT 1

eb

V

REF

#

A1

2

a

A2

4

a

A3

8

a

###

A10

1024

J

V

OUT2

e

V

REF

#

A1

2

a

A2

4

a

A3

8

a

###

A10

1024

Jc#

B1

2

a

B2

4

a

B3

8

a

###

B10

1024

J

where V

REF

can be an AC signal

FIGURE 6. Precision Analog-to-Digital Multiplier

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