NSC DAC1008LCN, DAC1006LCWM, DAC1006LCN Datasheet
DAC1006/DAC1007/DAC1008 mP Compatible,
Double-Buffered D to A Converters
General Description
The DAC1006/7/8 are advanced CMOS/Si-Cr 10-, 9- and
8-bit accurate multiplying DACs which are designed to interface directly with the 8080, 8048, 8085, Z-80 and other popular microprocessors. These DACs appear as a memory location or an I/O port to the mP and no interfacing logic is
needed.
These devices, combined with an external amplifier and
voltage reference, can be used as standard D/A converters;
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentially independent of the voltage reference.
They become equally attractive in audio signal processing
equipment as audio gain controls or as programmable attenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control.
All of these DACs are double buffered. They can load all 10
bits or two 8-bit bytes and the data format is left justified.
The analog section of these DACs is essentially the same
as that of the DAC1020.
The DAC1006 series are the 10-bit members of a family of
microprocessor-compatible DAC’s (MICRO-DAC
applications requiring other resolutions, the DAC0830 series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are available alternatives.
Part
Ý
(bits)
Pin Description
Accuracy
DAC1006 10
DAC1007 9 20
DAC1008 8
MICRO-DACTMand BI-FETTMare trademarks of National Semiconductor Corp.
For leftjustified
data
TM
’s). For
Features
Y
Uses easy to adjust END POINT specs, NOT BEST
STRAIGHT LINE FIT
Y
Low power consumption
Y
Direct interface to all popular microprocessors
Y
Integrated thin film on CMOS structure
Y
Double-buffered, single-buffered or flow through digital
data inputs
Y
Loads two 8-bit bytes or a single 10-bit word
Y
Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
Y
Works withg10V referenceÐfull 4-quadrant multiplication
Y
Operates STAND ALONE (without mP) if desired
Y
Available in 0.3×standard 20-pin package
Y
Differential non-linearity selection available as special
order
Key Specifications
Y
Output Current Settling Time 500 ns
Y
Resolution 10 bits
Y
Linearity 10, 9, and 8 bits
Y
Gain Tempco
Y
Low Power Dissipation 20 mW
(including ladder)
Y
Single Power Supply 5 to 15 V
January 1995
(guaranteed over temp.)
b
0.0003% of FS/§C
DC
DAC1006/DAC1007/DAC1008 mP Compatible,
Double-Buffered D to A Converters
Typical Application
DAC1006/1007/1008
* NOTE: FOR DETAILS OF BUS
CONNECTION SEE SECTION 6.0
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/H/5688
TL/H/5688– 1
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Digital Input VCCto GND
Voltage at V
Storage Temperature Range
Package Dissipation at T
DC Voltage Applied to I
(Note 4)
)17V
REF
CC
Input
b
e
25§C (Note 3) 500 mW
A
or I
OUT1
OUT2
65§Ctoa150§C
b
100 mV to V
DC
g
25V
CC
ESD Susceptibility (Note 11) 800V
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic) 260
Dual-In-Line Package (ceramic) 300
Operating Ratings (Note 1)
s
s
T
Temperature Range T
Part numbers with
MIN
‘‘LCN’’ and ‘‘LCWN’’ suffix 0
Voltage at Any Digital Input VCCto GND
T
A
MAX
Cto70§C
§
C
§
C
§
Electrical Characteristics
Tested at V
e
4.75 VDCand 15.75 VDC,T
CC
Parameter Conditions
Resolution 10 10 bits
Linearity Error Endpoint adjust only 4,7
Differential Endpoint adjust only 4,7
Nonlinearity T
Monotonicity T
Gain Error Using internal R
Gain Error Tempco T
Power Supply All digital inputs
Rejection latched high
Reference Input
Resistance 10 15 20 10 15 20 kX
Output Feedthrough V
Error All data inputs 90 90 mV
Output I
Capacitance I
OUT1
OUT2
I
OUT1
I
OUT2
Supply Current Drain T
k
k
T
T
MIN
b
DAC1006 0.05 0.05 % of FSR
DAC1007 0.1 0.1 % of FSR
DAC1008 0.2 0.2 % of FSR
MIN
b
DAC1006 0.1 0.1 % of FSR
DAC1007 0.2 0.2 % of FSR
DAC1008 0.4 0.4 % of FSR
MIN
b
DAC1006 10 10 bits
DAC1007 9 9 bits
DAC1008 8 8 bits
b
MIN
Using internal R
V
CC
REF
T
A
10VsV
10VsV
10VsV
10VsV
MAX
REF
k
k
T
T
A
MAX
REF
k
k
T
T
A
MAX
REF
REF
k
k
T
T
A
MAX
e
14.5V to 15.5V 0.003 0.008 % FSR/V
11.5V to 12.5V 0.004 0.010 % FSR/V
4.75V to 5.25V 0.033 0.10 % FSR/V
e
20V
p-p
latched low
All data inputs 60 60 pF
latched low 250 250 pF
All data inputs 250 250 pF
latched high 60 60 pF
s
s
T
MIN
T
A
MAX
e
25§C, V
A
s
a
10V 5
s
a
10V 5
s
a
10V 5
fb
s
a
10V 5b1.0g0.3 1.0
fb
e
10.000 VDCunless otherwise noted
REF
e
12V
V
See
Note
CC
to 15V
DC
Min. Typ. Max. Min. Typ. Max.
6
6
4,6
6
9
b
0.0003b0.001
,fe100 kHz
6 0.5 3.5 0.5 3.5 mA
g
5%
DC
g
5% Units
e
V
CC
b
1.0g0.3 1.0 % of FS
g
5V
5%
DC
b
0.0006b0.002 % of FS/§C
p-p
2
Electrical Characteristics
Tested at V
e
4.75 VDCand 15.75 VDC,T
CC
Parameter Conditions
Output Leakage T
Current I
OUT1
I
OUT2
Digital Input T
Voltages Low level
s
T
MIN
A
All data inputs
latched low 10 200 200 nA
All data inputs
latched high 200 200 nA
s
T
MIN
A
LCN and LCWM suffix 0.8, 0.8 0.7, 0.8 V
High level (all parts) 2.0 2.0 V
Digital Input T
Currents Digital inputs
MIN
s
T
A
Digital inputsl2.0V 1.0
Current Settling t
Time
Write and XFER t
Pulse Width T
Data Set Up Time t
Data Hold Time t
Control Set Up t
Time T
Control Hold Time t
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: For current switching applications, both I
degraded by approximately V
Note 5: Guaranteed at V
Note 6: T
Note 7: The unit ‘‘FSR’’ stands for ‘‘Full Scale Range.’’ ‘‘Linearity Error’’ and ‘‘Power Supply Rejection’’ specs are based on this unit to eliminate dependence on a
particular V
guarantees that after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within
0.05%
Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t
of only 100 ns. The entire write pulse must occur within the valid data interval for the specified tW,tDS,tDH, and tSto apply.
Note 9: Guaranteed by design but not tested.
Note 10: A 200 nA leakage current with R
Note 11: Human body model, 100 pF discharged through a 1.5 kX resistor.
e
MIN
REF
c
V
of a straight line which passes through zero and full scale.
REF
S
WVIL
DSVIL
DHVIL
CSVIL
CHVIL
REF
0§C and T
MAX
value and to indicate the true performance of the part. The ‘‘Linearity Error’’ specification of the DAC1006 is ‘‘0.05% of FSR (MAX).’’ This
e
V
0V, V
IL
e
0V, V
e
A
s
T
T
MIN
A
e
0V, V
e
T
A
s
T
T
MIN
A
e
OV, V
e
T
A
s
T
T
MIN
A
e
0V, V
e
A
s
T
T
MIN
A
e
0V, V
e
T
A
s
T
T
MIN
A
d
V
. For example, if V
OS
REF
e
g
10 VDCand V
e
70§C for ‘‘LCN’’ and ‘‘LCWM’’ suffix parts.
e
fb
REF
20K and V
e
25§C, V
A
s
T
MAX
s
T
MAX
s
T
MAX
k
0.8V
e
5V 500 500 ns
IH
e
5V,
IH
25§C 8 150 60 320 200 ns
s
T
MAX
e
5V,
IH
25§C 9 150 80 320 170 ns
s
T
MAX
e
5V
IH
25§C 9 200 100 320 220 ns
s
T
MAX
e
5V,
IL
25§C 9 150 60 320 180 ns
s
T
MAX
e
5V,
IH
25§C 9 10 0 10 0 ns
s
T
MAX
and I
OUT1
OUT2
e
10Vthena1mVoffset, VOS,onI
REF
e
g
1VDC.
e
10V corresponds to a zero error of (200c10
REF
e
10.000 VDCunless otherwise noted (Continued)
REF
e
g
12V
V
See
Note
CC
to 15V
Min. Typ. Max. Min. Typ. Max.
5%
DC
g
5% Units
DC
e
5V
DC
g
5%
V
CC
6
6
6
b
b
40
150
a
10 1.0
b
b
40
150 mA
a
10 mA
9 320 100 500 250 ns
320 120 500 250 ns
250 120 500 320 ns
320 100 500 260 ns
10 0 10 0 ns
must go to ground or the ‘‘Virtual Ground’’ of an operational amplifier. The linearity error is
OUT1
or I
will introduce an additional 0.01% linearity error.
OUT2
) of 320 ns. A typical part will operate with t
W
b
9
c
20c103)c100d10 which is 0.04% of FS.
DC
DC
DC
DC
W
3
Switching Waveforms
Typical Performance Characteristics
Errors vs. Supply Voltage Errors vs. Temperature Write Width, t
TL/H/5688– 2
W
Control Setup Time, t
Digital Threshold
vs. Supply Voltage
CS
Data Setup Time, t
4
DS
Digital Input Threshold
vs. Temperature
Data Hold Time, t
DH
TL/H/5688– 3
Block and Connection Diagrams
DAC1006/1007/1008 (20-Pin Parts)
DAC1006/1007/1008
(20-Pin Parts)
Dual-In-Line Package
Top View
See Ordering Information
USE DAC1006/1007/1008
FOR LEFT JUSTIFIED DATA
TL/H/5688– 5
DAC1006/1007/1008ÐSimple Hookup for a ‘‘Quick Look’’
*A TOTAL OF 10
INPUT SWITCHES
& 1K RESISTORS
Notes:
eb
1. For V
2. SW1 is a normally closed switch. While SW1 is closed, the DAC register is latched and new data
can be loaded into the input latch via the 10 SW2 switches.
When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes.
10.240 VDCthe output voltage steps are approximately 10 mV each.
REF
TL/H/5688– 28
TL/H/5688– 7
5
1.0 DEFINITION OF PACKAGE PINOUTS
R
1.1 Control Signals (All control signals are level actuated.)
: Chip Select Ð active low, it will enable WR.
CS
WR: Write Ð The active low WR is used to load the digital
data bits (DI) into the input latch. The data in the input latch
is latched when WR
is high. The 10-bit input latch is split
into two latches; one holds 8 bits and the other holds 2 bits.
The Byte1/Byte2
latches when Byte1/Byte2
control pin is used to select both input
e
1 or to overwrite the 2-bit input
latch when in the low state.
Byte1/Byte2
: Byte Sequence Control Ð When this control
is high, all ten locations of the input latch are enabled. When
low, only two locations of the input latch are enabled and
these two locations are overwritten on the second byte
write. On the DAC1006, 1007, and 1008, the Byte1/Byte2
must be low to transfer the 10-bit data in the input latch to
the DAC register.
XFER
: Transfer Control Signal, active low Ð This signal, in
combination with others, is used to transfer the 10-bit data
which is available in the input latch to the DAC register Ð
see timing diagrams.
1.2 Other Pin Functions
DI
(ie0 to 9): Digital Inputs Ð DI0is the least significant bit
i
(LSB) and DI
I
OUT1
digital input code of all 1s and is zero for a digital input code
is the most significant bit (MSB).
g
: DAC Current Output1ÐI
is a maximum for a
OUT1
of all 0s.
I
: DAC Current Output2ÐI
OUT2
I
,or
OUT1
I
OUT1
a
I
OUT2
1023 V
e
1024 R
REF
is a constant minus
OUT2
where Rj15 kX.
: Feedback Resistor Ð This is provided on the IC chip
FB
for use as the shunt feedback resistor when an external op
amp is used to provide an output voltage for the DAC. This
on-chip resistor should always be used (not an external resistor) because it matches the resistors used in the on-chip
R-2R ladder and tracks these resistors over temperature.
V
: Reference Voltage Input Ð This is the connection for
REF
the external precision voltage source which drives the R-2R
ladder. V
the analog voltage input for a 4-quadrant multiplying DAC
can range fromb10 toa10 volts. This is also
REF
application.
V
: Digital Supply Voltage Ð This is the power supply pin
CC
for the part. V
optimum for
independent of V
tics and Description in Section 3.0, T
can be froma5toa15 VDC. Operation is
CC
a
15V. The input threshold voltages are nearly
. (See Typical Performance Characteris-
CC
inputs.)
GND: Ground Ð the ground pin for the part.
1.3 Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC1006
10
has 2
or 1024 steps and therefore has 10-bit resolution.
Linearity Error: Linearity error is the maximum deviation
from a
straight line passing through the endpoints of the
DAC transfer characteristic.
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
National’s linearity test (a) and the ‘‘best straight line’’ test
(b) used by other suppliers are illustrated below. The ‘‘best
straight line’’ requires a special zero and FS adjustment for
each part, which is almost impossible for user to determine.
The ‘‘end point test’’ uses a standard zero and FS adjustment procedure and is a much more stringent test for DAC
linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output (which is the worst case).
a. End Point Test After Zero and FS Adj. b. Best Straight Line
2
L compatible logic
It is measured after adjusting
TL/H/5688– 8
6
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within
g
(/2 LSB of
the final output value. Full-scale settling time requires a zero
to full-scale or full-scale to zero output change.
Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC1006 series, full-scale is V
For V
LE
able to zero.
eb
10V and unipolar operation, V
REF
e
10.0000Vb9.8mVe9.9902V. Full-scale error is adjust-
b
REF
FULL-SCA-
1 LSB.
Monotonicity: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 10-bit
DAC with 10-bit monotonicity will produce an increasing analog output when all 10 digital inputs are exercised. A 10-bit
DAC with 9-bit monotonicity will be monotonic when only
the most significant 9 bits are exercised. Similarly, 8-bit
monotonicity is guaranteed when only the most significant 8
bits are exercised.
2.0 DOUBLE BUFFERING
These DACs are double-buffered, microprocessor compatible versions of the DAC1020 10-bit multiplying DAC. The
addition of the buffers for the digital input data not only allows for storage of this data, but also provides a way to
assemble the 10-bit input data word from two write cycles
when using an 8-bit data bus. Thus, the next data update for
the DAC output can be made with the complete new set of
10-bit data. Further, the double buffering allows many DACs
in a system to store current data and also the next data. The
updating of the new data for each DAC is also not time
critical. When all DACs are updated, a common strobe signal can then be used to cause all DACs to switch to their
new analog output levels.
3.0 TTL COMPATIBLE LOGIC INPUTS
To guarantee TTL voltage compatibility of the logic inputs, a
novel bipolar (NPN) regulator circuit is used. This makes the
input logic thresholds equal to the forward drop of two diodes (and also matches the temperature variation) as occurs naturally in TTL. The basic circuit is shown in
Figure 1
A curve of digital input threshold as a function of power
supply voltage is shown in the Typical Performance Characteristics section.
4.0 APPLICATION HINTS
The DC stability of the V
factor to maintain accuracy of the DAC over time and tem-
source is the most important
REF
perature changes. A good single point ground for the analog
signals is next in importance.
These MICRO-DAC converters are CMOS products and
reasonable care should be exercised in handling them prior
to final mounting on a PC board. The digital inputs are protected, but permanent damage may occur if the part is subjected to high electrostatic fields. Store unused parts in conductive foam or anti-static rails.
4.1 Power Supply Sequencing & Decoupling
Some IC amplifiers draw excessive current from the Analog
inputs to V
b
when the supplies are first turned on. To prevent damage to the DAC Ð an external Schottky diode connected from I
prevent destructive currents in I
or LF356 is used Ð these diodes are not required.
OUT1
or I
to ground may be required to
OUT2
OUT1
or I
. If an LM741
OUT2
The standard power supply decoupling capacitors which are
used for the op amp are adequate for the DAC.
.
FIGURE 1. Basic Logic Threshold Loop
7
TL/H/5688– 9
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