NSC DAC0854BIN, DAC0854CIWMX, DAC0854CIWM, DAC0854CIN, DAC0854CIJ Datasheet

TL/H/11261

DAC0854 Quad 8-Bit Voltage-Output Serial D/A Converter with Readback

January 1995

DAC0854 Quad 8-Bit Voltage-Output
Serial D/A Converter with Readback

General Description

The DAC0854 is a complete quad 8-bit voltage-output digi­tal-to-analog converter that can operate on a single 5V sup­ply. It includes on-chip output amplifiers, internal voltage ref­erence, and a serial microprocessor interface. By combining
in one package the reference, amplifiers, and conversion
circuitry for four D/A converters, the DAC0854 minimizes
wiring and parts count and is hence ideally suited for appli­cations where cost and board space are of prime concern.

The DAC0854 also has a data readback function, which can
be used by the microprocessor to verify that the desired
input word has been properly latched into the DAC0854’s
data registers. The data readback function simplifies the de­sign and reduces the cost of systems which need to verify
data integrity.

The logic comprises a MICROWIRE

TM

-compatible serial in­terface and control circuitry. The interface allows the user to
write to any one of the input registers or to all four at once.
The latching registers are double-buffered, consisting of 4
separate input registers and 4 DAC registers. Double buffer­ing allows all 4 DAC outputs to be updated simultaneously.

The four reference inputs allow the user to configure the
system to have a separate output voltage range for each
DAC. The output voltage of each DAC can range between

0.3V and 2.8V and is a function of V

BIAS,VREF

, and the

input word.

Features

Y

Singlea5V supply operation

Y

MICROWIRE serial interface allows easy interface to
many popular microcontrollers including the COPS

TM

and HPCTMfamilies of microcontrollers

Y

Data readback capability

Y

Output data can be formatted to read back MSB or
LSB first

Y

Versatile logic allows selective or global update of the
DACs

Y

Power fail flag

Y

Output amplifiers can drive 2 kX load

Y

Synchronous/asynchronous update of the DAC outputs

Key Specifications

Y

Guaranteed monotonic over temperature

Y

Integral linearity error

g

(/2 LSB max

Y

Output settling time 2.7 ms max

Y

Analog output voltage range 0.3V to 2.8V

Y

Supply voltage range 4.5V to 5.5V

Y

Clock frequency 10 MHz max

Y

Power dissipation (f

CLK

e

10 MHz) 95 mW max

Y

On-board reference 2.65Vg2% max

Applications

Y

Automatic test equipment

Y

Industrial process controls

Y

Automotive controls and diagnostics

Y

Instrumentation

Connection Diagram

TL/H/11261– 1

Top View

Ordering Information

Industrial (b40§CkT

A

a

85§C) Package

DAC0854BIN, DAC0854CIN N20A Molded DIP

DAC0854CIJ J20A Ceramic DIP

DAC0854BIWM, DAC0854CIWM M20B Small Outline

Military (b55§CkT

A

k

a

125§C)

DAC0854CMJ/883 J20A Ceramic DIP

COPSTM, HPCTMand MICROWIRETMare trademarks of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

(Note 24)

Supply Voltage (AV

CC

,DVCC)7V

Supply Voltage Difference (AV

CC

–DVCC)

g

5.5V

Voltage at Any Pin (Note 3) GNDb0.3V to

AV

CC

/DV

CC

a

0.3V

Input Current at Any Pin (Note 3) 5 mA

Package Input Current (Note 4) 20 mA

Power Dissipation (Note 5) 105 mW

ESD Susceptibility (Note 6) 1250V

Soldering Information

J Package (10 sec.) 300

§

C

N Package (10 sec.) 260

§

C

SO Package

Vapor Phase (60 sec.) 215

§

C

Infrared (15 sec.) (Note 7) 220

§

C

Storage Temperature

b

65§Ctoa150§C

Operating Ratings (Notes1&2)

Supply Voltage 4.5V to 5.5V

Supply Voltage Difference (AV

CC

b

DVCC)

g

IV

Temperature Range T

MIN

k

T

A

k

T

MAX

DAC0854BIN, DAC0854CIN,
DAC0854CIJ, DAC0854BIWM,
DAC0854CIWM

b

40§CkT

A

k

85§C

DAC0854CMJ/883

b

55§CkT

A

k

125§C

Converter Electrical Characteristics

The following specifications apply for AV

CC

e

DV

CC

e

5V, V

REF

e

2.65V, V

BIAS

e

1.4V, R

L

e

2kX(RLis the load resistor on

the analog outputs – pins 1, 11, 14, and 19) and f

CLK

e

10 MHz unless otherwise specified. Boldface limits apply for T

A

e

TJfrom T

MIN

to T

MAX

. All other limits apply for T

A

e

25§C.

Symbol Parameter Conditions

Typical Limit Units

(Note 8) (Note 9) (Limits)

STATIC CHARACTERISTICS

n Resolution f

CLK

e

10 MHz 8 8 bits

Monotonicity (Note 10) 8 8 bits

Integral Linearity Error (Note 11)

DAC0854BIN, DAC0854BIWM

g

0.5 LSB (max)

DAC0854CIN, DAC0854CIJ,
DAC0854CIWM, DAC0854CMJ

g

1.0 LSB (max)

Differential Linearity Error

g

1.0 LSB (max)

Fullscale Error (Note 12)

g

35 mV

Fullscale Error Tempco (Note 13)

b

30 ppm/§C

Zero Error (Note 14)

g

35 mV

Zero Error Tempco (Note 13)

b

30 ppm/§C

Power Supply Sensitivity (Note 15)

b

42

b

34 dB (max)

DYNAMIC CHARACTERISTICS

t

s

a

Positive Voltage Output (Note 16)

1.5 2.1 ms

Settling Time C

L

e

200 pF

t

s

b

Negative Voltage Output (Note 16)

1.8 2.7 ms

Settling Time C

L

e

200 pF

Digital Crosstalk (Note 17) 1.8 mV

p-p

Digital Feedthrough (Note 18) 8.5 mV

p-p

Clock Feedthrough (Note 19) 3.3 mV

p-p

Channel-to-Channel Isolation (Note 20)

b

78 dB

Glitch Energy (Note 21) 7 nVbs

Peak Value of Largest Glitch 38 mV

PSRR Power Supply Rejection Ratio (Note 22)

b

49 dB

2

Converter Electrical Characteristics (Continued)

The following specifications apply for AV

CC

e

DV

CC

e

5V, V

REF

e

2.65V, V

BIAS

e

1.4V, R

L

e

2kX(RLis the load resistor on

the analog outputs – pins 1, 11, 14, and 19) and f

CLK

e

10 MHz unless otherwise specified. Boldface limits apply for T

A

e

TJfrom T

MIN

to T

MAX

. All other limits apply for T

A

e

25§C.

Symbol Parameter Conditions

Typical Limit Units

(Note 3) (Note 4) (Limits)

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

V

IN(1)

Logical ‘‘1’’ Input Voltage AV

CC

e

DV

CC

e

5.5V 2.0 V (min)

V

IN(0)

Logical ‘‘0’’ Input Voltage AV

CC

e

DV

CC

e

4.5V 0.8 V (max)

I

IL

Digital Input Leakage Current 1 5 mA (max)

C

IN

Input Capacitance 4 pF

C

OUT

Output Capacitance 5 pF

V

OUT(1)

Logical ‘‘1’’ Output Voltage I

SOURCE

e

0.8 mA 2.4 V (min)

V

OUT(0)

Logical ‘‘0’’ Output Voltage I

SINK

e

3.2 mA 0.4 V (max)

V

INT

Interrupt Pin Output Voltage 10 kX Pullup 0.4 V (max)

I

S

Supply Current Outputs Unloaded 14 19 mA

REFERENCE INPUT CHARACTERISTICS

V

REF

Input Voltage Range 0–2.75 V

R

REF

Input Resistance 7 4 kX (min)

10 kX (max)

C

REF

Input Capacitance Full-Scale Data Input 40 pF

V

BIAS

INPUT CHARACTERISTICS

V

BIAS

V

BIAS

Input Voltage Range 0.3–1.4 V

Input Leakage 1 mA

C

BIAS

Input Capacitance 9 pF

BANDGAP REFERENCE CHARACTERISTICS (C

L

e

220mF)

V

REF

OUT Output Voltage 2.65g2% V

DV

REF

/DT Tempco (Note 23) 22 ppm/§C

Line Regulation 4.5VkV

CC

k

5.5V, I

L

e

4mA 2 5 mV

DV

REF

/DILLoad Regulation 0kI

L

k

4mA 2 6 mV

0

k

I

L

k

4 mA; CMJ Suffix 2 15 mV

b

1kI

L

k

0 mA 2.5 mV

I

SC

Short Circuit Current V

REF

OUTe0V 12 mA

AC ELECTRICAL CHARACTERISTICS

t

DS

Data Setup Time 10 ns (min)

t

DH

Data Hold Time 0 ns (min)

t

CS

Control Setup Time 15 ns (min)

t

CH

Control Hold Time 0 ns (min)

t

MIN

Clock Frequency 10 MHz (max)

t

H

Minimum Clock High Time 20 ns (min)

t

L

Minimum Clock Low Time 40 ns (min)

3

Converter Electrical Characteristics (Continued)

The following specifications apply for AV

CC

e

DV

CC

e

5V, V

REF

e

2.65V, V

BIAS

e

1.4V, R

L

e

2kX(RLis the load resistor on

the analog outputs – pins 1, 11, 14, and 19) and f

CLK

e

10 MHz unless otherwise specified. Boldface limits apply for T

A

e

TJfrom T

MIN

to T

MAX

. All other limits apply for T

A

e

25§C.

Symbol Parameter Conditions

Typical Limit Units

(Note 3) (Note 4) (Limits)

AC ELECTRICAL CHARACTERISTICS (Continued)

t

CZ1

Output Hi-Z to Valid 1 37 ns (max)

t

CZ0

Output Hi-Z to Valid 0 42 ns (max)

t

1H

CS to Output Hi-Z 10 kX with 60 pF 130 ns (max)

t

0H

CS to Output Hi-Z 10 kX with 60 pF 117 ns (max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Converter Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not
operated under the listed test conditions.

Note 2: All voltages are measured with respect to ground, unless otherwise specified.

Note 3: When the input voltage (V

IN

) at any pin exceeds the power supply rails (V

IN

k

GND or V

IN

l

Va) the absolute value of current at that pin should be limited

to 5 mA or less.

Note 4: The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA.

Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

Jmax

(maximum junction temperature), H

JA

(package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any temperature is
P

Dmax

e

(T

Jmax

b

TA)/HJAor the number given in the Absolute Maximum Ratings, whichever is lower. The table below details T

Jmax

and HJAfor the various

packages and versions of the DAC0854.

Part Number T

Jmax

(§C) HJA(§C/W)

DAC0854BIN, DAC0854CIN 125 46
DAC0854BIJ, DAC0854CIJ 125 53
DAC0854BIWM, DAC0854CIWM 125 64
DAC0854CMJ/883 150 53

Note 6: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 7: See AN450 ‘‘Surface Mounting Methods and Their Effect on Production Reliability’’ of the section titled ‘‘Surface Mount’’ found in any current Linear

Databook for other methods of soldering surface mount devices.

Note 8: Typicals are at T

J

e

25§C and represent most likely parametric norm.

Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 10: A monotonicity of 8 bits for the DAC0854 means that the output voltage changes in the same direction (or remains constant) for each increase in the input

code.

Note 11: Integral linearity error is the maximum deviation of the output from the line drawn between zero and full-scale (excluding the effects of zero error and full­scale error).

Note 12: Full-scale error is measured as the deviation from the ideal 2.800V full-scale output when V

REF

e

2.650V and V

BIAS

e

1.400V.

Note 13: Full-scale error tempco and zero error tempco are defined by the following equation:

Error tempco

e

Ð

Error (T

MAX

)bError (T

MIN

)

V

SPAN

(Ð

10

6

T

MAX

b

T

MIN

(

where Error (T

MAX

) is the zero error or full-scale error at T

MAX

(in volts), and Error (T

MIN

) is the zero error or full-scale error at T

MIN

(in volts); V

SPAN

is the output

voltage span of the DAC0854, which depends on V

BIAS

and V

REF

.

Note 14: Zero error is measured as the deviation from the ideal 0.310V output when V

REF

e

2.650V, V

BIAS

e

1.400V, and the digital input word is all zeros.

Note 15: Power Supply Sensitivity is the maximum change in the offset error or the full-scale error when the power supply differs from its optimum 5V by up to

0.25V (5%). The load resistor R

L

e

5kX.

Note 16: Positive or negative settling time is defined as the time taken for the output of the DAC to settle to its final full-scale or zero output to within

g

0.5 LSB.

This time shall be referenced to the 50% point of the positive edge of CS

, which initiates the update of the analog outputs.

Note 17: Digital crosstalk is the glitch measured on the output of one DAC while applying an all 0s to all 1s transition at the input of the other DACs.

Note 18: All DACs have full-scale outputs latched and DI is clocked with no update of the DAC outputs. The glitch is then measured on the DAC outputs.

Note 19: Clock feedthrough is measured for each DAC with its output at full-scale. The serial clock is then applied to the DAC at a frequency of 10 MHz and the

glitch on each DAC full-scale output is measured.

Note 20: Channel-to-channel isolation is a measure of the effect of a change in one DAC’s output on the output of another DAC. The V

REF

of the first DAC is varied

between 1.4V and 2.65V at a frequency of 15 kHz while the change in full-scale output of the second DAC is measured. The first DAC is loaded with all 0s.

Note 21: Glitch energy is the difference between the positive and negative glitch areas at the output of the DAC when a 1 LSB digital input code change is applied
to the input. The glitch energy will have its largest value at one of the three major transitions. The peak value of the maximum glitch is separately specified.

Note 22: Power Supply Rejection Ratio is measured by varying AV

CC

e

DVCCbetween 4.75V and 5.25V with a frequency of 10 kHz and measuring the proportion

of this signal imposed on a full-scale output of the DAC under consideration.

Note 23: The bandgap reference tempco is defined by the following equation:

Tempco

e

Ð

V

REF(TMAX

)bV

REF(TMIN

)

V

REF(TROOM

)

(Ð

10

6

T

MAX

b

T

MIN

(

where T

ROOM

e

25§C, V

REF(TMAX

) is the reference output at T

MAX

, and similarly for V

REF(TMIN

) and V

REF(TROOM

).

Note 24: A Military RETS specification is available upon request.

4

Typical Converter Performance Characteristics

Temperature

Zero Error vs

vs Temperature

Full-Scale Error

vs Temperature

Supply Current

vs Temperature

Zero Error PSRR

vs Temperature

Full-Scale Error PSRR

Clock Frequency

Supply Current vs

TL/H/11261– 2

Typical Reference Performance Characteristics

Bandgap Voltage
vs Temperature

TL/H/11261– 3

Line Regulation
vs Temperature

TL/H/11261– 4

5