NSC COPGW888V, COPGW888DWF Datasheet
TL/DD12065
COP888GW 8-Bit Microcontroller with Pulse Train Generators and Capture Modules
PRELIMINARY
September 1996
COP888GW
8-Bit Microcontroller with Pulse Train Generators
and Capture Modules
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor’s M
2
CMOSTMprocess technology. The COP888GW is a
member of this expandable 8-bit core processor family of
microcontrollers. It is a fully static part, fabricated using double-metal silicon gate microCMOS technology.
Features include an 8-bit memory mapped architecture, MICROWIRE/PLUS serial I/O, two 16-bit timer/counters supporting three modes (Processor Independent PWM generation, External Event counter and Input Capture mode capabilities), four independent 16-bit pulse train generators with
16-bit prescalers, two independent 16-bit input capture
modules with 8-bit prescalers, multiply and divide functions,
full duplex UART, and two power savings modes (HALT and
IDLE), both with a multi-sourced wake up/interrupt capability. This multi-sourced interrupt capability may also be used
independent of the HALT or IDLE modes.
Each I/O pin has software selectable configurations. The
devices operate over a voltage range of 2.5V –6V. High
throughput is achieved with an efficient, regular instruction
set operating at a maximum of 1 ms per instruction rate. The
device has low EMI emissions. Low radiated emissions are
achieved by gradual turn-on output drivers and internal I
CC
filters on the chip logic and crystal oscillator. The device is
available in 68-pin PLCC package.
Key Features
Y
Two 16-bit input capture modules with 8-bit prescalers
Y
Four Pulse Train Generators with 16-bit prescalers
Y
Full duplex UART
Y
Two 16-bit timers, each with two 16-bit registers
supporting:
Ð Processor independent PWM mode
Ð External event counter mode
Ð Input capture mode
Y
Quiet design (low radiated emissions)
Y
16 kbytes on-board ROM
Y
512 bytes on-board RAM
Additional Peripheral Features
Y
Idle Timer
Y
Multi-Input Wake-Up (MIWU) with optional interrupts (8)
Y
MICROWIRE/PLUSTMserial I/O
I/O Features
Y
Memory mapped I/O
Y
Software selectable I/O options (TRI-STATEÉOutput,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
Y
Schmitt trigger inputs on port G
Y
Package: 68-pin PLCC
CPU/Instruction Set Features
Y
1 ms instruction cycle time
Y
Fourteen multi-source vectored interrupts servicing:
Ð External Interrupt with selectable edge
Ð Idle Timer T0
Ð Two Timers (each with 2 interrupts)
Ð MICROWIRE/PLUS
Ð Multi-Input Wake-Up
Ð Software Trap
Ð UART (2)
Ð Capture Timers
Ð Counters (one vector for all four counters)
Ð Default VIS (default interrupt)
Y
Versatile and easy-to-use instruction set
Y
8-bit Stack Pointer SPÐ(stack in RAM)
Y
Two 8-bit register indirect data memory pointers
(B and X)
Fully Static CMOS
Y
Two power saving modes: HALT and IDLE
Y
Low current drain (typicallyk1 mA)
Y
Single supply operation: 2.5V –5.5V
Y
Temperature range:b40§Ctoa85§C
Development Support
Y
Emulation and OTP device
Y
Real time emulation and full program debug offered by
MetaLink’s Development System
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
M
2
CMOSTM, MICROWIRE/PLUSTM, COPSTM, MICROWIRETMand WATCHDOGTMare trademarks of National Semiconductor Corporation.
IBM
É
,PCÉ, PC-ATÉand PC/XTÉare registered trademarks of International Business Machines Corporation.
iceMASTER
TM
is a trademark of MetaLink Corporation.
C
1996 National Semiconductor Corporation RRD-B30M106/Printed in U. S. A.
http://www.national.com
Block Diagram
TL/DD/12065– 1
FIGURE 1. COP888GW Block Diagram
Connection Diagram
TL/DD/12065– 2
Top View
Order Number COP888GW-XXX/V
See NS Package Number V68A
http://www.national.com 2
Absolute Maximum Ratings (Note)
SuppIy Voltage (V
CC
)7V
Voltage at Any Pin
b
0.3V to V
CC
a
0.3V
Total Current into VCCPin (Source) 100 mA
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range
b
65§Ctoa150§C
Note:
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics COP888GW:
b
40§CsT
A
s
a
85§C unless otherwise specified
Parameter ConditIons Min Typ Max UnIts
Operating Voltage 2.5 6.0 V
Power Supply Ripple (Note 1) Peak-to-Peak 0.1 V
CC
V
Supply Current (Note 2)
CKI
e
10 MHz V
CC
e
6V, t
c
e
1 ms10mA
CKI
e
4 MHz V
CC
e
2.5V, t
c
e
2.5 ms 1.7 mA
HALT Current (Note 3) V
CC
e
6V, CKIe0 MHz
k
110mA
IDLE Current
CKI
e
10 MHz V
CC
e
6V 1.7 mA
CKI
e
4 MHz V
CC
e
2.5V 0.4 mA
Input Levels (V
IH,VIL
)
RESET
, CKI
Logic High 0.8 V
CC
V
Logic Low 0.2 V
CC
V
All Other Inputs
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
Hi-Z Input Leakage V
CC
e
6V
b
2
a
2 mA
Input Pullup Current V
CC
e
6V, V
IN
e
0V
b
40
b
250 mA
G Port Input Hysteresis (Note 6) 0.05 V
CC
0.35 V
CC
V
Output Current Levels
D Outputs
Source V
CC
e
4V, V
OH
e
3.3V
b
0.4 mA
V
CC
e
2.5V, V
OH
e
1.8V
b
0.2 mA
Sink V
CC
e
4V, V
OL
e
1V 10 mA
V
CC
e
2.5V, V
OL
e
0.4V 2.0 mA
All Others
Source (Weak Pull-Up Mode) V
CC
e
4V, V
OH
e
2.7V
b
10
b
100 mA
V
CC
e
2.5V, V
OH
e
1.8V
b
2.5
b
33 mA
Source (Push-Pull Mode) V
CC
e
4V, V
OH
e
3.3V
b
0.4 mA
V
CC
e
2.5V, V
OH
e
1.8V
b
0.2 mA
Sink (Push-Pull Mode) V
CC
e
4V, V
OL
e
0.4V 1.6 mA
V
CC
e
2.5V, V
OL
e
0.4V 0.7 mA
TRI-STATE Leakage V
CC
e
6.0V
b
2
a
2 mA
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3mA
Maximum Input Current Room Temp
g
200 mA
without Latchup (Note 4, 6)
RAM Retention Voltage, VR(Note 5) 500 ns Rise and Fall Time (min) 2 V
Input Capacitance (Note 6) 7 pF
Load Capacitance on D2 (Note 6) 1000 pF
http://www.national.com3
AC Electrical Characteristics COP888GW:
b
40§CsT
A
s
a
85§C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc)
Crystal, Resonator 2.5V
s
V
CC
k
4V 2.5 DC ms
Ceramic V
CC
t
4V 1.0 DC ms
CKI Clock Duty Cycle (Note 5) feMax 40 60 %
Rise Time (Note 5) f
e
10 MHz Ext Clock 5 ms
Fall Time (Note 5) fe10 MHz Ext Clock 5 ms
Inputs
t
SETUP
V
CC
t
4V 200 ns
2.5V
s
V
CC
k
4V 500 ns
t
HOLD
V
CC
t
4V 60 ns
2.5V
s
V
CC
k
4V 150 ns
Output Propagation Delay (Note 8) R
L
e
2.2k, C
L
e
100 pF
t
PD1,tPD0
SO, SK V
CC
t
4V 0.7 ms
2.5V
s
V
CC
k
4V 1.8 ms
All Others V
CC
t
4V 1 ms
2.5V
s
V
CC
k
4V 2.5 ms
MICROWIRETMSetup Time (t
UWS
) (Note 6) V
CC
t
4V 20 ns
MICROWIRE Hold Time (t
UWH
) (Note 6) V
CC
t
4V 56 ns
MICROWIRE Output Propagation Delay (t
UPD
)V
CC
t
4V 220 ns
Input Pulse Width (Note 7)
Interrupt Input High Time 1 t
c
Interrupt Input Low Time 1 t
c
Timer 1, 2 Input High Time 1 t
c
Timer 1, 2 Input Low Time 1 t
c
Capture Timer High Time 1 CKI
Capture Timer Low Time 1 CKI
Reset Pause Width 1 t
c
Note 1: Maximum rate of voltage change to be defined.
Note 2: Supply current is measured after running 2000 cydes with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillatng. Test conditions: All inputs tied to V
CC
, L, C, E, F, and G port I/O’s configured as outputs and programmed
low and not driving a load; D outputs programmed low and not driving a load. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Part will pull up CKI during HALT in crystal clock mode.
Note 4: Pins G6 and RESET
are designed with a high voltage input network. These pins allow input voltages greater than VCCand the pins will have sink current to
V
CC
when biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC.) The effective resistance to VCCis 750X
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14 volts. WARNING: Voltages in excess of 14 volts will cause damage
to the pins. This warning excludes ESD transients.
Note 5: Condition and parameter valid only for part in HALT mode.
Note 6: Parameter characterized but not tested.
Note 7: t
c
e
Instruction Cycle Time
Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
TL/DD/12065– 3
FIGURE 2. MICROWIRE/PLUS Timing
http://www.national.com 4
Typical Performance Characteristics
b
40§CsT
A
s
a
85§C
Port D Source Current
TL/DD/12065– 23
Port D Sink Current
TL/DD/12065– 24
Ports C/G/L/E/F Source Current
TL/DD/12065– 25
Ports C/G/L/E/F Sink Current
TL/DD/12065– 26
Ports C/G/L/E/F Weak Pull-Up Source Current
TL/DD/12065– 27
Dynamic Ð IDDvs V
CC
TL/DD/12065– 28
Idle Ð IDDvs V
CC
TL/DD/12065– 29
HALT Ð IDDvs V
CC
TL/DD/12065– 30
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Pin Descriptions
VCCand GND are the power supply pins. All VCCand GND
pins must be connected.
CKI is the clock input. This comes from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
RESET
is the master reset input. See Reset description
section.
The device contains five bidirectional 8-bit I/O ports (C, E,
F, G and L), where each individual bit may be independently
configured as an input (Schmitt trigger inputs on ports L and
G), output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.)
Figure 3
shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
Configuration Data
Port Set-Up
Register Register
0 0 Hi-Z Input (TRI-STATE Output)
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
The Port L supports Multi-Input Wake Up on all eight pins.
L1 is used for the UART external clock. L2 and L3 are used
for the UART transmit and receive. L4 and L5 are used for
the timer input functions T2A and T2B. L6 and L7 are used
for the capture timer input functions CAP1 and CAP2.
The Port L has the following alternate features:
L0 MIWU
L1 MIWU or CKX
L2 MIWU or TDX
L3 MIWU or RDX
L4 MIWU or T2A
L5 MIWU or T2B
L6 MIWU or CAP1
L7 MIWU or CAP2
Port G is an 8-bit port with 6 I/O pins (G0– G5), an input pin
(G6), and a dedicated output pin (G7). Pins G0– G6 all have
Schmitt Triggers on their inputs. Pin G7 serves as the dedicated output pin for the CKO clock output. There are two
registers associated with the G Port, a data register and a
configuration register. Therefore, each of the 6 I/O bits
(G0–G5) can be individually configured under software control.
TL/DD/12065– 4
FIGURE 3. I/O Port Configurations
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Pin Descriptions (Continued)
Since G6 is an input only pin and G7 is dedicated CKO clock
output pin, the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits
will return zeros.
Note that the chip will be placed in the HALT mode by writing a ‘‘1’’ to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register.
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock.
Config Reg. Data Reg.
G7 Not Used HALT
G6 Alternate SK IDLE
Port G has the following alternate features:
G0 INTR (ExternaI Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I/O)
G4 SO (MICROWIRE Serial Data Output)
G5 SK (MICROWIRE SeriaI Clock)
G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions:
G7 CKO OsciIlator dedicated output
Ports C and F are 8-bit I/O ports.
Port E is an 8-bit I/O port. It has the following alternate
features:
E0 CT1 (Output for counter1, PuIse Train Generator)
E1 CT2 (Output for counter2, Pulse Train Generator)
E2 CT3 (Output for counter3, PuIse Train Generator)
E3 CT4 (Output for counter4, Pulse Train Generator)
Port I is an eight-bit Hi-Z input port.
Port D is an 8-bit output port that is preset high when
RESET
goes Iow. The user can tie two or more D port out-
puts (except D2) together in order to get a higher drive.
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate
addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (t
c
) cycle time.
There are six CPU registers:
A is the 8-bit Aocumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
S is the 8-bit Data Segment Address Register used to extend the Iower haIf of the address range (00 to 7F) into 256
data segments of 128 bytes each.
All the CPU registers are memory mapped with the exception of the AccumuIator (A) and the Program Counter (PC).
PROGRAM MEMORY
The program memory consists of 16384 bytes of ROM.
These bytes may hoId program instructions or constant data
(data tables for the LAID instruction, jump vectors for the
JID instruction, and interrupt vectors for the VIS instruction).
The program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices Vector to program
memory location OFF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the B, X, SP pointers and S register.
The data memory consists of 512 bytes of RAM. Sixteen
bytes of RAM are mapped as ‘‘registers’’ at addresses 0F0
to 0FF Hex. These registers can be loaded immediately,
and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory
pointer registers X, SP, B and S are memory mapped into
this space at address locations 0FC to 0FF Hex respectively, with the other registers being available for general usage.
Note: RAM contents are undefined upon power-up.
Data Memory Segment RAM
Extension
Data memory address 0FF is used as a memory mapped
location for the Data Segment Address Register (S).
The data store memory is either addressed directly by a
single-byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previously. With the exception of the RAM register memory from
address locations 00F0 to 00FF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to 00FF) is extended. If this upper bit
equals one (representing address range 0080 to 00FF),
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension
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Data Memory Segment RAM Extension (Continued)
register S is used to extend the base address range (from
0000 to 007F) from XX00 to XX7F, where XX represents the
8 bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 to 017F for
data segment 1, 0200 to 027F for data segment 2, etc., up
to FF00 to FF7F for data segment 255. The base address
range from 0000 to 007F represents data segment 0.
Figure 4
illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data segments of 128-bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
availabIe for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers,
controI registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data segment extension.
The instructions that utilize the stack pointer (SP) always
reference the stack as part of the base segment (Segment
0), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the
stack (used with subroutine linkage and interrupts) is always
located in the base segment. The stack pointer will be initialized to point at data memory location 006F as a result of
reset.
The 128 bytes of RAM contained in the base segment are
split between the Iower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F
in the Iower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 384 bytes of RAM
in this device are memory mapped at address locations
0100 to 017F
§
0200 to 027F, and 0300 to 037F hex.
TL/DD/12065– 5
*Reads as all ones.
FIGURE 4. RAM Organization
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Reset
This device enters a reset state immediately upon detecting
a logic low on the RESET
pin. The RESET pin must be held
low for a minimum of one instruction cycle to guarantee a
valid reset. During power-up initialization, the user must insure that the RESET
pin is held low until this device is within
the specified V
CC
voltage. An R/C circuit on the RESET pin
with a delay 5 times (5x) greater than the power supply rise
time is recommended.
When the RESET
input goes low, the I/O ports are initialized immediately, with any observed delay being only propagation delay. When the RESET
pin goes high, this device
comes out of the reset state synchronously. This device will
be running within two instruction cycles of the RESET
pin
going high.
RESET
may also be used to exit this device from the HALT
mode.
Some registers are reset to a known state, whereas other
registers and RAM are ‘‘unchanged’’ by reset. When the
controller goes into reset state while it is performing a write
operation to one of these registers or RAM that are ‘‘unchanged’’ by reset, the register or RAM value will become
unknown (i.e. not unchanged). This is because the write operation is terminated prematurely by reset and the results
become uncertain. These registers and RAM locations are
unchanged by reset only if they are not written to when the
controller resets.
The following initializations occur with RESET
:
Port L: TRI-STATE
Port C: TRI-STATE
Port G: TRI-STATE
Port E: TRI-STATE
Port F: TRI-STATE
Port D: HIGH
PC: CLEARED
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
T1CNTRL: CLEARED
T2CNTRL: CLEARED
TxRA, TxRB: RANDOM
CCMR1, CCMR2: CLEARED
CM1PSC, CM1CRL, CM1CRH, CM2PSC, CM2CRL, and
CM2CRH:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
CCR1 and CCR2: CLEARED
CxPRH, CxPRL, CxCTH, and CxCTL:
UNAFFECTED after RESET with RC clock option (power
already applied)
RANDOM after RESET at power-on
PSR, ENUR and ENUI: CLEARED
ENU: CLEARED except Bit 1 (TBMT)
e
1
Accumulator, Timer 1 and Timer 2:
RANDOM after RESET with crystal clock option (power already applied)
RANDOM after RESET at power-on
MDCR: CLEARED
MDR1, MDR2, MDR3, MDR4, MDR5: RANDOM
WKEN, WKEDG: CLEARED
WKPND: RANDOM
S Register: CLEARED
SP (Stack Pointer): Loaded with 6F Hex
B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
RAM:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
The external RC network shown in
Figure 5
should be used
to ensure that the RESET
pin is held low until the power
supply to the chip stabilizes.
TL/DD/12065– 6
RCl5cPOWER SUPPLY RISE TIME
FIGURE 5. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration), The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (t
c
).
Figure 6
shows the Crystal diagram
TL/DD/12065– 7
FIGURE 6. Crystal Diagram
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
http://www.national.com9
Oscillator Circuits (Continued)
Table I shows the component values required for various
standard crystal values.
TABLE I. CrystaI Oscillator Configuration, T
A
e
25§C
R1 R2 C1 C2 CKI Freq
Conditions
(kX)(MX) (pF) (pF) (MHz)
0 1 30 30– 36 10 V
CC
e
5V
0 1 30 30– 36 4 V
CC
e
5V
0 1 200 100 – 150 0.455 V
CC
e
5V
Control Registers
CNTRL Register (Address X’00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide by
(00
e
2, 01e4, 1xe8)
IEDG External interrupt edge polarity select (0eRis-
ing edge, 1
e
Falling edge)
MSEL Selects G5 and G4 as MICROWIRE/PLUS sig-
nals SK and SO respectively
T1C0 Timer T1 Start/Stop control in timer modes
1 and 2
T1 Underflow Interrupt Pending Flag in timer
mode 3
T1C1 Timer T1 mode control bit
T1C2 Timer T1 mode control bit
T1C3 Timer T1 mode control bit
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7 Bit 0
PSW Register (Address X’00EF)
The PSW register contains the following select bits:
GIE GIobaI interrupt enable (enables interrupts)
EXEN EnabIe externaI interrupt
BUSY MICROWIRE/PLUS busy shifting flag
EXPND ExternaI interrupt pending
T1ENA Timer T1 Interrupt Enable for Timer Underflow or
T1A Input capture edge
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture
edge in mode 3)
C Carry FIag
HC Half Carry Flag
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0
The Half-Carry fIag is aIso affected by aII the instructions
that affect the Carry fIag. The SC (Set Carry) and RC (Reset
Carry) instructions wilI respectiveIy set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry fIags.
ICNTRL Register (Address X’00E8)
The ICNTRL register contains the foIlowing bits:
T1ENB Timer T1 Interrupt Enable for T1B Input capture
edge
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture
edge
mWEN EnabIe MICROWIRE/PLUS interrupt
mWPND MICROWIRE/PLUS interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
T0PND Timer T0 Interrupt pending
LPEN L Port Interrupt Enable (Multi-Input Wake up/In-
terrupt)
Bit 7 couId be used as a flag
Unused LPEN T0PND T0EN WPND WEN T1PNDB T1ENB
Bit 7 Bit 0
T2CNTRL Register (Address X’00C6)
The T2CNTRL register contains the following bits:
T2ENB Timer T2 Interrupt Enable for T2B Input capture
edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B capture
edge
T2ENA Timer T2 Interrupt Enable for Timer Underflow or
T2A Input capture edge
T2PNDA Timer T2 Interrupt Pending Flag (Auto reload RA
in mode 1, T2 Underflow in mode 2, T2A capture
edge in mode 3)
T2C0 Timer T2 Start/Stop control in timer modes 1 and
2 Timer T2 Underflow Interrupt Pending Flag in
timer mode 3
T2C1 Timer T2 mode control bit
T2C2 Timer T2 mode control bit
T2C3 Timer T2 mode control bit
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Bit 7 Bit 0
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Timers
The device contains a very versatile set of timers (T0, T1,
T2). All timers and associated autoreload/capture registers
power up containing random data.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
reaI time and Iow power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed
rate of the instruction cycle cIock, t
c
. The user cannot read
or write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
#
Exit out of the Idle Mode (See Idle Mode description)
#
Start up delay out of the HALT mode
The IDLE Timer T0 can generate an interrupt when the thirteenth bit toggIes. This toggle is Iatched into the T0PND
pending flag, and wiIl occur every 4 ms at the maximum
clock frequency (t
c
e
1 ms). A control flag T0EN allows the
interrupt from the thirteenth bit of Timer T0 to be enabled or
disabIed. Setting T0EN will enable the interrupt, while resetting it will disable the interrupt.
TIMER T1 AND TIMER T2
The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2 are identical, all comments are equally applicable to either of the two timer
blocks.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and
Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The
user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely independent of the microcontroller. The user software services the
timer block only when the PWM parameters require updating.
In this mode the timer Tx counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Figure 7
shows a block diagram of the timer in PWM mode.
The underfIows can be programmed to toggle the TxA output pin. The underfIows can also be programmed to generate interrupts.
UnderfIows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending fIags under software control. Two control enabIe fIags, TxENA and TxENB, alIow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA wilI cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
Mode 2. ExternaI Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is cIocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are Iatched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
TL/DD/12065– 8
FIGURE 7. Timer in PWM Mode
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Timers (Continued)
TL/DD/12065– 9
FIGURE 8. Timer in External Event Counter Mode
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 8
shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed
t
c
rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively Iatched into the
pending flags, TxPNDA and TxPNDB.
The control flag TxENA allows the interrupt on TxA to be
either enabled or disabled. Setting the TxENA flag enables
interrupts to be generated when the selected trigger condition occurs on the TxA pin. Similarly, the flag TxENB controls the interrupts from the TxB pin.
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 9
shows a block diagram of the timer in Input Capture
mode.
TL/DD/12065– 10
FIGURE 9. Timer in Input Capture Mode
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Timers (Continued)
TIMER CONTROL FLAGS
The timers T1 and T2 have identical control structures. The
control bits and their functions are summarized below.
TxC0 Timer Start/Stop controI in Modes 1 and 2 (Proc-
essor Independent PWM and External Event
Counter), where 1
e
Start, 0eStop Timer UnderfIow Interrupt Pending Flag in Mode 3 (Input
Capture)
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
TxENA Timer Interrupt Enable FIag
TxENB Timer Interrupt Enable Flag
1
e
Timer Interrupt EnabIed
0eTimer Interrupt Disabled
TxC3 Timer mode controI
TxC2 Timer mode control
TxC1 Timer mode controI
The timer mode controI bits (TxC3, TxC2 and TxC1) are
detailed beIow:
Capture Timer
This device contains two independent capture timers, Capture Timer 1 and Capture Timer 2. Each capture timer contains an 8-bit programmable prescaler register, a 16-bit
down counter, a 16-bit input capture register, and capture
edge select Iogic. The 16-bit down counter is clocked at a
specific frequency determined by the value loaded into the
prnscaler register. A selected positive or negative edge
transition on the capture input causes the contents of the
down counter to be latched into the capture register. The
values captured in the registers reflect the eIapsed time between two positive or two negative transitions on the capture input. The time between a positive and negative edge
(a pulse width) may be measured if the selected capture
edge is switched after the first edge is captured. Each capture timer may be stopped/started under software control,
and each capture timer may be configured to interrupt the
microcontroller on an underflow or input capture.
Figure 10
shows the capture timer 1 block diagram.
TABLE II. Timer Mode Control
TxC3 TxC2 TxC1 Timer Mode
Interrupt A Interrupt B Timer
Source Source Counts On
0 0 0 MODE 2 (External Event Counter) Timer Underflow Positive TxB Edge TxA Positive Edge
0 0 1 MODE 2 (External Event Counter) Timer Underflow Positive TxB Edge TxA Negative Edge
1 0 1 MODE 1 (PWM) TxA Toggle Autoreload RA Autoreload RB t
c
1 0 0 MODE 1 (PWM) No TxA Toggle Autoreload RA Autoreload RB t
c
0 1 0 MODE 3 (Capture) Captures: Positive TxA Edge or Positive TxB Edge t
c
TxA Positive Edge Timer Underflow
TxB Positive Edge
1 1 0 MODE 3 (Capture) Captures: Positive TxA Edge or Negative TxB Edge t
c
TxA Positive Edge Timer Underflow
TxB Negative Edge
0 1 1 MODE 3 (Capture) Captures: Negative TxA Edge or Positive TxB Edge t
c
TxA Negative Edge Timer Underflow
TxB Positive Edge
1 1 1 MODE 3 (Capture) Captures: Negative TxA Edge or Negative TxB Edge t
c
TxA Negative Edge Timer Underflow
TxB Negative Edge
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Timers (Continued)
TL/DD/12065– 11
FIGURE 10. Capture Timer 1 Block Diagram
The registers shown in the block diagram include those for
Capture Timer 1 (CM1), as well as, the capture timer 1 control register. These registers are read/writable (with the exception of the capture registers, which are read-only) and
may be accessed through the data memory address/data
bus. The registers are designated as:
CM1PSC Capture Timer 1 Prescaler (8-bit)
CM1CRL Capture Timer 1 Capture Register (Low-byte),
read-only
CM1CRH Capture Timer 1 Capture Register (High-byte),
read-only
CM2PSC Capture Timer 2 Prescaler (8-bit)
CM2CRL Capture Timer 2 Capture Register (Low-byte),
read-only
CM2CRH Capture Timer 2 Capture Register (High-byte),
read-only
CCMR1 Control Register for Capture Timer 1
CCMR2 Control Register for Capture Timer 2
CONTROL REGISTER BITS
The control bits for Capture Timer 1 (CM1) and Capture
Timer 2 (CM2) are contained in CCMR1 and CCMR2.
The CCMR1 Register Bits are:
CM1RUN CM1 start/stop control bit (1
e
start; 0estop)
CM1IEN CM1 interrupt enable control bit (1eenable
IRQ)
CM1IP1 CM1 interrupt pending bit 1 (1
e
CM1 under-
flowed)
CM1IP2 CM1 interrupt pending bit 2 (1
e
CM1 captured)
CM1EC Select the active edge for capture on CM1 (0
e
rising, 1efalling)
CM1TM CM1 test mode control bit (1especial test path
in test mode. This bit is reserved during normal
operation, and must never be set to one.)
CM1 un- un- CM1 CM1 CM1 CM1 CM1
TM used used EC IP2 IP1 IEN RUN
Bit 7 Bit 0
All interrupt pending bits must be reset by software.
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