NSC CLC533MDC, CLC533AJP, CLC533AJE-TR13, CLC533AJE, 5962-9320301MEA Datasheet

Features

■

12-bit settling (0.01%) – 17ns

■

Low noise – 42µVrms

■

Isolation – 80dB @ 10MHz

■

110MHz -3dB bandwidth (Av= +2)

■

Low distortion – 80dB @ 5MHz

■

Adjustable bandwidth – 180MHz (max)

Applications

■

Infrared system multiplexing

■

CCD sensor signals

■

Radar I/Q switching

■

High definition video HDTV

■

Test and calibration

Functional Diagram

Pinout

DIP & SOIC

General Description

The CLC533 is a high-speed 4:1 multiplexer employing active
input and output stages. The CLC533 also employs a closed-loop
design which dramatically improves accuracy over conventional
analog multiplexer circuits. This monolithic device is constructed
using an advanced high-performance bipolar process.

The CLC533 has been specifically designed to provide a 24ns
settling time to 0.01%. This coupled with the adjustable band­width, makes the CLC533 an ideal choice for infrared and CCD
imaging systems, with channel-to-channel isolation of 80dB @
10MHz. Low distortion and spurious signal levels (-80dBc) make
the CLC533 a very suitable choice for I/Q processors in radar
receivers.

The CLC533 is offered over both the industrial and militar y tem­perature ranges. The industrial versions, CLC533AJP\AJE\AIB,
are specified from -40°C to +85°C and are packaged in 16-pin
plastic DIPs, SOIC’s and CERDIP packages. The extended tem­perature versions, CLC533A8B/A8L-2A, are specified from -55°C
to +125°C and are packaged in 16-pin CERDIP and 20-terminal
LCC packages.

Ordering Information ...
CLC533AJP -40°C to +85°C 16-pin plastic DIP

CLC533AJE -40°C to +85°C 16-pin plastic SOIC
CLC533ALC -40°C to +85°C dice
CLC533A8B -55°C to +125°C 16-pin CERDIP,

MIL-STD-883
CLC533AMC -40°C to +85°C dice, MIL-STD-833
CLC533A8L-2A -55°C to +125°C 20-ter minal LCC,

MIL-STD-883
Contact factory for other packages and DESC SMD number.

CLC533
High-Speed 4:1 Analog Multiplexer

N

June 1999

CLC533

High-Speed 4:1 Analog Multiplexer

A1A0OUT

00 A
01 B
10 C
11 D

ECL Mode - D

REF

= open

TTL Mode - D

REF

= +5V

INA3
GND2
NC1
OUTPUT20
COMP

1

19

GND 9

IN

D

10

NC 11

V

ee

12

A

1

13

14

A

0

15

COMP

2

16NC17

D

REF

18

V

cc

8

GND

7

IN

B

6NC5

GND

4

IN

c

© 1999 National Semiconductor Corporation http://www.national.com

Printed in the U.S.A.

http://www.national.com 2

PARAMETERS CONDITIONS TYP MIN/MAX RATINGS

2

UNITS SYMBOL

Ambient T emper ature CLC533AJP/AJE/AIB +25°C -40°C +25°C +85°C

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth V

OUT

< 0.1V

pp

180 130 130 110 MHz SSBW

-3dB bandwidth V

OUT

= 2V

pp

45 35 35 30 MHz LSBW

gain flatness V

OUT

< 0.1V

pp

peaking 0.1MHz to 200MHz 0.2 0.5 0.5 0.5 dB GFP

rolloff 0.1MHz to 100MHz 1.0 2.0 2.0 3.0 dB GFR
linear phase deviation dc to 100MHz 2.0 deg LPD
crosstalk rejection - 1 channel 2V

pp

, 10MHz 80 74 74 74 dB CT10

2V

pp

, 20MHz 74 68 68 68 dB CT20

2V

pp

, 30MHz 68 62 62 62 dB CT30

crosstalk rejection - 3 channels 2V

pp

, 10MHz 80 74 74 74 dB 3CT10

2V

pp

, 20MHz 74 68 68 68 dB 3CT20

2V

pp

, 30MHz 68 62 62 62 dB 3CT30

TIME DOMAIN PERFORMANCE

rise and fall time 0.5V step 2.7 3.3 3.3 3.8 ns TRS

2V step 10 12.5 12.5 14.5 ns TRL

settling time

2

2V step ±0.01% 17 24 24 27 ns TSP

±0.1% 13 18 18 21 ns TSS
overshoot 2.0V step 2 5 5 6 % OS
slew rate 160 130 130 110 V/µsSR

SWITCH PERFORMANCE

channel to channel switching time 50% SELECT to 10%V

OUT

6 8 8 9 ns SWT10

(2V step at output) 50% SELECT to 90%V

OUT

16 21 21 24 ns SWT90

switching transient 30 mV ST

DISTORTION AND NOISE PERFORMANCE

2nd harmonic distortion 2V

pp

, 5MHz 80 67 67 67 dBc HD2

3rd harmonic distortion 2V

pp

, 5MHz 86 67 67 67 dBc HD3

equivalent input noise

spot noise voltage > 1MHz 4.2 nV/√Hz SNF
integrated noise 1MHz to 100MHz 42 54 51 mVrms INV
spot noise current 5 pA/√Hz SNF

STATIC AND DC PERFORMANCE

* analog output offset 1 12 3.5 4.5 mV VOS

temperature coefficient 15 90 20 µV/°C D VIO

* analog input bias current 50 280 120 120 µA IBN

temperature coefficient 0.3 2.0 0.8 µA/°C DIBN
analog input resistance 200 90 120 120 kΩ RIN
analog input capacitance 2 3.0 2.5 2.5 pF CIN

* gain accuracy ±2V 0.994 0.988 0.988 0.988 V/V GA

integral endpoint linearity ±1V (full scale) 0.02 0.05 0.03 0.03 %FS ILIN
output voltage no load ±3.4 2.4 2.8 2.8 V VO
output current 45 20 50 50 mA IO
output resistance DC 1.5 4.0 2.5 2.5 Ω RO

DIGITAL INPUT PERFORMANCE

ECL mode (D

REF

floating)
input voltage logic HIGH -1.1 -1.1 -1.1 V VIH1
input voltage logic LOW -1.5 -1.5 -1.5 V VIL1
input current logic HIGH 200 220 80 80 µA IIH1
input current logic LOW 200 220 80 80 µA IIL1

TTL mode (D

REF

= +5V)
input voltage logic HIGH 2.0 2.0 2.0 V VIH2
input voltage logic LOW 0.8 0.8 0.8 V VIL2
input current logic HIGH 200 220 80 80 µA IIH2
input current logic LOW 200 220 80 80 µA IIL2

POWER REQUIREMENTS

* supply current (+V

CC

= +5.0V) no load 28 38 36 36 mA ICC

* supply current (-V

ee

= -5.2V) no load 28.5 39 37 37 mA IEE

nominal power dissipation no load 288 mW PD

* power supply rejection ratio -53 -60 -60 dB PSRR

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.

CLC533 Electrical Characteristics

(+Vcc= +5.0V; -Vee= -5.2V; Rin= 50Ω;RL= 500Ω;C

COMP

= 8pf; ECL Mode, pin 13 = NC)

3 http://www.national.com

Small Signal Gain/Phase vs. Load*

*with recommended C

COMP

Digitalized Pulse Response

±

±

CLC533 Typical Performance Characteristics

(TA = 25°C, +Vcc = +5V, -Vee = -5.2V, RL = 500Ω unless specified)