NSC 5962-8769801FA, 5962-8769801EA, 5962-87698012A Datasheet
54AC153•54ACT153
Dual 4-Input Multiplexer
General Description
The ’AC/’ACT153 is a high-speed dual 4-input multiplexer
with common select inputs and individual enable inputs for
each section. It can select two lines of data from four
sources. The two buffered outputs present data in the true
(non-inverted) form. In addition to multiplexer operation, the
’AC/’ACT153 can act as a function generator and generate
any two functions of three variables.
Features
n ICCreduced by 50
%
n Outputs source/sink 24 mA
n ’ACT153 has TTL-compatible inputs
n Standard Microcircuit Drawings (SMD)
—’AC153: 5962-87625
—’ACT153: 5962-87698
Logic Symbols
Pin
Names
Description
I
0a–I3a
Side A Data Inputs
I
0b–I3b
Side B Data Inputs
S
0,S1
Common Select
Inputs
E
a
Side A Enable Input
E
b
Side B Enable Input
Z
a
Side A Output
Z
b
Side B Output
FACT®is a registered trademarkof Fairchild Semiconductor Corporation.
DS100271-1
IEEE/IEC
DS100271-2
September 1998
54AC153
•
54ACT153 Dual 4-Input Multiplexer
© 1998 National Semiconductor Corporation DS100271 www.national.com
Connection Diagrams
Functional Description
The ’AC/’ACT153 is a dual 4-input multiplexer. It can select
two bits of data from up to four sources under the control of
the common Select inputs (S
0,S1
). The two 4-input multi-
plexer circuits have individual active-LOW Enables (E
a,Eb
)
which can be used to strobe the outputs indepedently.When
the Enables (E
a,Eb
) are HIGH, the corresponding outputs
Za,Zb) are forced LOW. The ’AC/’ACT153 is the logic implementation of a 2-pole, 4-position switch, where the position
of the switch is determined by the logic levels supplied to the
Select inputs. The logic equations for the outputs are shown
below.
Z
a
=
E
a
•
(I
0a
•
S
1
•
S0+I
1a
•
S
1
•
S0+
I
2a
•
S
1
•
S0+I
3a
•
S
1
•
S0)
Z
b
=
E
b
•
(I
0b
•
S
1
•
S0+I
1b
•
S
1
•
S0+
I
2b
•
S
1
•
S0+I
3b
•
S
1
•
S0)
Truth Table
Select Inputs (a or b) Output
Inputs
S
0S1
E I0I1I2I
3
Z
XXHXXXX L
L LLL XX X L
LLLHXXX H
HLLXLXX L
HLLXHXX H
LHLXXLX L
LHLXXHX H
HHLXXXL L
HHLXXXH H
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Pin Assignment
for DIP and Flatpak
DS100271-3
Pin Assignment
for LCC
DS100271-4
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Logic Diagram
DS100271-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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