Nokia 3110 System Module Schematics
Programmes After Market Services
NHE–8/9 Series Transceivers
Chapter 3
System Module
issue 3 12/98
NHE–8/9
System Module
Technical Documentation
CONTENTS
Overview 3 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation 3 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Description Summary 3 – 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Distribution 3 – 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baseband Module 3 – 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Specifications 3 – 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description 3 – 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Interface 3 – 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard and Display Light 3 – 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Control 3 – 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Internal Audio 3 – 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Audio 3 – 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RFI2, N450 Operation 3 – 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIM Interface 3 – 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RF Module 3 – 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Summary 3 – 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Signals and Connections 3 – 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Technical Specifications 3 – 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description 3 – 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Characteristics 3 – 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Characteristics 3 – 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesizers 3 – 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connections 3 – 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Antenna 3 – 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Antenna selection switch 3 – 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parts List 3 – 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Module – GJ3_09 3 – 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Module – GJ3_10 3 – 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Module – GJ3_12 3 – 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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PAMS
NHE–8/9
Technical Documentation
List of Figures
Figure 1. Block Diagram – BB/RF Modules 3– 6. . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2. Power Distribution Diagram. 3–23. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3. Charge Switch Circuit Diagram 3–24. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4. Power up sequence 3–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5. Flash Loading acknowledgement procedure 3–35. . . . . . . . . . . . . . .
Figure 6. XMIC Bridge Implementation 3–42. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7. Power distribution diagram 3–52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8. RF Block Diagram 3–54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note: In printed manuals all A3 drawings are located at the back of the binder.
Schematics/Layouts (GJ3_09 )
Figure 9 Component Layout Diagram –Top 3–A1. . . . . . . . . . . . . . . . . . . . . . .
Figure 10 Component Layout Diagram – Bottom 3–A2. . . . . . . . . . . . . . . . . . .
Figure 11 SYSTEM Block 3–A3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12 RX/TX Block 3–A4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13 RX 3–A5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14 TX 3–A6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15 Baseband 3–A7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16 Audio 3–A8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17 CPU 3–A9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18 DSP Memory Blocks 3–A10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19 Keyboard /Display interface 3–A11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 20 MCU memory Block 3–A12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21 Power Supply & Charging 3–A13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22 BB/RF Analog Interface 3–A14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23 System Connector 3–A15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics/Layouts (GJ3_10 )
Figure 24 Component Layout Top 3–A16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25 Component Layout Bottom 3–A17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 26 System Block 3–A18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 27 RX/TX Block 3–A19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 28 RX 3–A20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 29 TX 3–A21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 30 Baseband 3–A22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 31 Audio 3–A23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 32 CPU 3–A24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 33 DSP 3–A25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 34 Keyboard / Display Interface 3–A26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35 MCU 3–A27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 36 Power Supply / Charging 3–A28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 37 BB / RF Analog Interface 3–A29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 38 System Connector 3–A30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Module
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NHE–8/9
System Module
Schematics/Layouts (GJ3_12 )
Component Layout Diagram –Top 3–A31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component Layout Diagram – Bottom 3–A32. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM Block 3–A33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX/TX Block 3–A34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX 3–A35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX 3–A36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baseband 3–A37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio 3–A38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU 3–A39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Memory Blocks 3–A40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard /Display interface 3–A41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU memory Block 3–A42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Documentation
PAMS
Power Supply & Charging 3–A43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BB/RF Analog Interface 3–A44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Connector 3–A45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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PAMS
NHE–8/9
Technical Documentation
Overview
The nhe–8/9 is a radio transceiver unit for the pan–European GSM network.
It is a GSM phase 1 power class 4 transceiver providing 1 1 power levels with
a maximum output power of 2 W.
The transceiver consists of a Radio module (GJ3), UIF–module (GU9) and
assembly parts.
The plug–in (small size) SIM (Subscriber Identity Module) card is located
inside the phone.
Modes of Operation
There are four different operation modes
– power off mode
– idle mode
System Module
– active mode
– local mode
In the
In the
as long as possible.
In the
parts might be in the idle state part of the time.
The
power off mode
idle mode
circuits are in reset, powered down and clocks are stopped
active mode
local mode
is used for alignment and testing.
only the circuits needed for power up are supplied.
all the circuits are supplied with power although some
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NHE–8/9
System Module
Circuit Description Summary
The transceiver electronics consists of the Radio Module (RF + BB blocks),
the UI–module and the display module. The UI–module is connected to the
Radio Module with a connector and display module is connected to
UI–module by solder joint. BB blocks and RF blocks are interconnected with
PCB wiring. The Transceiver is connected to accessories via a bottom
system connector with charging and accessory control.
The BB blocks provide the MCU and DSP environments, Logic control IC,
memories, audio processing and RF control hardware (RFI2). On board
power supply circuitry delivers operating voltages for BB blocks. RF blocks
have regulators of their own.
The general purpose microcontroller, Hitachi H8/3001, communicates with
the DSP, memories and Logic control IC with an 8–bit data bus.
The RF block is designed for a handportable phone which operates in the
GSM system. The purpose of the RF block is to receive and demodulate the
radio frequency signal from the base station and to transmit a modulated RF
signal to the base station.
PAMS
Technical Documentation
DUPLEX
FILTER
RF BLOCK
RX
RX
SYNTE
SYNTE
TX
TX
Keyboard
SYSTEM
ASIC
Clk
13 M
IF 13 M
Clk 13 M
AFC
TXI,TXQ
TXC
RF CONTROL
SIM
PSCLD
RESET
RFI2
Figure 1. Block Diagram – BB/RF Modules
Display
RESET
Clk
13 M
Clk
13 M
RESET
MCU
DSP
Clk 512 k,
RESET
M2BUS
FBUS
AUDIO
Clk 8 k
SYSTEM BLOCK
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NHE–8/9
Technical Documentation
Power Distribution
The power supply is based on the ASIC circuit PSCLD. The chip consists of
regulators and control circuits providing functions like power up, reset and
watchdog functions. External buffering is required to provide more current.
The MCU and the PSCLD circuits control charging together, detection being
carried out by the PSCLD and higher level intelligent control by the MCU.
Charger voltages as well as temperature and size of the battery are
measured by internal ADC of MCU or RFI (depending on the state of the
phone). MCU measures battery voltage via DSP by means of RFI2 internal
ADC.
Baseband Module
The GJ3 module is used in GSM products. The baseband is implemented
using DCT2 core technology. The baseband is built around one DSP,
System ASIC and the MCU. The DSP performs all speech and GSM
related signal processing tasks. The baseband power supply is 3V except
for the A/D and D/A converters that are the interface to the RF section.
The A/D converters used for battery and accessory detection are
integrated into the same device as the signal processing converters.
System Module
The audio codec is a separate device which is connected to both the DSP
and the MCU. The audio codec support the internal and external
microphone/earpiece functions. External audio is connected in a dual
ended fashion to improve audio quality together with accessories.
The baseband implementation support a 32.768 kHz sleep clock function
for power saving. The 32.768 kHz clock is used for timing purposes during
inactive periods between paging blocks. This arrangement allows the
reference clock, derived from RF to be switched off.
The baseband clock reference is derived from the RF section and the
reference frequency is 13 MHz. A low level clipped sinusoidal wave form
is fed to the ASIC which acts as the clock distribution circuit. The DSP is
running at 39 MHz using an internal PLL. The clock frequency supplied to
the DSP is 13 MHz. The MCU bus frequency is the same as the input
frequency. The system ASIC provides both 13 MHz and 6.5 MHz as
alternative frequencies. The MCU clock frequency is programmable by the
MCU. The nhe–8/9 baseband uses 13 MHz as the MCU operating
frequency. The RF A/D, D/A converters are operated using the 13 MHz
clock supplied from the system ASIC
The power supply and charging section supplies Lithium Ion and NiMH
type of battery technology. The battery charging unit is designed to accept
constant current type of chargers, that are approved by NMP.
The power supply IC, contains four different regulators. The output voltage
from two of the regulators are 3.15V nominal. A third regulator controls an
external boost transistor for a 3.15V ’high’ current supply. The last
regulator supplies the SIM card voltage, which is 4.9V.
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NHE–8/9
g
System Module
Technical Documentation
Technical Specifications
The Baseband in nhe–8/9 Operates in the following Modes
Active, as during a call or when baseband circuitry is operating
Sleep, in this mode the clock to the baseband is stopped and
timing is kept by the 32.768 kHz oscillator. All Baseband
circuits are powered
Acting dead, in this mode the battery is charged but only
necessary functions for charging are running
Power off, in this mode all baseband circuits are powered off.
The regulator IC N300 is powered
External Signals and Connections
Table 1. List of Connectors
Connector Name Code Notes Specifications / Ratings
PAMS
System Connector 5469007 X100
SIM Connector 5409033 X102
Table 2. System Connector X100
Pin Name Parameter Min Typ Max Unit Remark
1, 7,
18,
20
2 V_OUT Accessory Out-
3 XMIC
GND Charger & Sys-
tem Ground
put Supply
External Micro-
ID
phone Input
Endless No Accessory
IR Link 2.22 2.39 2.56 V Infra Red Link connected
Headset 1.7 1.9 2.05 V Headset Adapter Con-
Compact HF 1.15 1.3 1.4 V Compact HF Connected
0
800
3.40 9.3 V Output Current 50 mA.
8 50 mV The maximum value corre-
0
1500VmA
Measuring Reference
Max Value for Charger
Peaks
sponds to 0 dBm network
level with input amplifier
gain set to 20 dB. Typical
value is maximum value
–16 dB.
nected
4 EXT_RF External RF con-
trol input
5 TX FBUS transmit
6 MBUS Serial
Control
Bus
Page 3 – 8
”0”
”1”
0 0.5 V External RF in use
2.4 3.2 V Internal antenna in use
0 0.5
2.4 3.2
0
2.4
0.5
3.2
Accessory FBUS transmit
signal, Serial data bus. The
signal has a pull–up inside
the ASIC.
Baud rate 9.6 – 115.2kBit /
s.
V
General Purpose Control
V
and Test Control Bus
issue 3 12/98
PAMS
NHE–8/9
Technical Documentation
Table 2. System Connector X100 (continued)
8 SGND Signal ground 0 0 V Measuring Reference for
Audio signals. 47 ohm to
9 XEAR
10 HOOK Acces-
11 RX FBUS receive
External Speaker 0 32 500 mV Connected to Audio Codec
Inverted Output. Typical
level corresponds to –16
dBmO network level with
volume control in nominal
position 8db below maxi-
mum. Maximum 0 dBm0
max. volume codec gain
MUTE ON
OFF
OFF
sory
Hook
Signal
ON 2.4
0
1 1.5
0 0.5 V
2.4 3.2 V
0.5
1.7
0.5
3.2
V
V
V
V
Baseband has 4.7 kohm
Accessory FBUS receive
signal, Serial data bus.
Baud rate 9.6 – 115.2kBit /
Phone has a pull–up resis-
System Module
RemarkUnitMaxTypMinParameterNamePin
Audio Ground
–6dB.
HF Speaker Mute
HF Speaker Active
HOOK OFF
HOOK ON
Pull–up
s.
tor.
13 BGND GND 0 0 0 V Battery GND
14 BTEMP Battery Temper-
ature
15 BSI Battery Size 0 0 3.3 V Used for SIM Card Detec-
16 VBatt Battery Voltage 5.3 6 9.3 V Main Power Supply
12,
17,
19
V_IN Charger supply
Voltage
0 0 3.3 V Also used for Vibration
Alert
tion
9.8
12
10.3
14
10.8
16
VVFast Charger ACH–6 (780
mA)
Standard Charger ACH–8
(265mA)
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NHE–8/9
System Module
PAMS
Technical Documentation
Table 3. SIM Connector X102
Pin Name Parameter Logic
Level
1 GND, C5 GND 0 0 V Digital GND
2,6 VSIM, C1,C6SIM Supply
Voltage
3 SDATA,
C7
4 SRES, C2 SIM Reset ”1”
5 CLK, C3 SIM Clock ”1”
SIM DA TA
VI
VO
”1”
”0”
”1”
”0”
”0”
”0”
Min Typ Max Unit Remark
4.8 4.9 5.0 V Tr, max.
2V/us max
200 us. T
max. 200 us.
0.7xVSIM
0
0.7xVSIM
0
VSIM–0.7
0
0.7xVSIM
0
VSIM
0.8
VSIM
0.4
VSIM
0.6
VSIM
0.5
V
V
V Clock fre-
quency mini-
mum 1 MHz if
clock stopping
not allowed
Note1.
f
Note 1. VSIM supply voltage may be selected to 3 V to meet 3V SIM card specifications. ( Voltage
range 3.1 to 3.3 V). The values in NO TAG will be different, values only valid for ”5 volt SIM card”.
Page 3 – 10
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PAMS
S
PSCLD
NHE–8/9
Technical Documentation
Table 4. User Interface Connector X101
4
5 VL Display Sup-
6 SYSRE-
7 GND Ground 0 V
8 KEYLIGHT Keboard
9 LCDLIGHT Display
10 BUZZER PWM signal-
11 GND Ground 0 V
GND Ground 0 V
3.0 3.2 V
ply
Reset
ETX
Light
Light
Buzzer con-
trol
”1” 2.4 3.2 V
”0” 0 0.6 V
”1”
”0”
”1”
”0”
2.8
0
2.8
0
0 3.2 V
3.2
0.2
3.3
0.2
System Module
Edge sensi-
tive
V Max 1 mA
can be
drawn from
N300
(PSCLD)
V Max 1 mA
can be
drawn from
N300
(PSCLD)
12 GENSCLK Serial clock
13 GENSD Serial data
14 LCDENX LCD enable
15 VBatt Battery Sup-
ply
18 XPWRON Power ON/
OFF
”1” 2.4 3.2 V
”0” 0 0.6 V
”1” 2.4 3.2 V
”0” 0 0.6 V
”1” 2.4 3.2 V
”0” 0 0.6 V
5.3 9.3 V
”1” 5.3 9.3 V
”0” 0 0.4 V
1.083 MHz
Pulled up to
Vbatt inside
.
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NHE–8/9
System Module
Table 4. User Interface Connector X101 (continued)
19 EARN Earphone 0 14 220 mV Connected
Technical Documentation
to Audio Co-
dec Inverted
Output. Typical level cor-
responds to
–16 dBmO
network level
with volume
control giv-
ing nominal
RLR
(=+2dB) 8
db below
max. Max
level is
0dBmO with
max volume
(codec gain
–11 db)
PAMS
20 EARP Earphone 0 14 220 mV Connected
to Audio Co-
dec non Inverted Out-
put. Typical
level corre-
sponds to
–16 dBmO
network level
with volume
control giv-
ing nominal
RLR
(=+2dB) 8
db below
max. Max
level is
0dBmO with
max volume
(codec gain
–11 db)
21 ROW(0) ROW(0) In-
put
22 ROW(1) ROW(1) In-
put
”1”
”0”
”1”
”0”
2.4
0
2.4
0
3.2
0.6
3.2
0.6
V
V
23 ROW(2) ROW(2) In-
24 ROW(3) ROW(3) In-
25 ROW(4) ROW(4) In-
Page 3 – 12
put
put
put
”1”
”0”
”1”
”0”
”1”
”0”
2.4
0
2.4
0
2.4
0
3.2
0.6
3.2
0.6
3.2
0.6
V
V
V
issue 3 12/98
PAMS
NHE–8/9
Technical Documentation
Table 4. User Interface Connector X101 (continued)
26 ROW(5) ROW(5) In-
put
27 COL(0) COL(0) Out-
put
28 COL(1) COL(1) Out-
put
29 COL(2) COL(2) Out-
put
30 COL(3) COL(3) Out-
put
31 GND Ground 0 V
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
2.4
0
2.6
0
2.6
0
2.6
0
2.6
0
3.2
0.6
3.2
0.4
3.2
0.4
3.2
0.4
3.2
0.4
System Module
V Also used for
data control
for LCD
V
V
V
V
Table 5. DAI interface connecting test pads
Pin Name Parameter Logic
Level
1 CODECB(0) Audio codec
clock
2 CODECB(4) DSP Serial
Data Receive
3 CODECB(5) DSP Serial
Data Trans-
mit
4 CODECB(1) Audio codec
sync
5 VL Digital Supply 3.0 3.3 V test pin J320
6 GND GND 0 0.2 V test pin J321
”1”
”0”
”1”
”0”
”1”
”0”
”1”
”0”
Min Typ Max Unit Remark
2.4
0
2.4
0
2.4
0
2.4
0
3.2
0.6
3.2
0.6
3.2
0.6
3.2
0.6
V Audio Codec clock
for DAI measure-
ments; test pin
J316
V Serial PCM data
receive for DAI
measurements;
test pin J317
V Serial PCM data
transmit for DAI
measurements;
test pin J318
V Audio Codec frame
synchronisation for
DAi measure-
ments; test pin
J319
issue 3 12/98
Page 3 – 13
NHE–8/9
System Module
Technical Documentation
Internal Signals and Connections
Table 6. SYS_CONN Block Connections
Name of Signal or Bus Type Notes References
XEAR/MUTE IN External earphone input from AU-
DIO block to System connector
SGND OUT Used as reference for external audio
XMIC/ID OUT External Microphone output from
System connector to AUDIO block
EXT_RF OUT External RF control output from
System Connector to CCPU block
BTYPE OUT Battery type
BTEMP OUT Battery temperature
HOOK OUT Accessory Interrupt
CHARGER+ OUT Charger positive contact
GND Ground
PAMS
VBATT IN Battery Supply Input to Power Block
MBUS I/O Serial Data Bus to MCU
V_OUT OUT External Accessory supply voltage
TX OUT Accessory FBUS digital data output
RX IN Accessory FBUS digital data input
RF I/O External RF connector signal
Page 3 – 14
issue 3 12/98
PAMS
NHE–8/9
Technical Documentation
Table 7. Audio Block Connections
Name of Signal or Bus Type Notes References
SGND OUT Negative Output From N200 (Co-
dec) Pin 2 used as reference for ex-
ternal audio
CODECB(5:0) IN/OUT Serial Digital Bus for Speech trans-
mission to/from CCPU Block
SCONB(5:0) IN/OUT Serial Control Bus from CCPU Block
XMIC IN External Microphone Input from
System Connector
MICP IN Positive Microphone input from in-
ternal Microphone
MICN IN Negative Microphone input from in-
ternal Microphone
XEAR OUT Positive Output from N200 (CO-
DEC)
EARN OUT Negative Earpiece output signal
from N200 (Codec)
EARP OUT Positive Earpiece output signal from
N200 (Codec)
BUZZER OUT Buzzer Output to User Interface
Connector
ACCDET OUT LP Filtered Signal from XMIC input
for Accessory Detection. Connected
to CCPU and RFI Block
System Module
Table 8. Keyboard Block Connections
Name of Signal or Bus Type Notes References
KEYB(9:0) IN/OUT Keyboard input/output
PWRONX OUT Power on signal to Power Block
COL(3:0) OUT Column Output to Keyboard con-
nector X101
ROW(5:0) IN Row inputs from keyboard Connec-
tor X101
PWRX IN Power On Signal input from Key-
board Connector
Active Low
issue 3 12/98
Page 3 – 15
NHE–8/9
System Module
Table 9. Power Block Connections
Name of Signal or Bus Type Notes References
MBUS(2:0) I/O Serial Data Bus to MCU
CODECB(5:0) IN/OUT Serial Synchronous Data Bus for
DAI and Testing
MCUP4(7:0) I/O MCU Port 4 Bus
SCONB(5:0) I/O Serial Control Bus for Regulator IC
Control
SIMI(5:0) I/O SIM Card Signals from CCPU Block
BSI IN Battery Size Signal from System
Connector
BTEMP IN Battery Temperature Signal from
System Connector
CHARGER IN Charger Supply Input to Power
Block
GND Ground
Technical Documentation
PAMS
PWRONX IN Power On Signal from Keyboard
Block
SLEEPIX IN Sleep Control Signal from CCPU MCUMEMC(6)
VBAT IN Battery Supply Input to Power Block
VBATT OUT Battery Voltage to UI module
VBATT OUT Battery Power Supply to RF VBAT
CHARGE I/O Charge Detection Signal to CCPU
V_OUT OUT Accessory Power Supply
VLCD OUT Supply Voltage to LCD and Driver
VA OUT Supply voltage to Audio / analog cir-
cuitry.
VSL OUT Supply voltage and sleep mode sup-
ply
VL OUT Supply voltage for logic circuitry
SLEEPOX OUT Sleep signal to control RF VCXO Active Low, VXOENA
PURX OUT Power Up Reset to CCPU Block Active Low
M2BUS I/O Serial Control Bus to System Con-
nector
SIMCARD(3:0) I/O SIM Card SIgnals to Card Connec-
tor X102
LIGHTC(1:0) OUT Display & Keyboard Light Control
signals
ADCONV(5:0) OUT BSI, BTEMP, VBAT and VCAR V olt-
age to Baseband A/D Converter
Page 3 – 16
issue 3 12/98
PAMS
NHE–8/9
Technical Documentation
Table 10. CCPU Block Connections
Name of Signal or Bus Type Notes References
DSP_DATA(15:0) I/O 16 Bit DSP Data Bus
DATA(7:0) I/O 8 Bit MCU Data Bus
RFI_DATA(11:0) I/O 12 Bit RFI2 Data Bus
MBUS(2:0) I/O Serial Data Bus to MCU
CODECB(5:0) I/O DSP and Audio Codec Serial Bus
ACCES(1:0) I/O Accessory FBUS data
CPUAD(5:0) IN Input to MCU A/D Converter
PURX IN Power Up Reset
RFCLK IN System Clock from RF
RFDAX IN Data Available Signal From RFI2
CHARGE I/O Charger Presence Signal
HEADS IN Accessory Interrupt
RFCGND IN Reference Ground for RFCLK
System Module
RFICLK OUT 13 MHz Clock to RFI2
DSPINT(3:0) IN DSP Interrupt signals
DSPGENP(3:0) OUT DSP General Purpose Outputs
SCONB(5:0) OUT/IN Control Bus for Power Supply IC,
Display Driver and Audio Codec
DSP_ADDR(15:0) OUT DSP Address Bus
MEMC(6:0) OUT Chip Select and Memory control sig-
nals from MCU
MCUP4(7:0) I/O MCU Port 4 Signals
SIM(5:0) I/O SIM Card SIgnals to Power Block
DMEMC(3:0) OUT DSP Memory Control Signal Bus
RFO CONT OUT External RF output control
ADDR(23:0) OUT MCU Address Bus
RFCONT(7:0) OUT RF and Synthesizer Control Signal
Bus
RFIADC(5:0) OUT RFI2 Address and Control signal
Bus
KEYB(9:0) OUT/IN Keyboard ROW and Column Sig-
nals
issue 3 12/98
Page 3 – 17
NHE–8/9
System Module
Table 11. DSP_MEM Block Connections
Name of Signal or Bus Type Notes References
DSPMEMC(3:0) IN DSP Memory Control Signals from
CCPU Block
DSP_ADDR(15:0) IN 16–Bit DSP Address Bus from
CCPU Block
DSP_DATA(15:0) I/O 16–Bit DSP Data Bus from CCPU
Block
Table 12. MCU_MEM Block Connections
Name of Signal or Bus Type Notes References
MEMC(6:0) IN Memory Control Signals from CCPU
Block
ADR(23:0) IN 23–Bit MCU Address Bus from
CCPU Block
DA TA(7:0) I/O 8–Bit MCU Data Bus from CCPU
Block
Technical Documentation
PAMS
Table 13. RFI Block Connections
Name of Signal or Bus Type Notes References
RFIDATA(11:0) I/O 12 Bit Data Bus Between RFI2 and
CCPU Block
DSPINT(3:0) OUT Interrupt to CCPU Block
AUXAD(5:0) IN Baseband Measurement A/D Con-
verter Signals to RFI2 Block
RFIADC(5:0) OUT 4 Bit Address and 2 Bit Control Bus
from CCPU Block
VXOENA IN Sleep signal to control RFI2 analog
power supply
VBATT IN Battery Supply Voltage from Power
Block
RFICLK IN 13 MHz clock from CCPU Block
RFIDAX OUT Data Available Signal From RFI2
RXQ IN Input Signal From RF
RXI IN Input signal from RF
VREF 2.5V OUT Reference Voltage to RF
AFC OUT AFC Voltage to RF VCXO
Active Low, SLEEPOX
TXC OUT Power Ramp Control Signal to RF
TXIN OUT Negative In Phase Signal to RF
TXIP OUT Positive In Phase Signal to RF
TXQN OUT Negative Quadrature Signal to RF
TXQP OUT Positive Quadrature Signal to RF
RFIPORT(6:0) OUT Parallel Port From RFI Block
Page 3 – 18
issue 3 12/98
PAMS
C
reg-
tor
WRCreg-
tor
C
reg-
tor
C
C
C
NHE–8/9
Technical Documentation
Table 14. AC and DC Characteristics of the RF–baseband signals
Signal
name
VBATT bat-
VXOENA ASICRF
RXPWR ASI
FromTo Parameter Min Typical Max Unit Function
Voltage 5.3 6.0 9.3 V
RF
tery
Current 1500mA
Logic high ”1” 2.4 3.15 3.3 V Synth. regulator ON
regula-
Logic low ”0” 0 0.5 V Synth. regulator OFF,
tor
Current 0.5 mA
timing inaccuracy 10 us
Logic high ”1” 2.4 3.15 3.3 V RX supply voltage ON
RF
Logic low ”0” 0 0.5 V RX supply voltage OFF
ula-
Current 0.5 mA
System Module
Supply voltage for RF
vcxo voltage ON,
VCXO voltage OFF
SYNTHP
TXPWR ASI
SENA1 ASI
SDATA ASI
ASI
Logic high ”1” 2.4 3.15 3.3 V RF regulators ON
RF
Logic low ”0” 0 0.5 V RF regulators OFF
ula-
Current 1.0 mA
Logic high ”1” 2.4 3.15 3.3 V TX supply voltage ON
RF
Logic low ”0” 0 0.5 V TX supply voltage OFF
ula-
Current 0.5 mA
Logic high ”1 2.4 3.15 3.3 V
PLL
Logic low ”0” 0 0.8 V
Current 50 uA
Load capacitance 10 pF
Logic high ”1 2.4 3.15 3.3 V
PLL
Logic low ”0” 0 0.8 V
Load resistance 10 koh
Load capacitance 10 pF
Data rate frequency 3.25 MH
Dual PLL Enable
Synthesizer data
m
z
SCLK ASI
issue 3 12/98
Logic high ”1 2.4 3.15 3.3 V
PLL
Logic low ”0” 0 0.8 V
Load impedance 10 koh
Load capacitance 10 pF
Data rate frequency 3.25 MH
Synthesizer clock
m
z
Page 3 – 19
NHE–8/9
C
System Module
Table 14. AC and DC Characteristics of the RF–baseband signals (continued)
PAMS
Technical Documentation
Signal
name
TXP ASI
RFC VCTCXASI
PDATA0 RFI2LNA
m
RF
C
O
LNA
RFI
2
FunctionUnitMaxTypicalMinParameterToFro
Logic high ”1” 2.4 3.15 3.3 V
Logic low ”0” 0 0.8 V
Load Resistance 50 koh
Load Capacitance 10 pF
Timing inaccuracy 1 us
Frequency 13 MH
Signal amplitude 0.4 1.0 3.0 Vpp
Load Resistance 10 koh
Load Capacitance 5 pF
Logic high ”1” 2.4 3.15 3.3 V Nominal front end gain
Logic low ”0” 0 0.8 V Reduced front end gain
Current 0.1 mA Nominal front end gain
Transmitter power control enable
m
High stability clock sig–
z
nal for the locig circuits
m
PDATA1 RFI
2
PDATA2 RFI
2
PDATA3 RFI
2
PDATA4 RFI
2
PDATA5 RFI
2
Logic high ”1” 2.4 3.15 3.3 V
Logic low ”0” 0 0.5 V
Current 10 uA
Logic high ”1” 2.4 3.15 3.3 V
Logic low ”0” 0 0.5 V
Current 10 uA
Logic high ”1” 2.4 3.15 3.3 V
Logic low ”0” 0 0.5 V
Current 10 uA
Logic high ”1” 2.4 3.15 3.3 V
Logic low ”0” 0 0.5 V
Current 10 uA
Logic high ”1” 2.4 3.15 3.3 V
Logic low ”0” 0 0.5 V
Current 10 uA
Not used !
Not used !
Not used !
Not used !
Not used !
Page 3 – 20
issue 3 12/98
PAMS
C
O
O
O
VCTCXO
RXIN
FRFT2
signal to baseband
NHE–8/9
Technical Documentation
Table 14. AC and DC Characteristics of the RF–baseband signals (continued)
Signal
name
AFC RFI
RXIP /
m
2
CR
Voltage 0.26 3.94 V
VCT
X
Resolution 11 bits
Load impedance
(dynamic)
Noise Voltage 500
Settling time 1 ms
RFI
Output level 25 570 mVppDifferential RX 13 MHz
Source impedance 300 ohm
Load Resistance 10 koh
Load Capacitance 5 pF
10 koh
m
uVrm
s
m
System Module
FunctionUnitMaxTypicalMinParameterToFro
Automatic frequency
control signal for
VCTCX
10...10000 Hz
TXIP/
TXIN
RFI2CR
FRT
Phase Imbalance 2 deg
Amplitude Imbal-
ance
Differential voltage
swing
Differential Offset
voltage
Diff. Offset voltage
temp. dependence
DC level 2.0162.1 2.40 V
Offset voltage +–10mV
Source Impedance 50 ohm
Load Resistance 16 koh
Load Capacitance 10 pF
Resolution 8 bits
DNL +–0.9LSB
2.23 2.40 2.57 Vpp
1 dB
+–4.
mV
7
+–
2
m
Differential in–phase
TX baseband signal for
the RF modulator
TXQP/
TXQN
issue 3 12/98
RFI2CR
FRT
INL + –1 LSB
Group delay mis-
match
Same spec as for TXIP / TXIN Differential quadrature
100 ns
phase TX baseband
signal for the RF modulator
Page 3 – 21
NHE–8/9
tro
trol
System Module
Table 14. AC and DC Characteristics of the RF–baseband signals (continued)
PAMS
Technical Documentation
Signal
name
TXC RFI
VREF 2.5 RFI2RF Voltage level 2.493 V RF reference voltage
m
CR
2 FRT
Voltage Max 3.86 3.94 V
Voltage Min 0.26 0.34 V
Vout temperature
dependence
Source Impedance 50 ohm
Input resistance 10 koh
Input capacitance 10 pF
Settling Time 10 us
Noise level 500
Resolution 10 bits
DNL +–0.9LSB
INL + –4LSB
10 LSB
m
uVrm
s
Transmitter power control, CRFRT gain con-
0...200kHz
FunctionUnitMaxTypicalMinParameterToFro
l
RFO_CO
NT U
RFOUT RF OU
RFCGND ASICRF RFC signal ground
MC
Logic high ”1” 2.4 3.3 V
RF
Logic low ”0” 0 0.6 V
T
External RF control
2 W External RF signal
from/to bottom connector
Page 3 – 22
issue 3 12/98
PAMS
NHE–8/9
Technical Documentation
Functional Description
Power Supply
Vxoena
VBAT
V305
CHARGER +
L107
L108
CHGND
BGND
R344
C340
CHARGER
UNIT
V100
L101
GND
GND
AGND
L311
N451
4.50 V
L312
PSCLD
N300
VA
3.16 V
VSIM
5/3V
VRFI
N450
Z152
Z151
V306
GND
VSL
VSLRC
3.16 V
D151; pin 124
VSLC
3.16 V
D151
D401
D403
System Module
VBATT to RF
VBATT to UI module
VL
3.16 V
L306
Z150
Z153
Z451 VLRFI
VLCD
3.16 V3.16 V
VLMCU
VLDSP
D152
D404
D405
3.16 V
D150
D400
3.16 V
N450
Figure 2. Power Distribution Diagram.
The power supply for the baseband is the main battery. A charger input is
used to charge the battery. Two different chargers can be used for
charging the battery. A switch mode type fast charger that can deliver 780
mA and a standard charger that can deliver 265 mA. Both chargers are of
constant current type.
The baseband has one power supply IC, N300 delivering power to the
different parts in the baseband. There are two logic power supply and one
analog power supply. The analog power supply VA is used for analog
circuits such as audio codec, N200 and microphone bias circuitry. Due to
the current consumption and the baseband architecture the digital supply
is divided into two parts.
Both digital power supply rails from the N300, PSCLD are used to
distribute the power dissipation inside N300, PSCLD. The main logic
power supply VL has an external power transistor, V306 to handle the
power dissipation that will occur when the battery is fully charged or during
charging.
issue 3 12/98
Page 3 – 23
NHE–8/9
W
A
System Module
D151, ASIC and the MCU SRAM, D403 are connected to the same logic
supply voltage. All other digital circuits are connected to the main digital
supply.
Charging Control Switch Functional Description
The charging switch circuit diagram is shown below. The figure is for
reference only.
L303
L300
VBAT
PAMS
Technical Documentation
VB
V304 V305
C303
R343
V302
R308
V303
R327
R342
V311
R304
C304
R308
R309
CHARGER
GND
C300 C301 C302
R302
R303
R301
R326
V301
Figure 3. Charge Switch Circuit Diagram
The charging switch transistor V304 controls the charging current from the
charger input to the battery. During charging the transistor is forced in
saturation and the voltage drop over the transistor is 0.2–0.4V depending
upon the current delivered by the charger. Transistor V304 is controlled by
the PWM output from N300, via resistors R309, R308 and transistor V311.
The output from N300 is of open drain type. When transistor V304 is
conducting the output from N300 pin is low. In this case resistors R305
and R306 are connected in parallel with R304. This arrangement
increases the base current thru V304 to put it into saturation.
C308
C305
P
R306R305
Transistors V304, V302, V303 and V311 forms a simple voltage regulator
circuitry. The reference voltage for this circuitry is taken from zener diode
V301. The feedback for the regulator is taken from the collector of V304.
When the PWM output from N300 is active, low, the feedback voltage is
determined by resistors R308 and R309. This arrangement makes the
charger control switch circuitry to act as a programmable voltage regulator
with two output voltages depending upon the state of the PWM output
from N300. When the PWM is inactive, in high impedance state, the
feedback voltage is almost the same as on the collector of V304. Due to
the connection the voltage on V303 and V311 emitters are the same.
The feedback means that the system regulates the output voltage from
V304 in such a way that the base of V303 and V311 are at the same
voltage. The voltage on V302 is determined by the V301 zener voltage.
Page 3 – 24
issue 3 12/98
PAMS
NHE–8/9
Technical Documentation
The darlington connection of V303 and V302 service two purposes ; 1 the
load on the voltage reference V301 is decreased, 2 the output voltage on
V304 is decreased by the VBE voltage on V302 which is a wanted feature.
The voltage reduction allows a relative temperature stable zener diode to
be used and the output voltage from V304 is at a suitable level when the
PWM output from N300 is not active.
The circuitry is self starting which means that an empty battery is initially
charged by the regulator circuitry around the charging switch transistor.
The battery is charged to a voltage of maximum 4.8V. This charging
switch circuitry allows for both NiCd, NiMH and Lithium type of batteries to
be used. At the same time it will secure that the battery will not over
charge in case one cell is short circuited.
When the PWM output from N300 is active the feedback voltage is
changed due to the presence of R308 and R309. When the PWM is active
the charging switch regulator voltage is set to 9.3V maximum. This means
that even if the voltage on the charger input exceeds 11.5V the battery
voltage will not exceed 9.3 V. This protects N300 from over voltage even if
the battery was to be detached while charging.
System Module
The RC network C304, R308 and R309 also acts as a delay circuitry when
switching from one output voltage to an other. This happens when the
PWM output from N300 is pulsing. The reason for the delay is to reduce
the surge current that will occur when V304 is put into conducting state.
Before V304 is put in conducting state there is a significant voltage drop
over V304. The energy is stored in capacitors in the charger and these
capacitors must first be drained in order to put the charger in constant
current mode. This is done by discharging the capacitors into the battery.
The delay caused by C304 will reduce the surge current thru V304 to an
acceptable value.
R301 and R326 are used to regulate the zener current. During charging
with empty battery the zener voltage might drop due to low zener current
but this is no problem since the regulator is operating in constant current
mode while charging. The zener voltage is more important when the
charger voltage is high or in case that the PWM output from N300 is
inactive. In this case the charger idle voltage is present at the charger
supply pins.
R300 and R327 together with V304 forms a constant current source. The
surge current limitation behavior is frequency dependent since L107 is an
inductor. The purpose of this circuitry is to reduce the surge current thru
V304 when it is put in conducting state. Due to the low resistance value
required in L107 this arrangement is not very effective and the RC
network R308, R309 and C304 contributes more to the surge current
reduction.
V305 is a schottky diode that prevents the battery voltage from reverse
biasing V304 when the charger is not connected. The leakage current for
V305 is increasing with increasing temperature and the leakage current is
passed to ground via R308, V311 and R304.
issue 3 12/98
Page 3 – 25
NHE–8/9
System Module
This arrangement prevents V304 from being reversed biased as the
leakage current increases at high temperatures.
Components L107, C300, C301, C302 and L108 forms a filter for EMC
attenuation. The circuitry reduces the conductive EMC part from entering
the charger cable causing an increase in emission as the cable will act as
an antenna.
V100 is a 18V transient suppressor. V100 protects the charger input and
in particular V304 for over voltage. The cut off voltage is 18V with a
maximum surge voltage up to 25V. V100 also protects the input for wrong
polarity since the transient suppressor is bipolar.
Power Supply Regulator PSCLD, N300
The power supply regulators are integrated into the same circuit N300.
The power supply IC contains three different regulators. The main digital
power supply regulator is implemented using an external power transistor
V306. The other two regulators are completely integrated into N300.
PAMS
Technical Documentation
PSCLD, N300 External Components
N300 performs the required power on timing. The PSCLD, N300 internal
power on and reset timing is defined by the external capacitor C330. This
capacitor determines the internal reset delay, which is applied when the
PSCLD, N300 is initially powered by applying the battery. The baseband
power on delay is determined by C311. With a value of 10 nF the power
on delay after a power on request has been active is in the range of
50–150 ms. C310 determines the PSCLD, N300 internal oscillator
frequency and the minimum power off time when power is switched off.
The sleep control signal from the ASIC, D151 is connected via PSCLD,
N300. During normal operation the baseband sleep function is controlled
by the ASIC, D151 but since the ASIC is not powered up during the
startup phase the sleep signal is controlled by PSCLD, N300 as long as
the PURX signal is active, low. This arrangement ensures that the 13 MHz
clock provided from RF to the ASIC, D151 is started and stable before the
PURX signal is released and the baseband exits reset. When PURX is
inactive, high, sleep control signal is controlled by the ASIC D151.
To improve the performance of the analog voltage regulator VA an
external capacitor C329 has been added to improve the PSRR.
N300 requires capacitors on the input power supply as well as on the
output from each regulator to keep each regulator stable during different
load and temperature conditions. C305 and C308 are the input filtering
capacitors. Due to EMC precautions a filter using C305, L300 and C308
has been inserted into the supply rail. This filter reduces the high
frequency components present at the battery supply from exiting the
baseband into the battery pack. The regulator outputs also have filter
capacitors for power supply filtering and regulator stability. A set of
different capacitors are used to achieve a high bandwith in the
suppression filter.
Page 3 – 26
issue 3 12/98
PAMS
NHE–8/9
Technical Documentation
PSCLD, N300 Control Bus
The PSCLD, N300 is connected to the baseband common serial control
bus, SCONB(5:0). This bus is a serial control bus from the ASIC, D151 to
several devices on the baseband. This bus is used by the MCU to control
the operation of N300 and other devices connected to the bus. N300 has
two internal 8 bit registers and the PWM register used for charging control.
The registers contains information for controlling reset levels, charging
HW limits, watchdog timer length and watchdog acknowledge.
The control bus is a three wire bus with chip select for each device on the
bus and serial clock and data. From PSCLD, N300 point of view the bus is
used as write only to PSCLD. It is not possible to read data from PSCLD,
N300 by using this bus.
The MCU can program the HW reset levels when the baseband
exits/enters reset. The programmed values remains until PSCLD is
powered off, the battery is removed. At initial PSCLD, N300 power on the
default reset level is used. The default value is 5.1 V with the default
hysteresis of 400 mV. This means that reset is exit at 5.5 V when the
PSCLD, N300 is powered for the first time.
System Module
The watchdog timer length can be programmed by the MCU using the
serial control bus. The default watchdog time is 32 s with a 50 %
tolerance. The complete baseband is powered off if the watchdog is not
acknowledged within the specified time. The watchdog is running while
PSCLD, N300 is powering up the system but PURX is active. This
arrangement ensures that if for any reason the battery voltage doesn’t
increase above the reset level within the watchdog time the system is
powered off by the watchdog. This prevents a faulty battery from being
charged continuously even if the voltage never exceeds the reset limit. As
the time PURX is active is not exactly known, depends upon startup
condition, the watchdog is internally acknowledged in PSCLD when PURX
is released. This gives the MCU always the same time to respond to the
first watchdog acknowledge.
Baseband power off is initiated by the MCU and power off is performed by
writing the smallest value to the watchdog timer register. This will power
off the baseband within 0.5 ms after the watchdog write operation.
The control bus can also be used to setup the behavior of the N300
regulators during sleep mode, when sleep signal is active low. In order to
reduce power during sleep mode two of the three regulators can be
switched off. The third regulator, VSL which is kept active then supplies
the output of the other regulators. All regulator outputs from PSCLD, N300
are supplied but the current consumption is restricted. It is also possible to
keep the VL regulator active during sleep mode in case the power
consumption is in excess of what the VSL regulator can deliver in sleep
mode to the VL output.
issue 3 12/98
Page 3 – 27
NHE–8/9
System Module
The PSCLD, N300 also contains switches for connecting the charger
voltage and the battery voltage to the base band A/D converters. Since
the battery voltage is present and the charger voltage might be present in
power off the A/D converter signals must be connected using switches.
The switch state can be changed by the MCU via the serial control bus.
When PURX is active both switches are open to prevent battery/charger
voltage from being applied to the baseband measurement circuitry which
is powered off. Before any measurement can be performed both switches
must be set in not closed mode by MCU.
Charger Detection
A charger is detected if the voltage on N300, ’VCHAR’ is higher than
0.5V. The charger voltage is scaled outside PSCLD, N300 using resistors
R302 and R303. With the implemented resistor values the corresponding
voltage at the charger input is 2.8V. Due to the multifunction of the charger
detection signal from PSCLD, N300 to ASIC, D151 the charger detection
line is not forced ,active high until PURX is inactive. In case PURX is
inactive the charger detection signal is directly passed to D151. The active
high on ’CHRG_IND/ALARM’ pin generates and interrupt to MCU which
then starts the charger detection task in SW.
PAMS
Technical Documentation
The reason for not passing the charger detection signal to the ASIC, D151
when PURX is active is the RTC implementation in ASIC, D151., The
same signal is used to power up the system if the RTC alarm is activated
and the system is powered up. Due to this the PSCLD, N300
’CHRG_IND/ALARM’ pin, is in input mode as long as PURX is active, low.
Correspondingly at the ASIC end this pin is an output as long as PURX is
active. The RTC function needs SW support and is not implemented in
nhe–8/9. The baseband architecture provides for the functionality
required.
SIM Interface and Regulator in N300
The SIM card regulator and interface circuitry is integrated into the
PSCLD, N300. The benefit from this is that the interface circuits are
operating from the same supply voltage as the card, avoiding the voltage
drop caused by the external switch used in previous designs. The PSCLD,
N300 SIM interface also acts as voltage level shifting between the SIM
interface in the ASIC, D151 operating at 3V and the card operating at 5V.
Interface control in PSCLD is direct from ASIC, D151 SIM interface using
SIM(5:0) bus. The MCU can select the power supply voltage for the SIM
using the serial control bus. The default value is 3V which needs to be
changed to 5V before powering up the SIM interface in the ASIC, D151.
Regulator enable and disable is controlled by the ASIC via SIM(2).
Page 3 – 28
issue 3 12/98
PAMS
NHE–8/9
Technical Documentation
Power Up Sequence
The baseband can be powered up in three different ways.
When the power switch is pressed input pin ’PWRONX’ on
PSCLD, N300 is connected to ground and this switches the
regulators inside PSCLD on.
An other way to power up is to connect the charger,whichr
causes the baseband to power up and start charging the
battery.
The third way to power the system up is to attach the battery.
Power up using Power on Button
This is the most common way to power the system up. It is successful if
the battery voltage is higher than the power on reset level set by the MCU,
in the PSCLD, N300, default value 5.5 Vdc. The power up sequence is
started when the power on input pin ’PWRONX’ at PSCLD is activated,
low. The PSCLD then internally enters the reset state where the regulators
are switched on. At this state the PWM output ’CHRGSW’ on the PSCLD
is forced active to support additional power from any charger connected.
The sleep control output signal is forced high enabling the regulator to
supply the VCO and startup the clock.
System Module
After the power on reset delay of 50–150 ms PURX is released and the
system exits reset mode. The PWM output is still active until the MCU
writes the first value to the PWM register. The watchdog has to be
acknowledged within 16 s after that PURX is released, go high.
The power up sequence using power on/off button is shown below.
PwrSwitch
has been pressed
Supply voltage
VL
Master Reset
PurX
MCU Clock starts
issue 3 12/98
MCU Reset release
Figure 4. Power up sequence
Page 3 – 29
NHE–8/9
System Module
Power up with Empty Battery using Charger
When the charger is inserted into the DC jack or charger voltage is
supplied at the system connector contacts/pins, PSCLD ( N300) powers
up the baseband. The charging control switch is operating as a linear
regulator, the output voltage is 4.5V–5V. This allows the battery to be
charged immediately when the charger is connected, which guarantees
successful power up procedure with an empty battery.
With an empty battery the only power source is the charger. When the
battery has been initially charged and the voltage is higher than the
PSCLD, N300 switch on the sleep control signal which is connected to the
PSCLD for power saving function. Sleep mode, enters inactive state, high,
to enable the regulator that controls the power supply to the VCO to be
started. The ASIC, D151 which normally controls the sleep control line has
the sleep output inactive, low, as long as the system reset ’PURX’, from
PSCLD, is active, low. After a delay of about 5–10 ms the system reset
output from PSCLD enters high state. This delay is to ensure that the
clock is stable when the ASIC exits reset.
PAMS
Technical Documentation
The sleep control output from the PSCLD that has been controling
VXOENA until now, returns the control to the sleep signal from the ASIC
as the PURX signal goes inactive. When the PURX signal goes inactive,
high, the charge detection output at PSCLD, that is in input mode when
PURX is active, switches to output and goes high indicating that a charger
is present. When the system reset, PURX, goes high the sleep control line
is forced inactive, high, by the ASIC, D151 via PSCLD, N300.
Once the system has exited reset mode the battery is initially charged until
the MCU writes a new value to the PWM register in the PSCLD. If the
watchdog is not acknowledged the battery charging is switched off when
the PSCLD shuts off the power to the baseband. The PSCLD will not enter
the power on mode again until the charger has been extracted and
inserted again or the power on/off switch has been pressed.
The battery is charged as long as the power on line, PWRONX is active
low. This is done to allow the phone to be started manually from the power
button when the charger is conncted and there is no need to disconnect
the charger to get a power up if the battery is empty.
Power On Reset Operation
The system power up reset is generated by the regulator IC, N300. The
reset is connected to the ASIC, D151 that is put into reset mode whenever
the reset signal, PURX is low. The ASIC ( D151 ) then resets the DSP
(D152), the MCU (D150) and the digital parts in RFI2 (N450). When reset
is removed the clock supplied to the ASIC, D151 is enabled inside the
ASIC. At this point the 32.768 kHz oscillator signal is not enabled inside
the ASIC, since the oscillator is still in the startup phase.
Page 3 – 30
issue 3 12/98
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