NEC UPD78F9177YGB-8ES, UPD78F9177YGA-9EU, UPD78F9177GB-8ES Datasheet

DATA SHEET

µµµµ

Y

MOS INTEGRATED CIRCUIT

PD78F9177, 78F9177

8-BIT SINGLE-CHIP MICROCONTROLLER

The µPD78F9177 and µPD78F9177Y are µPD789177, 789177Y Subseries (small, general-purpose) in the 78K/0S

Series.

The µPD78F9177 replaces the internal ROM of the µPD789176 and µPD789177 with flash memory, while the

PD78F9177Y replaces the ROM of the µPD789176Y and µPD789177Y with flash memory.

µ

Because flash memory allows the program to be written and erased electrically with the device mounted on the
board, this product is ideal for the evolution stages of system development, small-scale production and rapid
development of new products.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.

µ

PD789167, 789177, 789167Y, 789177Y Subseries User’s Manual: U14186E

78K/0S Series User's Manual Instruction: U11047E

FEATURES

• Pin compatible with mask ROM version (except V

• Flash memory: 24 Kbytes

• High-speed RAM: 512 bytes

• Minimum instruction execution time can be changed from high-speed (0.4 µs: @5.0-MHz operation with main

system clock) to ultra-low-speed (122 µs: @ 32.768-kHz operation with subsystem clock)

• 10-bit resolution A/D converter: 8 channels

• I/O ports: 31

• Serial interface: 2 channels

3-wire serial I/O mode / UART mode: 1 channel

•

SMB (µPD78F9177Y only): 1 channel

•

• Timers: 6 channels

16-bit timer: 1 channel

•

8-bit timer/event counter: 2 channels

•

8-bit timer: 1 channel

•

Watch timer: 1 channel

•

Watchdog timer: 1 channel

•

• On-chip 16-bit multiplier

• Power supply voltage: VDD = 1.8 to 5.5 V

PP

pin)

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. U14022EJ1V0DS00 (1st edition)
Date Published August 2000 NS CP(K)
Printed in Japan

The mark shows major revised

©

2000

APPLICATIONS

Power windows, battery management unit, side air bags, etc

ORDERING INFORMATION

(1)

PD78F9177

µµµµ

Part Number Package

PD78F9177GB-8ES 44-pin plastic QFP (10 × 10)

µ

(2)

PD78F9177Y

µµµµ

Part Number Package

PD78F9177YGB-8ES 44-pin plastic LQFP (10 X 10)

µ

PD78F9177YGA-9EU 48-pin plastic TQFP (fine pitch) (7 X 7)

µ

µµµµ

PD78F9177, 78F9177Y

2

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

78K/0S SERIES DEVELOPMENT

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products under mass production

Products under development

Y subseries supports SMB.

Small, general-purpose

PD789046 PD789026 with subsystem clock added

44 pins
42/44 pins
28 pins

Small, general-purpose + A/D

44 pins
44 pins
30 pins
30 pins
30 pins
30 pins
30 pins
30 pins

µ

PD789026

µ

PD789014

µ

PD789177

µ

PD789167

µ

PD789156

µ

PD789146

µ

PD789134A

µ

PD789124A

µ

PD789114A

µ

PD789104A

µ

PD789177Y

µ

PD789167Y

µ

µ
µ

PD789014 with timer reinforced and ROM and RAM expanded

UART. Low-voltage (1.8-V) operation

PD789167 with improved A/D

µ
µ

PD789104A with improved timer
PD789146 with improved A/D

µ
µ

PD789104A with EEPROM added
PD789124A with improved A/D

µ

RC oscillation model of PD789104A

µ

PD789104A with improved A/D
PD789026 with A/D and multiplier added

µ

µ

78K/0S
series

For inverter control

44 pins

For driving LCD

80 pins
80 pins
64 pins
64 pins
64 pins
64 pins
64 pins
64 pins

For driving Dot LCD

144 pins
88 pins

For ASSP

52 pins
52 pins
44 pins
44 pins
20 pins
20 pins

PD789842

µ

PD789417A

µ

PD789407A

µ

PD789456

µ

PD789446

µ

PD789436

µ

PD789426

µ

PD789316

µ

PD789306

µ

PD789835

µ

PD789830

µ

PD789467

µ

PD789327

µ

PD789800

µ

PD789840

µ

PD789861

µ

PD789860

µ

Internal inverter control circuit and UART

PD789407A with improved A/D

µ
µ

PD789456 with improved I/O

µ

PD789446 with improved A/D
PD789426 with improved display output

µ
µ

PD789426 with improved A/D
PD789306 with A/D added

µ

RC oscillation model of PD789306
Basic subseries for driving LCD

Segment/common output: 96 pins
Segment: 40 pins, common: 16 pins

PD789327 with A/D added

µ

For remote controller. Internal LCD controller/driver
For PC keyboard. Internal USB function
For key pad. Internal POC
RC oscillation model of PD789860
For keyless entry. Internal POC and key return circuit

µ

µ

Data Sheet U14022EJ1V0DS00

3

The major differences between subseries are shown below.

Function

Subseries Name
Small,

general­purpose

PD789046 16 K 1 ch

µ

PD789026 4 K-16 K

µ

PD789014 2 K-4 K 2 ch

µ

ROM

Capacity

8-bit 16-bit Watch WDT

1 ch 1 ch 34 pins

Timer

1 ch

−

−

8-bit

10-bit

A/D

A/D

−−

µµµµ

PD78F9177, 78F9177Y

Serial Interface I/O

1 ch (UART:1 ch)

22 pins

DD

V

MIN

Value

1.8 V

Remark

−

Small,
general­purpose
+ A/D

For
inverter
control

For LCD
driving

PD789177

µ

PD789167

µ

PD789156

µ

PD789146

µ

PD789134A

µ

PD789124A

µ

PD789114A

µ

PD789104A

µ

PD789842 8 K-16 K 3 ch

µ

µ

PD789417A

µ

PD789407A
PD789456

µ

PD789446 6 ch

µ

PD789436

µ

PD789426

µ

PD789316

µ

PD789306

µ

16 K-24 K 3 ch 1 ch

8 K-16 K

2 K-8 K

12 K-24 K 3 ch

12 K-16 K

8 K to
16K

1 ch

1 ch

Note

1 ch 1 ch 1 ch

2 ch

−

1 ch 1 ch 8 ch

1 ch

−

8 ch

−

4 ch

4 ch

−

4 ch

7 ch

−

−

6 ch

−

8 ch

1 ch (UART: 1 ch)

−

4 ch

−

4 ch

−

4 ch

−

1 ch (UART: 1 ch) 30 pins 4.0 V

−

1 ch (UART: 1 ch)

7 ch

−

6 ch

−

6 ch

−

2 ch (UART: 1 ch) 23 pins

31 pins

20 pins

43 pins

30 pins

40 pins

1.8 V

1.8 V

−

Internal
EEPROM

RC oscillation
version

−

−

−

RC oscillation
version

−

LCD
driving

ASSP

Note

4

PD789835 24 K-60 K 6 ch

µ

PD789830 24 K 1 ch 1 ch

µ

PD789467 1 ch

µ

PD789327

µ

PD789800

µ

PD789840

µ

PD789861

µ

PD789860

µ

4 K-24 K 2 ch

8 K 1 ch

4 K

2 ch

−

−

−

1 ch 1 ch

1 ch 1 ch

1 ch

−

10-bit timer: 1 channel

Data Sheet U14022EJ1V0DS00

3 ch 28 pins 1.8 VFor Dot

−

−

−

4 ch 1 ch 29 pins 2.8 V

−

1 ch

−

30 pins 2.7 V

−

1 ch 21 pins
2 ch (USB: 1 ch) 31 pins 4.0 V

−

−

18 pins

14 pins 1.8 V

1.8 V Internal

−

LCD

−

RC oscillation
version,
Internal
EEPROM

Internal
EEPROM

OVERVIEW OF FUNCTIONS

µµµµ

PD78F9177, 78F9177Y

Item

Flash memory 24 KbytesInternal memory
High-speed RAM 512 bytes

Minimum instructi on execution time • 0.4/1.6 µs (@5.0-MHz operation with main system clock)

• 122
General-purpose registers 8 bits × 8 registers
Instruction set • 16-bit operations

• Bit manipulations (set, reset, test)
Multiplier 8 bits × 8 bits = 16 bits
I/O ports Total: 31

• CMOS input: 8

• CMOS I/O: 17

• N-ch open drain: 6
A/D converters 10-bit resolution × 8 channels
Serial interfaces 3-wire serial I/O/UART : 1 c hannel

Timers • 16-bit timer:1 channel

• 8-bit timer/event counter:2 channels

• 8-bit timer:1 channel

• Watch timer:1 channel

• Watchdog timer:1 channel
Timer output 4 output
Buzzer output 1
Vectored interrupt
sources

Non-maskable Internal: 1
Power supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = −40°C to +85°C
Package 44-pin plastic LQFP (10 × 10)

Internal: 10, External: 4
Internal: 12, External: 4

PD78F9177

µ

s (@ 32.768-kHz operation with s ubsystem clock)

µ

•

3-wire serial I/O / UART: 1 channel

• SMB: 1 channel

PD78F9177)Maskable

(µ

PD78F9177Y)

(µ

•

44-pin plastic LQFP (10 X10)

•

48-pin plastic TQFP (fine pitch) (7 x 7)

PD78F9177Y

µ

Data Sheet U14022EJ1V0DS00

5

µµµµ

PD78F9177, 78F9177Y

CONTENTS

1. PIN CONFIGURATION (TOP VIEW)................................................................................................. 7

2. BLOCK DIAGRAM............................................................................................................................. 10

3. PIN FUNCTIONS................................................................................................................................ 11

3.1 Port Pins.................................................................................................................................................. 11

3.2 Non-Port Pins.......................................................................................................................................... 12

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins...................................................... 13

4. CPU ARCHITECTURE....................................................................................................................... 15

5. FLASH MEMORY PROGRAMMING ................................................................................................ 16

5.1 Selecting Communication Mode .......................................................................................................... 16

5.2 Function of Flash Memory Programming ............................................................................................ 17

5.3 Flashpro III Connection Example ......................................................................................................... 17

5.4 Example of Settings for Flashpro III (PG-FP3) .................................................................................... 19

6. INSTRUCTION SET OVERVIEW ...................................................................................................... 20

6.1 Conventions ........................................................................................................................................... 20

6.2 Operations .............................................................................................................................................. 22

7. ELECTRICAL SPECIFICATIONS...................................................................................................... 27

8. CHARACTERISTICS CURVES ........................................................................................................ 45

9. PACKAGE DRAWING ...................................................................................................................... 46

10. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 48

APPENDIX A. DIFFERENCES BETWEEN

PD78F9177, 78F9177Y, AND MASK ROM VERSIONS...... 49

µµµµ

APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 50

APPENDIX C. RELATED DOCUMENTS............................................................................................... 52

6

Data Sheet U14022EJ1V0DS00

1. PIN CONFIGURATION (TOP VIEW)

µµµµ

PD78F9177, 78F9177Y

• 44-pin plastic LQFP (10

PD78F9177GB-8ES

µ

PD78F9177YGB-8ES

µ

P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
P66/ANI6
P67/ANI7

AV

SS

P10
P11

××××

10)

REFAVDD

AV

P53

P52

P51

P50

44 43 42 41 40 39 38 37 36 35 34

1
2
3
4
5
6
7
8

9
10
11

12 13 14 15 16 17 18 19 20 21 22

P05

SS1

V

P04

P03

P02

33
32
31
30
29
28
27
26
25
24
23

P01
P00
P26/TO80
P25/TI80/SS20

DD0

V
VSS0
X1
X2
RESET
XT1
XT2

Note

The SCL0 and SDA0 pins are available in

Cautions 1. Connect the V

2. Connect the AVDD pin to V

3. Connect the AVSS pin to V

P31/INTP1/TO81

P32/INTP2/TO90

P30/INTP0/TI81/CPT90

PP

pin directly to V

P33/INTP3/TO82/BZO90

DD0

SS0

DD1

V

Note

D20

X

Note

D20

X

P23/SCL0

P22/SI20/R

P21/SO20/T

P24/SDA0

P20/SCK20/ASCK20

PD78F9177Y product only.

µ

SS0

or V

SS1

.

.

.

PP

V

Data Sheet U14022EJ1V0DS00

7

µµµµ

PD78F9177, 78F9177Y

• 44-pin plastic QFP (fine pitch) (7

PD78F9177YGA-9EU

µ

P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
P66/ANI6
P67/ANI7

AV

SS

P10
P11

IC2

10
11
12

7)

××××

REFAVDD

AV

P53

P52

IC0

P51

4847 46 45444342 41 403938 37

1
2
3
4
5
6
7
8
9

1314 15 16171819 20 212223 24

DD1

V

P50

IC2

P05

SS1

V

P04

P03

P02

36
35
34
33
32
31
30
29
28
27
26
25

PP

V

P01
P00
P26/TO80
P25/Tl80/SS20
V

DD0

IC2
V

SS0

X1
X2
RESET
XT1
XT2

Cautions 1. Connect the V

2. Connect the IC0 (Internally Connected) pin directly to V

3. Leave the IC2 pin open.

4. Connect the AV

5. Connect the AV

P31/INTP1/TO81

P32/INTP2/TO90

P30/INTP0/Tl81/CPT90

PP

pin directly to the V

DD

pin to V

SS

pin to V

P33/INTP3/TO82/BZO90

DD0

.

SS0

.

P23/SCL0

P24/SDA0

P22/Sl20/RxD20

P21/SO20/TxD20

P20/SCK20/ASCK20

SS0

or V

SS1

pin in normal operation mode.

SS0

SS1

or V

.

8

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

ANI0 to ANI7: Analog Input RESET: Reset
ASCK20: Asynchronous Serial Input RxD20: Receive Data

DD

AV

: Analog Power Supply SCK20: Serial Clock (for SIO20)

REF

AV

: Analog Reference Voltage SCL0

SS

AV

: Analog Ground SDA0

Note2

: Serial Clock (for SMB0)

Note2

: Serial Data
BZO90: Buzzer Output SI20: Serial Input
CPT90: Capture Trigger Input SO20: Serial Output
IC0

Note1

,IC2

Note2

: Internally Connected SS20: Chip Select Input
INTP0 to INTP3: Interrupt from Peripherals TI80, TI81: Timer Input
P00 to P05: Port 0 TO80 to TO82, TO90: Timer Output
P10, P11: Port 1 TxD20: Transmit Data

DD0

P20 to P26: Port 2 V
P30 to P33: Port 3 V
P50 to P53: Port 5 V

DD1

, V

: Power Supply

PP

: Programming Power Supply

SS0

SS1

, V

: Ground

P60 to P67: Port 6 X1, X2: Crystal (Main System Clock)

XT1, XT2: Crystal (Subsystem Clock)

Notes 1.

2.

The IC0 pin is available in 48-pin plastic TQFP (fine pitch) only.
The IC2, SCL0, and SDA0 pins are available in

PD78F9177Y product only.

µ

Data Sheet U14022EJ1V0DS00

9

2. BLOCK DIAGRAM

µµµµ

PD78F9177, 78F9177Y

TI80/SS20/P25

TO80/P26

TI81/INTP0/CPT90/P30

TO81/INTP1/P31

TO82/INTP3/BZO90/P33

CPT90/INTP0/TI81/P30

TO90/INTP2/P32

BZO90/INTP3/TO82/P33

SCK20/ASCK20/P20

SO20/T

X

D20/P21

SI20/RXD20/P22

SS20/TI80/P25

SCL0/P23
SDA0/P24

ANI0/P60-

ANI7/P67

AV
AV

AV

REF

8-BIT TIMER/
EVENT COUNTER80

8-BIT TIMER/
EVENT COUNTER81

8-BIT TIMER82

16-BIT TIMER90

WATCH TIMER

WATCHDOG TIMER

DD
SS

SIO20

Note1

SMB

A/D

CONVERTER

78K/0S

CPU CORE

RAM

ROM

PORT0

PORT1

PORT2

PORT3

PORT5

PORT6

SYSTEM

CONTROL

INTERRUPT

CONTROL

P00-P05

P10, P11

P20-P26

P30-P33

P50-P53

P60-P67

RESET
X1
X2
XT1
XT2

INTP0/TI81/CPT90/P30
INTP1/TO81/P31
INTP2/TO90/P32
INTP3/TO82/BZO90/P33

Notes 1.

MULTIPLIER

SMB is available in

The IC0 pin is available in 48-pin plastic TQFP (fine pitch) only.

2.

The IC2 pin is available in

3.

PD78F9177Y product only.

µ

PD78F9177Y product only.

µ

V

DD0

V

SS0

V

PP

IC0
IC2

Note2
Note3

V

SS1

V

DD1

10

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

3. PIN FUNCTIONS

3.1 Port Pins

Pin Name I/O Function After Reset Alternate Function

P00 to P05 I/O Port 0

6-bit input/output port
Input/output mode can be specified in 1-bit units
When used as an input port, an on-chip pull -up resistor can be
specified by soft ware.

P10, P11 I/O Port 1

2-bit input/output port
Input/output mode can be specified in 1-bit units
When used as an input port, an on-chip pull -up resistor can be

specified by soft ware.
P20 SCK20/ASCK20
P21 SO20/TxD20
P22 SI20/RxD20
P23
P24
P25 TI80/SS20
P26
P30 INTP0/TI81/CPT90
P31 INTP1/TO81
P32 INTP2/TO90
P33

I/O Port 2

7-bit input/output port

Input/output mode can be specified in 1-bit units

For P20 to P22, P25, and P26, an on-c hi p pul l -up resistor can be

specified by soft ware.

Only P23 and P24 can be used as N-ch open-drai n

input/output port pins.

I/O Port 3

4-bit input/output port

Input/output mode can be specified in 1-bit units

On-chip pull-up resistor can be s pecified by software.

Input

Input

Input

Input

−

−

Note

SCL0

Note

SDA0

TO80

INTP3/TO82/BZO90

P50 to P53 I/O Port 5

4-bit N-ch open-drain input/output port

Input/output mode can be specified in 1-bit units
P60 to P67 Input Port 6

8-bit input-only port

PD78F9177Y only

µ

Note

Input

Input ANI0 to ANI7

−

Data Sheet U14022EJ1V0DS00

11

µµµµ

PD78F9177, 78F9177Y

3.2 Non-Port Pins

Pin Name I/O Function After Reset Alternate Function
INTP0 P30/TI81/CPT90
INTP1 P31/TO81

Input External interrupt input for which t he valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified

INTP2 P32/TO90
INTP3
SI20 Input Serial data input to serial interface Input P22/RxD20
SO20 Output Serial data output from serial interface Input P21/TxD20
SCK20 I/O Serial clock i nput /output for serial interface Input P20/ASCK20
SS20 Input Chip select input to serial int erface Input P25/TI80
ASCK20 Input Serial clock input for asynchronous serial i nterface Input P20/SCK20
RxD20 Input Serial data input for asynchronous serial interface Input P22/SI20
TxD20 Output S eri al data output for asynchronous s eri al i nt erface Input P21/SO20
SCL0
SDA0

Note1

Note1

I/O SMB0 clock input/output Input P23

I/O SMB0 data input/output Input P24
TI80 Input External count clock input to 8-bit ti mer/event counter (TM80) Input P25/SS20
TI81 Input External count clock input to 8-bit ti mer/event counter (TM81) Input P30/INTP0/CPT90
TO80 Output 8-bit timer/event count er (TM 80) output Input P26
TO81 Output 8-bit timer/event count er (TM 81) output Input P31/INTP1
TO82 Output 8-bit timer (TM82) output Input P33/INTP3/BZO90
TO90 Output 16-bit timer (TM90) output Input P32/INTP2
BZO90 Output 16-bit tim er (TM 90) Buzzer output Input P33/INTP3/TO82
CPT90 Input Capture edge input Input P30/INTP0/TI81
ANI0 to

Input A/D c onverter analog input Input P60 to P67

ANI7

REF

AV

SS

AV

DD

AV
X1 Input
X2
XT1 Input
XT2

DD0

V

DD1

V

SS0

V

SS1

V

A/D converter reference v ol t age

−

A/D converter ground potential

−

A/D converter analog power supply

−

Connecting crystal res onator for main system clock
oscillation

−

Connecting crystal res onator for subsystem clock oscillation

−

Positive power supply

−

Positive power supply (other than ports)

−

Ground potential

−

Ground potential (other than ports)

−

RESET Input System reset input Input
V

IC0

IC2

PP

Note2

Note1

Sets flash memory programming mode. Applies high vol t age

−

when a program is written or verifi ed. Connect directly to V

SS1

or V

in normal operation mode.

Internally connected. Connect this pin directly to the V

−

SS1

V

pin.

Internally connected. Leave this pin open.

−

SS0

SS0

or

Input

P33/TO82/BZO90

−−

−−

−−

−−

−−

−−

−−

−−

−−

−−

−−

−

−−

−−

−−

Notes 1.

12

PD78F9177Y only.

µ

2.

48-pin plastic TQFP (fine pitch) only.

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins is shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Type of I/O Circuit for Each Pin and Connection of Unused Pins

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pi ns

DD0

, V

DD0

DD0

SS0

DD0

, V

or V

, V

or V

or V

SS1

DD1

or V

DD1

DD1

or V

SS1

DD1

.

Input: Independently connects to V

P00 to P05
P10, P11
P20/SCK20/ASCK20

5-H

8-C

I/O

via a resistor.

Output: Leave open.

P21/SO20/TxD20
P22/SI20/RxD20
P23/SCL0
P24/SDA0

Note1

Note1

13-X Input: Independentl y connects to V

resistor.

Output: Leave open.
P25/TI80/SS20
P26/TO80

P30/INTP0/TI81/CPT90
P31/INTP1/TO81
P32/INTP2/TO90

8-C

Input: Independently connects to V

via a resistor.

Output: Leave open.

Input: Independently connects to V

resistor.

Output: Leave open.

P33/INTP3/TO82/BZO90
P50 to P53 13-T

Input: Independently connects to V

resistor.

Output: Leave open.
P60/ANI0 to P67/ANI7 9-C Input Connect directly to V
XT1 Input Connect to V
XT2

−

Leave open.

−

SS0

or V

RESET 2 Input

PP

V
IC0
IC2

Note2

Note1

−−

Connect directly to V

Leave open.

SS1

DD0

SS0

, V

.

or V

DD1

or V

−

SS1

SS0

.

SS0

via a

SS0

via a

via a

, V

, V

SS1

SS1

Notes 1.

The IC2, SCL0, and SDA0 pins are available in

2.

48-pin plastic TQFP (fine pitch) only.

Data Sheet U14022EJ1V0DS00

PD78F9177Y product only.

µ

13

Figure 3-1. Pin Input/Output Circuits

µµµµ

PD78F9177, 78F9177Y

Type 2

IN

Schmitt-triggered input with hysteresis characteristics

Type 5-H

Pull-up
enable

Data

V

DD0

P-ch

V

DD0

P-ch

IN/OUT

Output
disable

N-ch

V

SS0

Input
enable

Type 9-C

IN

P-ch

N-ch

AV

SS

Comparator

V

REF

+

−

(Threshold voltage)

Type 13-T

Output data

Output disable

V

N-ch

SS0

Input enable

Input buffer with intermediate withstand voltage

Input
enable

IN/OUT

Type 8-C

Pull-up
enable

Data

Output
disable

DD0

V

Type 13-X

P-ch

IN/OUT

V

DD0

P-ch

Output data

Output disable

N-ch

V

SS0

IN/OUT

N-ch

V

SS0

Input buffer with 5-V
withstand voltage

Comparator

14

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

4. CPU ARCHITECTURE

Products in the µPD78F9177 and µPD78F9177Y can access up to 64 Kbytes of memory space.
Figure 4-1 shows the memory map.

Figure 4-1. Memory Map

FFFFH

Special function registers

256 × 8 bits

FF00H
FEFFH

Internal high-speed RAM

512 × 8 bits

FD00H

Data memory space

FCFFH

6000H
5FFFH

Reserved

5FFFH

Program memory
space

0000H

Internal flash memory

24576 x 8 bits

0080H
007FH

0040H
003FH

0024H
0023H

0000H

Program area

CALLT table area

Program area

Vector table area

Data Sheet U14022EJ1V0DS00

15

µµµµ

PD78F9177, 78F9177Y

5. FLASH MEMORY PROGRAMMING

The on-chip program memory in the µPD78F9177 and µPD78F9177Y is flash memory.

The flash memory can be written with the µPD78F9177 and µPD78F9177Y mounted on the target system (on­board). Connect the dedicated flash programmer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine
and target system to write the flash memory.

Remark

FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd.

5.1 Selecting Communication Mode

The flash memory is written by using Flashpro III and by means of serial communication. Select a communication
mode from those listed in Table 5-1. To select a communication mode, the format shown in Figure 5-1 is used. Each
communication mode is selected by the number of V

PP

pulses shown in Table 5-1.

Table 5-1. Communication Mode

Communication Mode P i ns Used Number of V
3-wire serial I/O SCK20/ASCK20/P20

SO20/TxD20/P21
SI20/RxD20/P22

Note1

SMB

UART TxD20/SO20/P21

Pseudo 3-wire mode

Note2

SCL0/P23
SDA0/P24

RxD20/SI20/P22
P00 (Serial clock input)
P01 (Serial data output)
P02 (Serial data input)

0

4

8

12

PP

Pulses

Notes 1.

PD78F9177Y only

µ

Serial transfer is performed by controlling a port by software.

2.

Caution Be sure to select a communication mode based on the V

Figure 5-1. Communication Mode Selection Format

10 V

V

DD

V

PP

V

SS

V

RESET

16

DD

V

SS

Data Sheet U14022EJ1V0DS00

PP

pulse number shown in Table 5-1.

12 n

µµµµ

PD78F9177, 78F9177Y

5.2 Function of Flash Memory Programming

By transmitting/receiving commands and data in the selected communication mode, operations such as writing to

the flash memory are performed. Table 5-2 shows the major functions of flash memory programming.

Table 5-2. Functions of Flash Memory Programming

Function Description
Batch erase Erases all contents of memory
Batch blank check Checks erased state of entire memory
Data write Write to flash memory based on write start address and number of data written

(number of bytes)

Batch verify Compares all contents of memory with input data

5.3 Flashpro III Connection Example

How the Flashpro III is connected to the

PD78F9177 and µPD78F9177Y differs depending on the communication

µ

mode (3-wired serial I/O, SMB, UART, or pseudo 3-wire mode). Figures 5-2 to 5-5 show the connection in the
respective mode.

Figure 5-2. Flashpro III Connection in 3-wired Serial I/O Mode

µ

PD78F9177, 78F9177Y

V

PP

V

DD0

, V

DD1

, AV

RESET

SCK20
SI20
SO20
V

SS0

, V

SS1

, A

Note

Flashpro III

n = 1, 2

Note

VPPn

V

DD

RESET

CLK X1

SCK

SO

SI

GND

DD

VSS

Data Sheet U14022EJ1V0DS00

17