User’s Manual
78K0/FE2
8-Bit Single-Chip Microcontrollers
μ
PD78F0887(A)
μ
PD78F0888(A)
μ
PD78F0889(A)
μ
PD78F0890(A)
μ
PD78F0887(A2)
μ
PD78F0888(A2)
μ
PD78F0889(A2)
μ
PD78F0890(A2)
The 78K0/FE2 has an on-chip debug function.
Do not use this product for mass production after the on-chip debug function has been used because its reliability cannot
be guaranteed, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics
does not accept complaints concerning when use this product for mass production after the on-chip debug function has
been used.
Document No. U17554EJ4V0UD00 (4th edition)
Date Published March 2007 NS CP(K)
Printed in Japan
2005
[MEMO]
2
User’s Manual U17554EJ4V0UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
IL
CMOS device stays in the area between V
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IH
(MIN).
V
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
(MAX) and VIH (MIN) due to noise, etc., the device may
IL
(MAX) and
DD
or GND
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U17554EJ4V0UD
3
EEPROM is trademark of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash
is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
Caution: This product uses SuperFlash
®
technology licensed from Silicon Storage Technology, inc.
•
The information in this document is current as of March, 2007. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
•
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard":
"Special":
"Specific":
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
4
User’s Manual U17554EJ4V0UD
M8E 02. 11-1
[MEMO]
User’s Manual U17554EJ4V0UD
5
INTRODUCTION
Readers This manual is intended for user engineers who wish to understand the functions of the
78K0/FE2 and design and develop application systems and programs for these devices.
The target products are as follows.
78K0/FE2:
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The 78K0/FE2 manual are separated into two parts: this manual and the instructions
edition (common to the 78K/0 Series).
μ
PD78F0887 (A), 78F0888 (A), 78F0889 (A), 78F0890 (A)
78F0887 (A2), 78F0888 (A2), 78F0889 (A2), 78F0890 (A2)
78K0/FE2
User’s Manual
(This Manual)
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• Electrical specifications
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• When using this manual as the manual for (A) and (A2) grade products:
→ Only the quality grade differs between (A) grade products and (A2) grade
products.
Read the part number as follows.
• μPD78F0887→ μPD78F0887 (A), 78F0887 (A2)
•
μ
PD78F0888→ μPD78F0888 (A), 78F0888 (A2)
•
μ
PD78F0889→ μPD78F0889 (A), 78F0889 (A2)
•
μ
PD78F0890→ μPD78F0890 (A), 78F0890 (A2)
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark <R> shows major
revised points.
• How to interpret the register format:
→ For a bit number enclosed in brackets, the bit name is defined as a reserved word
in the assembler, and is already defined in the header file named sfrbit.h in the C
compiler.
• To check the details of a register when you know the register name:
→ Refer to APPENDIX C REGISTER INDEX.
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text.
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
Decimal
Hexadecimal
78K/0 Series
User’s Manual
Instructions
• CPU functions
• Instruction set
• Explanation of each instruction
...
×××× or ××××B
...
××××
...
××××H
6
User’s Manual U17554EJ4V0UD
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
78K0/FE2 User’s Manual This manual
78K/0 Series Instructions User’s Manual U12326E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
RA78K0 Ver.3.80 Assembler Package
ID78K0-QB Ver. 2.90 Integrated Debugger Operation U17437E
PM plus Ver. 5.20 U16934E
Operation U17199E
Language U17198E
Structured Assembly Language U17197E
Operation U17201E CC78K0 Ver.3.70 C Compiler
Language U17200E
Documents Related to Development Tools (Hardware) (User’s Manuals)
<R>
<R>
Document Name Document No.
QB-78K0FX2 In-Circuit Emulator U17534E
QB-78K0MINI ON-CHIP DEBUG Emulator U17029E
QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E
Documents Related to Flash Memory Programming
Document Name Document No.
PG-FP4 Flash Memory Programmer User’s Manual U15260E
PG-FPL3 Flash Memory Programmer User’s Manual U17454E
Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U17554EJ4V0UD
7
CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 17
1.1 Features......................................................................................................................................... 17
1.2 Applications .................................................................................................................................. 18
1.3 Ordering Information ................................................................................................................... 18
1.4 Pin Configuration (Top View) ...................................................................................................... 19
1.5 Fx2 Series Lineup......................................................................................................................... 21
1.5.1 78K0/Fx2 product lineup ................................................................................................................... 21
1.6 Block Diagram .............................................................................................................................. 23
1.7 Outline of Functions .................................................................................................................... 24
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 26
2.1 Pin Function List .......................................................................................................................... 26
2.2 Description of Pin Functions ...................................................................................................... 30
2.2.1 P00, P01, P05, P06 (port 0) .............................................................................................................. 30
2.2.2 P10 to P17 (port 1) ............................................................................................................................ 31
2.2.3 P30 to P33 (port 3) ............................................................................................................................ 32
2.2.4 P40 to P43 (port 4) ............................................................................................................................ 32
2.2.5 P50 to P53 (port 5) ............................................................................................................................ 33
2.2.6 P60 to P63 (port 6) ............................................................................................................................ 33
2.2.7 P70 to P76 (port 7) ............................................................................................................................ 33
2.2.8 P80 to P87 (port 8) ............................................................................................................................ 34
2.2.9 P90 to P93 (port 9) ............................................................................................................................ 34
2.2.10 P120 to P124 (port 12) .................................................................................................................... 34
2.2.11 P130 to P132 (port 13) .................................................................................................................... 35
2.2.12 AVREF............................................................................................................................................... 36
2.2.13 AVSS ................................................................................................................................................ 36
2.2.14 RESET ............................................................................................................................................ 36
2.2.15 REGC.............................................................................................................................................. 36
2.2.16 VDD and EVDD .................................................................................................................................. 36
2.2.17 VSS and EVSS................................................................................................................................... 36
2.2.18 FLMD0 ............................................................................................................................................ 36
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 37
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 41
3.1 Memory Space .............................................................................................................................. 41
3.1.1 Internal program memory space........................................................................................................ 48
3.1.2 Bank area (
3.1.3 Internal data memory space.............................................................................................................. 51
3.1.4 Special function register (SFR) area ................................................................................................. 51
3.1.5 Data memory addressing .................................................................................................................. 51
μ
PD78F0889 and 78F0890 only).................................................................................... 49
3.2 Processor Registers .................................................................................................................... 56
3.2.1 Control registers ................................................................................................................................ 56
3.2.2 General-purpose registers................................................................................................................. 60
3.2.3 Special Function Registers (SFRs) ................................................................................................... 61
3.3 Instruction Address Addressing................................................................................................. 68
8
User’s Manual U17554EJ4V0UD
3.3.1 Relative addressing............................................................................................................................68
3.3.2 Immediate addressing........................................................................................................................69
3.3.3 Table indirect addressing ...................................................................................................................70
3.3.4 Register addressing ...........................................................................................................................70
3.4 Operand Address Addressing .................................................................................................... 71
3.4.1 Implied addressing .............................................................................................................................71
3.4.2 Register addressing ...........................................................................................................................72
3.4.3 Direct addressing ...............................................................................................................................73
3.4.4 Short direct addressing ......................................................................................................................74
3.4.5 Special function register (SFR) addressing........................................................................................75
3.4.6 Register indirect addressing............................................................................................................... 76
3.4.7 Based addressing ..............................................................................................................................77
3.4.8 Based indexed addressing.................................................................................................................78
3.4.9 Stack addressing................................................................................................................................79
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0889, 78F0890 ONLY) .................. 80
4.1 Memory Bank................................................................................................................................ 80
4.2 Difference in Representation of Memory Space ....................................................................... 81
4.3 Memory Bank Select Register (BANK)....................................................................................... 82
4.4 Selecting Memory Bank............................................................................................................... 83
4.4.1 Referencing values between memory banks .....................................................................................83
4.4.2 Branching instruction between memory banks...................................................................................85
4.4.3 Subroutine call between memory banks ............................................................................................87
4.4.4 Instruction branch to bank area by interrupt.......................................................................................89
CHAPTER 5 PORT FUNCTIONS ........................................................................................................... 91
5.1 Port Functions.............................................................................................................................. 91
5.2 Port Configuration ....................................................................................................................... 92
5.2.1 Port 0 .................................................................................................................................................93
5.2.2 Port 1 .................................................................................................................................................95
5.2.3 Port 3 .................................................................................................................................................98
5.2.4 Port 4 ...............................................................................................................................................100
5.2.5 Port 5 ...............................................................................................................................................101
5.2.6 Port 6 ...............................................................................................................................................102
5.2.7 Port 7 ...............................................................................................................................................103
5.2.8 Port 8 ...............................................................................................................................................108
5.2.9 Port 9 ...............................................................................................................................................109
5.2.10 Port 12 ...........................................................................................................................................110
5.2.11 Port 13 ...........................................................................................................................................113
5.3 Registers Controlling Port Function ........................................................................................ 116
5.4 Port Function Operations.......................................................................................................... 123
5.4.1 Writing to I/O port.............................................................................................................................123
5.4.2 Reading from I/O port.......................................................................................................................123
5.4.3 Operations on I/O port......................................................................................................................123
5.5 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 124
CHAPTER 6 CLOCK GENERATOR .................................................................................................... 125
6.1 Functions of Clock Generator................................................................................................... 125
User’s Manual U17554EJ4V0UD
9
6.2 Configuration of Clock Generator ............................................................................................ 126
6.3 Registers Controlling Clock Generator.................................................................................... 128
6.4 System Clock Oscillator ............................................................................................................ 137
6.4.1 X1 oscillator......................................................................................................................................137
6.4.2 XT1 oscillator....................................................................................................................................137
6.4.3 When subsystem clock is not used ..................................................................................................140
6.4.4 Internal high-speed oscillator............................................................................................................140
6.4.5 Internal low-speed oscillator.............................................................................................................140
6.4.6 Prescaler ..........................................................................................................................................140
6.5 Clock Generator Operation ....................................................................................................... 141
6.6 Controlling Clock........................................................................................................................ 145
6.6.1 Controlling high-speed system clock ................................................................................................145
6.6.2 Example of controlling internal high-speed oscillation clock .............................................................148
6.6.3 Example of controlling subsystem clock...........................................................................................150
6.6.4 Controlling internal low-speed oscillation clock ................................................................................152
6.6.5 Clocks supplied to CPU and peripheral hardware ............................................................................152
6.6.6 CPU clock status transition diagram.................................................................................................153
6.6.7 Condition before changing CPU clock and processing after changing CPU clock ...........................158
6.6.8 Time required for switchover of CPU clock and main system clock .................................................159
6.6.9 Conditions before clock oscillation is stopped ..................................................................................160
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03 ........................................................... 161
7.1 Functions of 16-Bit Timer/Event Counters 00 to 03................................................................ 161
7.2 Configuration of 16-Bit Timer/Event Counters 00 to 03 ......................................................... 162
7.3 Registers Controlling 16-Bit Timer/Event Counters 00 to 03................................................. 171
7.4 Operation of 16-Bit Timer/Event Counters 00 to 03................................................................ 192
7.4.1 Interval timer operation.....................................................................................................................192
7.4.2 PPG output operations .....................................................................................................................195
7.4.3 Pulse width measurement operations ..............................................................................................198
7.4.4 External event counter operation......................................................................................................206
7.4.5 Square-wave output operation .........................................................................................................209
7.4.6 One-shot pulse output operation ......................................................................................................211
7.5 Special Use of TM0n .................................................................................................................. 216
7.5.1 Rewriting CR01n during TM0n operation .........................................................................................216
7.5.2 Setting LVS0n and LVR0n ...............................................................................................................216
7.6 Cautions for 16-Bit Timer/Event Counters 00 to 03 ................................................................ 218
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 222
8.1 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................... 222
8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 ........................................................ 224
8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51................................................ 226
8.4 Operations of 8-Bit Timer/Event Counters 50 and 51............................................................. 231
8.4.1 Operation as interval timer ...............................................................................................................231
8.4.2 Operation as external event counter ................................................................................................233
8.4.3 Square-wave output operation .........................................................................................................234
8.4.4 PWM output operation......................................................................................................................235
8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................... 239
10
User’s Manual U17554EJ4V0UD
CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 240
9.1 Functions of 8-Bit Timers H0 and H1 ....................................................................................... 240
9.2 Configuration of 8-Bit Timers H0 and H1................................................................................. 240
9.3 Registers Controlling 8-Bit Timers H0 and H1 ........................................................................ 244
9.4 Operation of 8-Bit Timers H0 and H1 ....................................................................................... 249
9.4.1 Operation as interval timer/square-wave output............................................................................... 249
9.4.2 Operation as PWM output mode......................................................................................................252
9.4.3 Carrier generator mode operation (8-bit timer H1 only)....................................................................258
CHAPTER 10 WATCH TIMER ............................................................................................................. 265
10.1 Functions of Watch Timer ....................................................................................................... 265
10.2 Configuration of Watch Timer................................................................................................. 266
10.3 Register Controlling Watch Timer.......................................................................................... 267
10.4 Watch Timer Operations.......................................................................................................... 269
10.4.1 Watch timer operation .................................................................................................................... 269
10.4.2 Interval timer operation ..................................................................................................................270
10.5 Cautions for Watch Timer ....................................................................................................... 271
CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 272
11.1 Functions of Watchdog Timer ................................................................................................ 272
11.2 Configuration of Watchdog Timer.......................................................................................... 273
11.3 Register Controlling Watchdog Timer ................................................................................... 274
11.4 Operation of Watchdog Timer................................................................................................. 275
11.4.1 Controlling operation of watchdog timer.........................................................................................275
11.4.2 Setting overflow time of watchdog timer.........................................................................................277
11.4.3 Setting window open period of watchdog timer..............................................................................278
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 280
12.1 Functions of Clock Output/Buzzer Output Controller.......................................................... 280
12.2 Configuration of Clock Output/Buzzer Output Controller ................................................... 281
12.3 Register Controlling Clock Output/Buzzer Output Controller............................................. 281
12.4 Clock Output/Buzzer Output Controller Operations............................................................. 284
12.4.1 Clock output operation ...................................................................................................................284
12.4.2 Operation as buzzer output............................................................................................................284
CHAPTER 13 A/D CONVERTER ......................................................................................................... 285
13.1 Function of A/D Converter ...................................................................................................... 285
13.2 Configuration of A/D Converter .............................................................................................. 286
13.3 Registers Used in A/D Converter ........................................................................................... 288
13.4 A/D Converter Operations ....................................................................................................... 296
13.4.1 Basic operations of A/D converter.................................................................................................. 296
13.4.2 Input voltage and conversion results..............................................................................................298
13.4.3 A/D converter operation mode .......................................................................................................299
13.5 How to Read A/D Converter Characteristics Table .............................................................. 301
13.6 Cautions for A/D Converter..................................................................................................... 303
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61.......................................................... 307
14.1 Functions of Serial Interfaces UART60 and UART61 ........................................................... 307
User’s Manual U17554EJ4V0UD
11
14.2 Configurations of Serial Interface UART60 and UART61..................................................... 312
14.3 Registers Controlling Serial Interfaces UART60 and UART61 ............................................ 316
14.4 Operations of Serial Interface UART60 and UART61............................................................ 335
14.4.1 Operation stop mode......................................................................................................................335
14.4.2 Asynchronous serial interface (UART) mode .................................................................................336
14.4.3 Dedicated baud rate generator.......................................................................................................351
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 ................................................................ 357
15.1 Functions of Serial Interfaces CSI10 and CSI11 ................................................................... 357
15.2 Configuration of Serial Interfaces CSI10 and CSI11 ............................................................. 358
15.3 Registers Controlling Serial Interfaces CSI10 and CSI11 .................................................... 360
15.4 Operation of Serial Interfaces CSI10 and CSI11.................................................................... 365
15.4.1 Operation stop mode......................................................................................................................365
15.4.2 3-wire serial I/O mode ....................................................................................................................366
CHAPTER 16 CAN CONTROLLER ..................................................................................................... 378
16.1 Outline Description .................................................................................................................. 378
16.1.1 Features .........................................................................................................................................378
16.1.2 Overview of functions .....................................................................................................................379
16.1.3 Configuration ..................................................................................................................................380
16.2 CAN Protocol ............................................................................................................................ 381
16.2.1 Frame format..................................................................................................................................381
16.2.2 Frame types ...................................................................................................................................382
16.2.3 Data frame and remote frame ........................................................................................................382
16.2.4 Error frame .....................................................................................................................................390
16.2.5 Overload frame...............................................................................................................................391
16.3 Functions .................................................................................................................................. 392
16.3.1 Determining bus priority .................................................................................................................392
16.3.2 Bit stuffing ......................................................................................................................................392
16.3.3 Multi masters..................................................................................................................................392
16.3.4 Multi cast ........................................................................................................................................392
16.3.5 CAN sleep mode/CAN stop mode function ....................................................................................392
16.3.6 Error control function ......................................................................................................................393
16.3.7 Baud rate control function ..............................................................................................................399
16.4 Connection with Target System.............................................................................................. 403
16.5 Internal Registers of CAN Controller...................................................................................... 404
16.5.1 CAN controller configuration...........................................................................................................404
16.5.2 Register access type ......................................................................................................................405
16.5.3 Register bit configuration................................................................................................................414
16.6 Bit Set/Clear Function.............................................................................................................. 418
16.7 Control Registers ..................................................................................................................... 420
16.8 CAN Controller Initialization.................................................................................................... 455
16.8.1 Initialization of CAN module ...........................................................................................................455
16.8.2 Initialization of message buffer.......................................................................................................455
16.8.3 Redefinition of message buffer.......................................................................................................455
16.8.4 Transition from initialization mode to operation mode ....................................................................456
16.8.5 Resetting error counter C0ERC of CAN module ............................................................................457
16.9 Message Reception.................................................................................................................. 458
12
User’s Manual U17554EJ4V0UD
16.9.1 Message reception.........................................................................................................................458
16.9.2 Receive Data Read ........................................................................................................................459
16.9.3 Receive history list function............................................................................................................460
16.9.4 Mask function.................................................................................................................................462
16.9.5 Multi buffer receive block function..................................................................................................464
16.9.6 Remote frame reception.................................................................................................................465
16.10 Message Transmission.......................................................................................................... 466
16.10.1 Message transmission .................................................................................................................466
16.10.2 Transmit history list function.........................................................................................................468
16.10.3 Automatic block transmission (ABT) ............................................................................................470
16.10.4 Transmission abort process .........................................................................................................471
16.10.5 Remote frame transmission .........................................................................................................472
16.11 Power Save Modes................................................................................................................. 473
16.11.1 CAN sleep mode .......................................................................................................................... 473
16.11.2 CAN stop mode............................................................................................................................ 475
16.11.3 Example of using power saving modes........................................................................................476
16.12 Interrupt Function .................................................................................................................. 477
16.13 Diagnosis Functions and Special Operational Modes ....................................................... 478
16.13.1 Receive-only mode ......................................................................................................................478
16.13.2 Single-shot mode .........................................................................................................................479
16.13.3 Self-test mode..............................................................................................................................480
16.13.4 Receive/Transmit Operation in Each Operation Mode ................................................................. 481
16.14 Time Stamp Function............................................................................................................. 482
16.14.1 Time stamp function.....................................................................................................................482
16.15 Baud Rate Settings ................................................................................................................ 484
16.15.1 Baud rate settings ........................................................................................................................484
16.15.2 Representative examples of baud rate settings ...........................................................................488
16.16 Operation of CAN Controller................................................................................................. 492
CHAPTER 17 INTERRUPT FUNCTIONS ............................................................................................ 518
17.1 Interrupt Function Types......................................................................................................... 518
17.2 Interrupt Sources and Configuration ..................................................................................... 518
17.3 Registers Controlling Interrupt Functions ............................................................................ 522
17.4 Interrupt Servicing Operations ............................................................................................... 530
17.4.1 Maskable interrupt acknowledgement............................................................................................530
17.4.2 Software interrupt request acknowledgement ................................................................................532
17.4.3 Multiple interrupt servicing .............................................................................................................533
17.4.4 Interrupt request hold .....................................................................................................................536
CHAPTER 18 STANDBY FUNCTION .................................................................................................. 537
18.1 Standby Function and Configuration..................................................................................... 537
18.1.1 Standby function ............................................................................................................................537
18.1.2 Registers controlling standby function............................................................................................537
18.2 Standby Function Operation................................................................................................... 540
18.2.1 HALT mode....................................................................................................................................540
18.2.2 STOP mode ...................................................................................................................................546
User’s Manual U17554EJ4V0UD
13
CHAPTER 19 RESET FUNCTION........................................................................................................ 553
19.1 Register for Confirming Reset Source................................................................................... 561
CHAPTER 20 MULTIPLIER/DIVIDER ................................................................................................... 562
20.1 Functions of Multiplier/Divider................................................................................................ 562
20.2 Configuration of Multiplier/Divider ......................................................................................... 562
20.3 Register Controlling Multiplier/Divider .................................................................................. 566
20.4 Operations of Multiplier/Divider.............................................................................................. 567
20.4.1 Multiplication operation...................................................................................................................567
20.4.2 Division operation...........................................................................................................................569
CHAPTER 21 POWER-ON-CLEAR CIRCUIT...................................................................................... 571
21.1 Functions of Power-on-Clear Circuit...................................................................................... 571
21.2 Configuration of Power-on-Clear Circuit ............................................................................... 572
21.3 Operation of Power-on-Clear Circuit...................................................................................... 572
21.4 Cautions for Power-on-Clear Circuit ...................................................................................... 575
CHAPTER 22 LOW-VOLTAGE DETECTOR ....................................................................................... 577
22.1 Functions of Low-Voltage Detector........................................................................................ 577
22.2 Configuration of Low-Voltage Detector ................................................................................. 578
22.3 Registers Controlling Low-Voltage Detector......................................................................... 578
22.4 Operation of Low-Voltage Detector........................................................................................ 581
22.4.1 When used as reset .......................................................................................................................582
22.4.2 When used as interrupt ..................................................................................................................587
22.5 Cautions for Low-Voltage Detector ........................................................................................ 592
CHAPTER 23 OPTION BYTE............................................................................................................... 595
23.1 Functions of Option Bytes ...................................................................................................... 595
23.2 Format of Option Byte ............................................................................................................. 597
CHAPTER 24 FLASH MEMORY .......................................................................................................... 600
24.1 Internal Memory Size Switching Register.............................................................................. 600
24.2 Internal Expansion RAM Size Switching Register ................................................................ 601
24.3 Writing with Flash Memory Programmer ............................................................................... 602
24.4 Programming Environment ..................................................................................................... 605
24.5 Communication Mode.............................................................................................................. 605
24.6 Connection of Pins on Board.................................................................................................. 607
24.6.1 FLMD0 pin......................................................................................................................................607
24.6.2 Serial interface pins........................................................................................................................607
24.6.3 RESET pin......................................................................................................................................609
24.6.4 Port pins .........................................................................................................................................609
24.6.5 REGC pin .......................................................................................................................................609
24.6.6 Other signal pins ............................................................................................................................609
24.6.7 Power supply..................................................................................................................................610
24.7 Programming Method .............................................................................................................. 611
24.7.1 Controlling flash memory................................................................................................................611
24.7.2 Flash memory programming mode.................................................................................................611
14
User’s Manual U17554EJ4V0UD
24.7.3 Selecting communication mode .....................................................................................................612
24.7.4 Communication commands............................................................................................................ 613
24.8 Security Settings...................................................................................................................... 614
24.9 Processing Time for Each Command When PG-FP4 Is Used (Reference) ........................ 616
24.10 Flash Memory Programming by Self-Programming........................................................... 617
24.10.1 Registers used for self-programming function..............................................................................624
24.11 Boot Swap Function .............................................................................................................. 628
CHAPTER 25 ON-CHIP DEBUG FUNCTION ..................................................................................... 630
25.1 Outline of Functions ................................................................................................................ 630
25.2 Connection with MINICUBE .................................................................................................... 631
25.3 Connection Circuit Examples ................................................................................................. 632
25.4 On-Chip Debug Security ID..................................................................................................... 634
25.5 Restrictions and Cautions on On-Chip Debug Function ..................................................... 634
CHAPTER 26 INSTRUCTION SET ...................................................................................................... 635
26.1 Conventions Used in Operation List...................................................................................... 635
26.1.1 Operand identifiers and specification methods ..............................................................................635
26.1.2 Description of operation column.....................................................................................................636
26.1.3 Description of flag operation column ..............................................................................................636
26.2 Operation List........................................................................................................................... 637
26.3 Instructions Listed by Addressing Type ............................................................................... 645
CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) .................................. 648
27.1 Absolute Maximum Ratings .................................................................................................... 648
27.2 Oscillator Characteristics........................................................................................................ 650
27.3 DC Characteristics ................................................................................................................... 652
27.4 AC Characteristics ................................................................................................................... 659
27.5 Data Retention Characteristics............................................................................................... 669
27.6 Flash EEPROM Programming Characteristics...................................................................... 670
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)................................ 671
28.1 Absolute Maximum Ratings .................................................................................................... 671
28.2 Oscillator Characteristics........................................................................................................ 673
28.3 DC Characteristics ................................................................................................................... 675
28.4 AC Characteristics ................................................................................................................... 681
28.5 Data Retention Characteristics............................................................................................... 691
28.6 Flash EEPROM Programming Characteristics...................................................................... 692
CHAPTER 29 PACKAGE DRAWINGS ................................................................................................ 693
CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS........................................................... 695
CHAPTER 31 CAUTIONS FOR WAIT ................................................................................................ 696
31.1 Cautions for Wait ..................................................................................................................... 696
31.2 Peripheral Hardware That Generates Wait ............................................................................ 697
31.3 Example of Wait Occurrence .................................................................................................. 699
User’s Manual U17554EJ4V0UD
15
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 700
A.1 Software Package ...................................................................................................................... 704
A.2 Language Processing Software ............................................................................................... 704
A.3 Control Software ........................................................................................................................ 705
A.4 Flash Memory Programming Tools.......................................................................................... 706
A.4.1 When using flash memory programmer FG-FP4, FL-PR4, PG-FPL3, and FP-LITE3 ......................706
A.4.2 When using on-chip debug emulator with programming function QB-MINI2....................................706
A.5 Debugging Tools (Hardware).................................................................................................... 707
A.5.1 When using in-circuit emulator QB-78K0FX2...................................................................................707
A.5.2 When using on-chip debug emulator QB-78K0MINI ........................................................................707
A.5.3 When using on-chip debug emulator with programming function QB-MINI2....................................708
A.6 Debugging Tools (Software)..................................................................................................... 708
APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 709
APPENDIX C REGISTER INDEX ......................................................................................................... 711
C.1 Register Index (In Alphabetical Order with Respect to Register Names)............................ 711
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................... 716
APPENDIX D REVISION HISTORY ..................................................................................................... 721
D.1 Main Revisions in this Edition.................................................................................................. 721
D.2 Revision History of Preceding Editions .................................................................................. 722
16
User’s Manual U17554EJ4V0UD
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.1
speed system clock) to ultra low-speed (122
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
μ
s: @ 32.768 kHz operation with subsystem clock)
μ
s: @ 20 MHz operation with high-
Part Number
μ
PD78F0887
μ
PD78F0888
μ
PD78F0889
μ
PD78F0890
Program Memory
(ROM)
Flash memory
60 KB
96KB 4096 bytes
128 KB 6144 bytes
Note
48 KB 1024 bytes 2048 bytes
Internal High-Speed RAM
Data Memory Item
Note
Internal Expansion RAM
Note The internal flash memory, internal high-speed RAM capacities, and internal expansion RAM capacities
can be changed using the internal memory size switching register (IMS) and the internal expansion RAM
size switching register (IXS).
{ On-chip single-power-supply flash memory
{ Self-programming (with boot swap function)
{ On-chip debug function
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ Short startup is possible via the CPU default start using the on-chip internal high-speed oscillator
{ On-chip watchdog timer (operable with on-chip internal low-speed oscillator clock)
{ On-chip multiplier/divider
{ On-chip clock output/buzzer output controller
{ I/O ports: 55 (N-ch open drain: 4)
{ Timer: 10 channels
{ Serial interface: 4 channels
(UART (LIN (Local Interconnect Network)-bus supported): 1 channel,
CSI/UART
Note
: 1 channel, CSI: 1 channel, CAN: 1 channel)
{ 10-bit resolution A/D converter: 12 channels
{ Supply voltage: V
(with internal high-speed oscillator clock or subsystem clock: V
{ Operating ambient temperature: T
DD = 4.0 to 5.5 V when 20 MHz, VDD = 2.7 to 5.5 V when 10 MHz, VDD = 1.8 to 5.5 V when 5 MHz
DD = 1.8 to 5.5 V)
A = −40 to +85°C, −40 to +125°C
Note Select either of the functions of these alternate-function pins.
Note
User’s Manual U17554EJ4V0UD
17
CHAPTER 1 OUTLINE
1.2 Applications
{ Automotive electrical appliances (Body control, Door control, Front light control)
{ Industrial equipment (Industrial robot, Building control)
1.3 Ordering Information
• Flash memory version
Part Number Package Quality Grade
μ
PD78F0887GK(A)-GAJ-AX 64-pin plastic LQFP (12x12) Special
μ
PD78F0887GK(A2)-GAJ-AX 64-pin plastic LQFP (12x12) Special
μ
PD78F0887GB(A)-GAH-AX 64-pin plastic LQFP (Fine pitch) (10x10) Special
μ
PD78F0887GB(A2)-GAH-AX 64-pin plastic LQFP (Fine pitch) (10x10) Special
μ
PD78F0888GK(A)-GAJ-AX 64-pin plastic LQFP (12x12) Special
μ
PD78F0888GK(A2)-GAJ-AX 64-pin plastic LQFP (12x12) Special
μ
PD78F0888GB(A)-GAH-AX 64-pin plastic LQFP (Fine pitch) (10x10) Special
μ
PD78F0888GB(A2)-GAH-AX 64-pin plastic LQFP (Fine pitch) (10x10) Special
μ
PD78F0889GK(A)-GAJ-AX 64-pin plastic LQFP (12x12) Special
μ
PD78F0889GK(A2)-GAJ-AX 64-pin plastic LQFP (12x12) Special
μ
PD78F0889GB(A)-GAH-AX 64-pin plastic LQFP (Fine pitch) (10x10) Special
μ
PD78F0889GB(A2)-GAH-AX 64-pin plastic LQFP (Fine pitch) (10x10) Special
μ
PD78F0890GK(A)-GAJ-AX 64-pin plastic LQFP (12x12) Special
μ
PD78F0890GK(A2)-GAJ-AX 64-pin plastic LQFP (12x12) Special
μ
PD78F0890GB(A)-GAH-AX 64-pin plastic LQFP (Fine pitch) (10x10) Special
μ
PD78F0890GB(A2)-GAH-AX 64-pin plastic LQFP (Fine pitch) (10x10) Special
Remark All these products are lead free products.
18
User’s Manual U17554EJ4V0UD
1.4 Pin Configuration (Top View)
• 64-pin plastic LQFP (12x12)
• 64-pin plastic LQFP (Fine pitch) (10x10)
P131/TI003
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P120/INTP0/EXLVI
P43
P42
P41
P40
RESET
P124/XT2/EXCLKS
P123/XT1
FLMD0
P122/X2/EXCLK
P121/X1
REGC
V
EV
V
EV
SS
SS
DD
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CHAPTER 1 OUTLINE
P132/TI013/TO03
P00/TI000
P01/TI010/TO00
P80/ANI0
P81/ANI1
P82/ANI2
P83/ANI3
P84/ANI4
P85/ANI5
P86/ANI6
P87/ANI7
P90/ANI8
P91/ANI9
P92/ANI10
P93/ANI11
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AV
SS
AV
REF
P10/SCK10/TxD61
P11/SI10/RxD61
P12/SO10
P13/TxD60
P14/RxD60
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P30/INTP1
P53
P52
P51
P50
P31/TI002/INTP2
P60
P61
P62
P63
P130
P75/SI11
P74/SO11
P76/SCK11
P73/BUZ/INTP7
P33/TI51/TO51/INTP4
P70/CTxD
P71/CRxD
P72/PCL/INTP6
P06/TI011/TO01
P05/SSI11/TI001
P32/TI012/TO02/INTP3
Cautions 1. Make AV
2. Make EV
3. Connect the REGC pin to V
SS and EVSS the same potential as VSS.
DD the same potential as VDD.
SS via a capacitor (0.47 to 1
μ
F: recommended).
4. ANI0/P80 to ANI11/P93 are set in the analog input mode after release of reset.
User’s Manual U17554EJ4V0UD
19
CHAPTER 1 OUTLINE
Pin Identification
ANI0 to ANI11: Analog input
AV
REF: Analog reference voltage
AV
SS: Analog ground
BUZ: Buzzer output
CRxD: Receive data for CAN
CTxD: Transmit data for CAN
EV
DD: Power supply for port
EV
SS: Ground for port
EXCLK: External clock input
(Main system clock)
EXCLKS: External clock input
(Subsystem clock)
EXLVI: External potential input
for low-voltage detector
FLMD0: Flash programming mode
INTP0 to INTP7: External interrupt input
P00, P01,
P05, P06
: Port 0
P10 to P17: Port 1
P30 to P33: Port 3
P40 to P43: Port 4
P50 to P53: Port 5
P60 to P63: Port 6
P70 to P76: Port 7
P80 to P87: Port 8
P90 to P93: Port 9
P120 to P124: Port 12
P130 to P132: Port 13
PCL: Programmable clock output
REGC: Regulator Capacitance
RESET: Reset
RxD60, RxD61: Receive data
SCK10, SCK11: Serial clock input/output
SI10, SI11: Serial data input
SO10, SO11: Serial data output
SSI11: Serial interface chip select input
TI000, TI010,
TI001, TI011,
TI002, TI012,
TI003, TI013,
TI50, TI51: Timer input
TO00, TO01,
TO02, TO03
TO50, TO51,
TOH0, TOH1: Timer output
TxD60, TxD61: Transmit data
V
DD: Power supply
V
SS: Ground
X1, X2: Crystal oscillator (high-speed system clock)
XT1, XT2: Crystal oscillator (subsystem clock)
20
User’s Manual U17554EJ4V0UD
CHAPTER 1 OUTLINE
1.5 Fx2 Series Lineup
1.5.1 78K0/Fx2 product lineup
•
44-pin LQFP (10 × 10 mm 0.8 mm pitch)
78K0/FC2
μ
PD78F0881
Single-power-supply flash
memory: 32 KB,
RAM: 2 KB
48-pin LQFP (7 × 7 mm 0.5 mm pitch)
•
78K0/FC2
μ
PD78F0884
Single-power-supply flash
memory: 32 KB,
RAM: 2 KB
•
64-pin LQFP (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch)
78K0/FE2
•
80-pin LQFP (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch)
78K0/FF2
Remark All product with on-chip debug function.
μ
PD78F0882
Single-power-supply flash
memory: 48 KB,
RAM: 3 KB
μ
PD78F0885
Single-power-supply flash
memory: 48 KB,
RAM: 3 KB
μ
PD78F0887
Single-power-supply flash
memory: 48 KB,
RAM: 3 KB
Single-power-supply flash
memory: 60KB,
RAM: 3 KB
Single-power-supply flash
memory: 60KB,
RAM: 3 KB
Single-power-supply flash
memory: 60 KB,
RAM: 3 KB
Single-power-supply flash
memory: 60 KB,
RAM: 3 KB
μ
PD78F0883
μ
PD78F0886
μ
PD78F0888
μ
PD78F0891
μ
PD78F0889
Single-power-supply flash
memory: 96 KB,
RAM: 5 KB
μ
PD78F0892
Single-power-supply flash
memory: 96 KB,
RAM: 5 KB
μ
PD78F0890
Single-power-supply flash
memory: 128 KB,
RAM: 7 KB
μ
PD78F0893
Single-power-supply flash
memory: 128 KB,
RAM: 7 KB
User’s Manual U17554EJ4V0UD
21
CHAPTER 1 OUTLINE
The list of functions in the 78K0/Fx2 is shown below.
Part Number
Item
Number of pins 44 pins 48 pins 64 pins 80 pins
Flash memory 32 K/48 K/60 K 48 K/60 K/96 K/128 K 60 K/96 K/128 K Internal
memory
(bytes)
Power supply voltage VDD = 4.0 to 5.5 V when 20 MHz, VDD = 2.7 to 5.5 V when 10 MHz,
Minimum instruction execution time 0.1 μs (when 20 MHz, VDD = 4.0 to 5.5 V)
Clock
Ports
Timer
Serial
interface
10-bit A/D converter 8 ch 9 ch 12 ch 16 ch
Interrupts
<R>
Reset
Multiplier/divider Provided
Clock output/buzzer output Provided
Self-programming function Provided
On-chip debug function Provided
Standby function HALT/STOP mode
Operating ambient temperature TA = −40 to +85°C, −40 to +125°C
RAM 2 K/3 K/3 K 3 K/3 K/5 K/7 K 3 K/5 K/7 K
Crystal/ceramic 4 to 20 MHz
Subclock 32.768 kHz
Internal low-speed
oscillator
Internal high-speed
oscillator
CMOS I/O 33 36 50 66
CMOS output 1
N-ch open-drain I/O 3 4
16 bits (TM0) 2 ch
8 bits (TM5) 2 ch
8 bits (TMH) 2 ch
For watch 1 ch
WDT 1 ch
CAN 1 ch
3-wire CSI
LIN-UART 1 ch
LIN-UART/CSI 1 ch
External 8
Internal 24 29
RESET pin Provided
POC 1.59 V ±0.15 V (detection voltage is fixed)
LVI 4.24/4.09/3.93/3.78/3.62/3.47/3.32/3.16/3.01/2.85/2.70/2.55/2.39/2.24/2.08/1.93 V
WDT Provided
78K0/FC2
DD = 1.8 to 5.5 V when 5 MHz
V
8 MHz (TYP., V
Note
4 ch
−
78K0/FE2 78K0/FF2
240 kHz (TYP.)
DD = 2.7 to 5.5 V)
1 ch
(selectable by software)
Note Since TM01 does not have the following terminal at 78K0/FC2, the function is restricted in part.
μ
μ
PD78F0881, 78F0882, and 78F0883: TI001, TI011, TO01
PD78F0884, 78F0885, and 78F0886: TI001
22
User’s Manual U17554EJ4V0UD
1.6 Block Diagram
CHAPTER 1 OUTLINE
TO00/TI010/P01
TI000/P00 (LINSEL)
RxD60/P14 (LINSEL)
TO01/TI011/P06
TI001/P05
TO02/TI012/P32
TI002/P31
TO03/TI013/P132
TI003/P131
TOH0/P15
TOH1/P16
TI50/TO50/P17
TI51/TO51/P33
RxD60/P14
TxD60/P13
RxD61/P11
TxD61/P10
SCK10/P10
SI10/P11
SO10/P12
SSI11/P05
SO11/P73
SI11/P74
SCK11/P75
ANI0/P80-ANI7/P87
ANI8/P90-ANI11/P93
AV
AV
REF
16-bit timer/
event counter 00
16-bit timer/
event counter 01
16-bit timer/
event counter 02
16-bit timer/
event counter 03
8-bit timer H0
8-bit timer H1
8-bit timer/
event counter 50
8-bit timer/
event counter 51
Internal low-speed
oscillator
Watchdog timer
Watch timer
Serial
interface UART60
LINSEL
Serial
interface UART61
Serial
interface CSI10
Serial interface
CSI11
12
A/D converter
SS
78K/0
CPU
core
Bank
Internal
high-speed
RAM
EV
EV
DD
VSS,
Flash
memory
Internal
expansion
FLMD0VDD,
SS
RAM
Port 0
Port 1
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 12
Port 13
Buzzer output
Clock output control
Multiplier/Divider
Power on clear/
low voltage
indicator
Reset control
System control
Internal high-speed
oscillator
On-chip
debugger
4
P00, P01, P05, P06
8
P10-P17
4
P30-P33
4
P40-P43
4
P50-P53
4
P60-P63
7
P70-P76
8
P80-P87
4
P90-P93
5
P120-P124
P130
2
P131, P132
BUZ/P73
PCL/P72
POC/LVI
control
RESET
X1/P121
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
EXLVI/P120
INTP0/P120 (LINSEL)
RxD60/P14 (LINSEL)
INTP1/P30-
INTP4/P33
INTP5/P16
INTP6/P72
INTP7/P73
CRxD/P71
CTxD/P70
4
2
Interrupt control
CAN
User’s Manual U17554EJ4V0UD
23
CHAPTER 1 OUTLINE
1.7 Outline of Functions
(1/2)
Item
Internal
memory
(bytes)
Flash memory
(self-programming
supported)
Note
Bank
High-speed RAM
Expansion RAM
Note
Note
Memory space 64 KB
High-speed system clock
(oscillation frequency)
Internal high-speed oscillation
clock (oscillation frequency)
Internal low-speed oscillation
clock (oscillation frequency)
Subsystem clock
(oscillation frequency)
General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
time
Instruction set
I/O ports
Timers
Timer outputs 8 (PWM output: 4)
Clock output
Buzzer output 1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (high-speed system clock: 10 MHz)
A/D converter 10-bit resolution × 12 channels
Note The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM capacity
can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size
switching register (IXS).
μ
PD78F0887
μ
PD78F0888
μ
PD78F0889
μ
PD78F0890
48 K 60 K 96 K 128 K
− −
4 6
1 K
2 K 2 K 4 K 6 K
Crystal/ceramic oscillation (X1), external main system clock input (EXCLK)
4 to 20 MHz: V
4 to 5 MHz: V
On-chip internal oscillation (8 MHz (TYP.): V
DD = 4.0 to 5.5 V, 4 to 10 MHz: VDD = 2.7 to 5.5 V,
DD = 1.8 to 5.5 V
DD = 2.7 to 5.5 V)
On-chip internal oscillation (240 kHz (TYP.))
Crystal oscillation (XT1), external subsystem clock input (EXCLKS)
(32.768 kHz: V
DD = 1.8 to 5.5 V)
0.1 μs/0.2 μs/0.4 μs/0.8 μs/1.6 μs (high-speed system clock: @ fXP = 20 MHz operation)
0.25 μs/0.5 μs/1.0 μs/2.0 μs/4.0 μs (TYP.) (internal oscillator clock: @ fRH = 8 MHz (TYP.)
operation)
122
μ
s (subsystem clock: when operating at fXT = 32.768 kHz)
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
Total: 55
CMOS I/O 50
CMOS output 1
N-ch open-drain I/O 4
• 16-bit timer/event counter: 4 channels
• 8-bit timer/event counter: 2 channels
• 8-bit timer: 2 channels
• Watch timer 1 channel
• Watchdog timer: 1 channel
• 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(high-speed system clock: 10 MHz)
• 32.768 kHz (subsystem clock: 32.768 kHz)
24
User’s Manual U17554EJ4V0UD
<R>
CHAPTER 1 OUTLINE
Item
Serial interface
Multiplier/divider
Vectored
interrupt sources
Reset
On-chip debug function Provided
Supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = −40 to +85°C, −40 to +125°C
Package • 64-pin plastic LQFP(10x10)
CAN
3-wire CSI
LIN-UART
LIN-UART/
Note
CSI
Internal 29
External 8
μ
PD78F0887
• 16 bit x 16 bit = 32 bit (Multiplication)
• 32 bit ÷ 32 bit = 32 bit remainder of 16 bits (Division)
• Reset using RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
• 64-pin plastic LQFP(12x12)
μ
PD78F0888
μ
1 ch
1 ch
1 ch
1 ch
PD78F0889
μ
PD78F0890
Note Select either of the functions of these alternate-function pins.
An outline of the timer is shown below.
Operation
mode
Function
Interval timer 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch
External event counter 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch
Timer output 1 1 1 1 1 1 1 1
PPG output 1 1 1 1
PWM output
Pulse width measurement 2 2 2 2
Square-wave output 1 1 1 1 1 1 1 1
Interrupt source 2 2 2 2 1 1 1 1 1
16-Bit Timer/
Event Counters 00 to 03
TM00 TM01 TM02 TM03 TM50 TM51 TMH0 TMH1
− − − −
8-Bit Timer/
Event Counters
50 and 51
− − − − − −
1 1 1 1
− − − − − −
8-Bit Timers H0
and H1
− − − −
Watch Timer
1 channel
− −
− −
− −
Note In the watch timer, the watch timer function and interval timer function can be used simultaneously.
Remark TM51 and TMH1 can be used in combination as a carrier generator mode.
Watchdog
Note
1 channel
(2/2)
Timer
−
User’s Manual U17554EJ4V0UD
25
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are three types of pin I/O buffer power supplies: AV
power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P80 to P87, P90 to P93
EVDD Port pins other than P80 to P87, P90 to P93 and P121 to P124
VDD • P121 to P124
• Non-port pins
This section explains the names and functions of the pins of the 78K0/FE2.
(1) Port pins
REF, EVDD, and VDD. The relationship between these
Table 2-2. Port pins (1/2)
Pin Name I/O Function After Reset Alternate Function
P00 TI000
P01 TI010/TO00
P05 SSI11/TI001
P06
P10 SCK10/TxD61
P11 SI10/RxD61
P12 SO10
P13 TxD60
P14 RxD60
P15 TOH0
P16 TOH1/INTP5
P17
P30 INTP1
P31 INTP2/TI002
P32 INTP3/TI012/TO02
P33
P40 to P43 I/O
I/O
I/O
I/O
Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 4.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
Input
Input
Input
TI011/TO01
TI50/TO50
INTP4/TI51/TO51
−
26
User’s Manual U17554EJ4V0UD
CHAPTER 2 PIN FUNCTIONS
Table 2-2. Port pins (2/2)
Pin Name I/O Function After Reset Alternate Function
P50 to P53 I/O
P60 to P63 I/O
P70 CTxD
P71 CRxD
P72 PCL/INTP6
P73 BUZ/INTP7
P74 SO11
P75 SI11
P76
P80 to P87 I/O
P90 to P93 I/O
P120 INTP0/EXLVI
P121 X1
P122 X2/EXCLK
P123 XT1
P124
P130 Output Output
P131
P132
I/O
I/O
I/O
Port 5.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 6.
4-bit I/O port
Input/output can be
specified in 1-bit units.
Port 7.
7-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 8.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Port 9.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Port 12.
5-bit I/O port.
Only for P120, use of an on-chip pull-up resistor can be
specified by a software setting.
Port 13.
P130 is 1-bit output-only port.
P131 and P132 are 2-bit I/O port.
P131 and P132 use of an on-chip pull-up resistor can be
specified by a software setting.
N-ch open drain I/O port. Input
Input
Input
SCK11
Input ANI0 to ANI7
Input ANI8 to ANI11
Input
XT2/EXCLKS
Input
−
−
−
User’s Manual U17554EJ4V0UD
27
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Table 2-3. Non-port pins (1/2)
Pin Name I/O Function After Reset Alternate Function
INTP0 P120/EXLVI
INTP1 P30
INTP2 P31/TI002
INTP3 P32/TI012/TO02
INTP4 P33/TI51/TO51
INTP5 P16/TOH1
INTP6 P72/PCL
INTP7
SI10 P11/RxD61
SI11
SO10 P12
SO11
SCK10 P10/TxD61
SCK11
SSI11 Input Serial interface chip select input Input P05/TI001
RxD60 P14
RxD61
TxD60 P13
TxD61
TI000
TI001
TI002
TI003
TI010
TI011
TI012
TI013
TO00 16-bit timer/event counter 00 output P01/TI010
TO01 16-bit timer/event counter 01 output P06/TI011
TO02
Input
Input Serial data input to serial interface Input
Output Serial data output from serial interface Input
I/O Clock input/output for serial interface Input
Input Serial data input to asynchronous serial interface Input
Output Serial data output from asynchronous serial interface Input
Input
Output
External interrupt request input for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be
specified
External count clock input to 16-bit timer/event counter 00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
External count clock input to 16-bit timer/event counter 01
Capture trigger input to capture registers (CR001, CR011) of
16-bit timer/event counter 01
External count clock input to 16-bit timer/event counter 02
Capture trigger input to capture registers (CR002, CR012) of
16-bit timer/event counter 02
External count clock input to 16-bit timer/event counter 03
Capture trigger input to capture registers (CR003, CR013) of
16-bit timer/event counter 03
Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
Capture trigger input to capture register (CR001) of 16-bit
timer/event counter 01
Capture trigger input to capture register (CR002) of 16-bit
timer/event counter 02
Capture trigger input to capture register (CR003) of 16-bit
timer/event counter 03
16-bit timer/event counter 02 output
Input
Input
Input
P73/BUZ
P75
P74
P76
P11/SI10
P10/SCK10
P00
P05/SSI11
P31/INTP2
P131
P01/TO00
P06/TO01
P32/TO02/INTP3
P132/TO03
P32/TI012/INTP3
28
User’s Manual U17554EJ4V0UD
CHAPTER 2 PIN FUNCTIONS
Table 2-3. Non-port pins (2/2)
Pin Name I/O Function After Reset Alternate Function
TO03 Output 16-bit timer/event counter 03 output Input P132/TI013
TI50 External count clock input to 8-bit timer/event counter 50 P17/TO50
TI51
TO50 8-bit timer/event counter 50 output P17/TI50
TO51 8-bit timer/event counter 51 output P33/TI51/INTP4
TOH0 8-bit timer H0 output P15
TOH1
PCL Output
BUZ Output Buzzer output Input P73/INTP7
ANI0 to ANI11 Input A/D converter analog input Input P80 to P87
CTxD Input CAN transmit data output Input P70
CRxD Output CAN receive data input Input P71
AVREF Input
AVSS
RESET Input System reset input
X1 Input Input P121
X2
XT1 Input Input P123
XT2
EXCLK Input External clock input for main system clock Input P122/X2
EXCLKS Input External clock input for subsystem clock Input P124/XT2
EXLVI Input Potential input for external low-voltage detection Input P120/INTP0
VDD
EVDD
VSS
EVSS
FLMD0
REGC
Input
Output
−
−
−
−
−
−
−
−
−
External count clock input to 8-bit timer/event counter 51
8-bit timer H1 output
Clock output (for trimming of high-speed system clock,
subsystem clock)
A/D converter reference voltage input and positive power
supply for port 2
A/D converter ground potential. Make the same potential as
SS or VSS.
EV
Connecting resonator for high-speed system clock
Connecting resonator for subsystem clock
Positive power supply (except for ports)
Positive power supply for ports
Ground potential (except for ports)
Ground potential for ports
Flash memory programming mode setting.
Input
P33/TO51/INTP4
Input
P16/INTP5
Input P72/INTP6
P90 to P93
− −
− −
− −
Input P122/EXCLK
Input P124/EXCLKS
− −
− −
− −
− −
− −
User’s Manual U17554EJ4V0UD
29
CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00, P01, P05, P06 (port 0)
P00, P01, P05 and P06 function as a 4-bit I/O port. These pins also function as timer I/O and serial interface chip
select input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00, P01, P05 and P06 function as 4-bit I/O port. P00, P01, P05 and P06 can be set to input or output in 1-bit
units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor
option register 0 (PU0).
(2) Control mode
P00, P01, P05 and P06 function as timer I/O, and serial interface chip select input.
(a) TI000, TI001
These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also
for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit
timer/event counters 00 and 01.
(b) TI010, TI011
These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit
timer/event counters 00 and 01.
(c) TO00, TO01
These are timer output pins.
(d) SSI11
This is the serial interface chip select input pin.
30
User’s Manual U17554EJ4V0UD
CHAPTER 2 PIN FUNCTIONS
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial
interface data I/O, clock I/O, and timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, timer I/O.
(a) SI10
This is a serial interface serial data input pin.
(b) SO10
This is a serial interface serial data output pin.
(c) SCK10
This is a serial interface serial clock I/O pin.
(d) RxD60, RxD61
These are the serial data input pins of the asynchronous serial interface.
(e) TxD60, TxD61
These are the serial data output pins of the asynchronous serial interface.
(f) TI50
This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
(g) TO50, TOH0, and TOH1
These are timer output pins.
(h) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
User’s Manual U17554EJ4V0UD
31
CHAPTER 2 PIN FUNCTIONS
2.2.3 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and
timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as external interrupt request input pins and timer I/O pins.
(a) INTP1 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI002
This is the pin for inputting an external count clock to 16-bit timer/event counter 02 and is also for inputting a
capture trigger signal to the capture registers (CR002, CR012) of 16-bit timer/event counter 02.
(c) TI012
This is the pin for inputting a capture trigger signal to the capture register (CR002) of 16-bit timer/event
counter 02.
(d) TO02
This is a timer output pin.
(e) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(f) TO51
This is a timer output pin.
Cautions 1. Be sure to pull the P31/TI002/INTP2 pin down before a reset release, to prevent malfunction.
2. Connect P31/TI002/INTP2 as follows when writing the flash memory with a flash programmer.
- P31/TI002/INTP2: Connect to EV
SS via a resistor (10 kΩ: recommended).
The above connection is not necessary when writing the flash memory by means of self
programming.
Remark P31/TI002/INTP2 and P32/TI012/TO02/INTP3 can be used as on-chip debug mode setting pins when
the on-chip debug function is used. For details, refer to CHAPTER 25 ON-CHIP DEBUG FUNCTION.
2.2.4 P40 to P43 (port 4)
P40 to P43 function as a 4-bit I/O port. P40 to P43 can be set to input or output in 1-bit units using port mode
register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
32
User’s Manual U17554EJ4V0UD
CHAPTER 2 PIN FUNCTIONS
2.2.5 P50 to P53 (port 5)
P50 to P53 function as a 4-bit I/O port. P50 to P53 can be set to input or output in 1-bit units using port mode
register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5).
2.2.6 P60 to P63 (port 6)
P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
P60 to P63 are N-ch open-drain pins.
2.2.7 P70 to P76 (port 7)
P70 to P76 function as a 7-bit I/O port. These pins also function as external interrupt request input, clock output
pins, buzzer output pins, CAN I/F I/O, serial interface data I/O and clock I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P76 function as a 7-bit I/O port. P70 to P76 can be set to input or output in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
(2) Control mode
P70 to P77 function as external interrupt request input, output pins, buzzer output pins, CAN I/F I/O, serial
interface data I/O and clock I/O.
(a) INTP6, INTP7
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) CRxD
This is the CAN serial receive data input pin.
(c) CTxD
This is the CAN serial transmit data output pin.
(d) PCL
This is a clock output pin.
(e) BUZ
This is a buzzer output pin.
(f) SI11
This is a serial interface serial data input pin.
(g) SO11
This is a serial interface serial data output pin.
(h) SCK11
This is the serial interface serial clock I/O pin.
User’s Manual U17554EJ4V0UD
33
CHAPTER 2 PIN FUNCTIONS
2.2.8 P80 to P87 (port 8)
P80 to P87 function as an 8-bit I/O port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P80 to P87 function as an 8-bit I/O port. P80 to P87 can be set to input or output in 1-bit units using port mode
register 8 (PM8).
(2) Control mode
P80 to P87 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input
pins, see (5) P80/ANI0 to P87/ANI7, P90/ANI8 to P93/ANI11 in 13.6 Cautions for A/D Converter.
Caution P80/ANI0 to P87/ANI7 is set in the analog input mode after release of reset.
2.2.9 P90 to P93 (port 9)
P90 to P93 function as an 4-bit I/O port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P90 to P93 function as an 4-bit I/O port. P90 to P93 can be set to input or output in 1-bit units using port mode
register 9 (PM9).
(2) Control mode
P90 to P93 function as A/D converter analog input pins (ANI8 to ANI11). When using these pins as analog input
pins, see (5) P80/ANI0 to P87/ANI7, P90/ANI8 to P93/ANI11 in 13.6 Cautions for A/D Converter.
Caution P90/ANI8 to P93/ANI11 is set in the analog input mode after release of reset.
2.2.10 P120 to P124 (port 12)
P120 to P124 function as a 5-bit I/O port. These pins also function as pins for external interrupt request input,
external clock input for main system clock, external clock input for subsystem clock and potential input for external
low-voltage detection. The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 to P124 function as a 5-bit I/O port. P120 to P124 can be set to input or output using port mode register 12
(PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12
(PU12).
(2) Control mode
P120 to P124 function as pins for external interrupt request input, potential input for external low-voltage
detection, resonator connection for main system clock, resonator connection for subsystem clock, external clock
input for main system clock and external clock input for subsystem clock.
(a) INTP0
This functions as an external interrupt request input for which the valid edge (rising edge, falling edge, or
both rising and falling edges) can be specified.
34
User’s Manual U17554EJ4V0UD
CHAPTER 2 PIN FUNCTIONS
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are the pins for connecting a resonator for high-speed system clock.
When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin.
Caution Connect P121/X1 as follows when writing the flash memory with a flash programmer.
- P121/X1: When using this pin as a port, connect it to V
SS via a resistor (10 kΩ:
recommended) (in the input mode) or leave it open (in the output mode).
The above connection is not necessary when writing the flash memory by means of self
programming.
Remark The X1 and X2 pins can be used as on-chip debug mode setting pins when the on-chip debug
function is used. For details, refer to CHAPTER 25 ON-CHIP DEBUG FUNCTION.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin.
(f) EXCLKS
This is an external clock input pin for subsystem clock.
2.2.11 P130 to P132 (port 13)
P130 functions as a 1-bit output-only port. P131 and P132 function as a 2-bit I/O port. These pins also function as
pins for timer I/O. The following operation modes can be specified in 1-bit units.
(1) Port mode
P131 and P132 can be set to input or output in 1 bit units using port mode register 13 (PM13). P131 and P132 use
of an on-chip pull-up resistor can be specified by pull-up resistor option register 13 (PU13).
(2) Control mode
P130, P131 and P132 function as timer I/O and serial interface chip select input.
(a) TI003
This is the pin for inputting an external count clock to 16-bit timer/event counter 03 and is also for inputting a
capture trigger signal to the capture registers (CR003, CR013) of 16-bit timer/event counter 03.
(b) TI013
This is the pin for inputting a capture trigger signal to the capture register (CR003) of 16-bit timer/event
counter 03.
(c) TO03
This is a timer output pin.
User’s Manual U17554EJ4V0UD
35
CHAPTER 2 PIN FUNCTIONS
2.2.12 AVREF
This is the A/D converter reference voltage input pin.
When the A/D converter is not used, connect this pin directly to EV
DD or VDD
Note
.
Note Connect port 8 and port 9 directly to EVDD when it is used as a digital port.
2.2.13 AVSS
This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with
the same potential as the EV
SS pin or VSS pin.
2.2.14 RESET
This is the active-low system reset input pin.
2.2.15 REGC
This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this
pin to V
SS via a capacitor (0.47 to 1 µF: recommended).
REGC
SS
V
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
2.2.16 V
DD and EVDD
DD is the positive power supply pin for other than ports.
V
EVDD is the positive power supply pin for ports.
2.2.17 V
SS and EVSS
SS is the ground potential pin for other than ports.
V
SS is the ground potential pin for ports.
EV
2.2.18 FLMD0
This is a pin for setting flash memory programming mode.
Connect to EV
SS or VSS in the normal operation mode. In flash memory programming mode, be sure to connect
this pin to the flash programmer.
36
User’s Manual U17554EJ4V0UD
CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-4 shows the types of pin I/O circuits and the recommended connections of unused pins.
Refer to Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-4. Pin I/O Circuit Types (1/2)
Pin Name I/O Circuit
I/O Recommended Connection of Unused Pins
Type
P00/TI000
P01/TI010/TO00
P05/SSI11/TI001
5-AH
I/O
Input: Independently connect to EV
EV
Output: Leave open.
P06/TI011/TO01
P10/SCK10/TxD61
P11/SI10/RxD61
P12/SO10
5-H
P13/TxD60
P14/RxD60 5-AH
P15/TOH0 5-H
P16/TOH1/INTP5
5-AH
P17/TI50/TO50
P30/INTP1
P31/TI002/INTP2
Note
P32/TI012/TO02/INTP3
P33/TI51/TO51/INTP4
P40 to P43
5-H
P50 to P53
P60 to P63 13-P
Input: Connect to EVSS.
Output: Leave this pin open at low-level
output after clearing the output latch of the
port to 0.
DD or
SS via a resistor.
P70/CTxD 5-H
P71/CRxD
5-AH
P72/PCL/INTP6
Input: Independently connect to EV
EV
SS via a resistor.
Output: Leave open.
DD or
P73/BUZ/INTP7
P74/SO11 5-H
P75/SI11
5-AH
P76/SCK11
Note Connect P31/TI002/INTP2 as follows when writing the flash memory with a flash
programmer.
- P31/TI002/INTP2: Connect to EV
SS via a resistor (10 kΩ: recommended).
The above connection is not necessary when writing the flash memory by means of self
programming.
User’s Manual U17554EJ4V0UD
37
CHAPTER 2 PIN FUNCTIONS
Table 2-4. Pin I/O Circuit Types (2/2)
Pin Name I/O Circuit
I/O Recommended Connection of Unused Pins
Type
P80/ANI0 to P87/ANI7
P90/ANI8 to P93/ANI11
Note 1
Note 1
11-G I/O
<Analog setting>
Connect to AV
REF or AVSS.
<Digital setting>
Input: Independently connect to EV
SS via a resistor.
EV
DD or
Output: Leave open.
P120/INTP0/EXLVI 5-AH I/O Input: Independently connect to EVDD or
EV
SS via a resistor.
Output: Leave open.
P121/X1
P122/X2/EXCLK
P123/XT1
Note 2, 3
Note 2
Note 2
P124/XT2/EXCLKS
Note 2
37 I/O Input: Independently connect to EV
EV
SS via a resistor.
Output: Leave open.
DD or
P130 3-C Output Leave open.
P131/TI003
5-AH I/O Input: Independently connect to EV
EV
SS via a resistor.
DD or
Output: Leave open.
P132/TI013/TO03
RESET 2 Input Connect to EVDD or VDD.
AVREF Connect directly to EVDD or VDD
− −
Note 4
.
AVSS Connect directly to EVSS or VSS.
FLMD0
Connect to EVSS or VSS.
Notes 1. P80/ANI0 to P87/ANI7 and P90/ANI8 to P93/ANI11 are set in the analog input mode
after release of reset.
2. Use the recommended connection above in I/O port mode (see Figure 6-6 Format
of Clock Operation Mode Select Register (OSCCTL)) when these pins are not
used.
3. Connect P121/X1 as follows when writing the flash memory with a flash programmer.
- P121/X1: When using this pin as a port, connect it to V
SS via a resistor (10 kΩ:
recommended) (in the input mode) or leave it open (in the output mode).
The above connection is not necessary when writing the flash memory by means of
self programming.
4. Connect port 8 and port 9 directly to EV
DD when it is used as a digital port.
38
User’s Manual U17554EJ4V0UD
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (1/2)
Type 2
Type 5-H
EV
DD
IN
Schmitt-triggered input with hysteresis characteristics
Type 3-C
EV
DD
P-ch
Data
OUT
N-ch
Vss0
Pullup
enable
Output
data
Output
disable
Input
enable
Type 11-G
Data
Output
disable
Comparator
(threshold voltage)
+
_
AV
REF
AV
P-ch
DD
EV
P-ch
IN/OUT
N-ch
EVss
REF
AV
P-ch
IN/OUT
N-ch
AV
SS
P-ch
N-ch
SS
Type 5-AH
Pull-up
enable
Data
Output
disable
Input
enable
EV
EV
DD
P-ch
N
SS
-ch
EV
DD
P-ch
IN/OUT
Input enable
Type 13-P
Data
Output disable
input enable
IN/OUT
N-ch
EVss
User’s Manual U17554EJ4V0UD
39
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (2/2)
EV
DD
Data
Output
disable
Input
enable
P-ch
N
-ch
X1,
XT1
40
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the 78K0/FE2 can each access a 64 KB memory space. Figures 3-1 to 3-4 show the memory map.
Caution Regardless of the internal memory capacity, the initial values of the internal memory size
switching register (IMS) and internal expansion RAM size switching register (IXS) of the
78K0/FE2 is fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each
product as indicated below.
Table 3-1. Set Values of Internal Memory Size Switching Register (IMS)
and Internal Expansion RAM Size Switching Register (IXS)
Flash Memory Version IMS IXS
μ
PD78F0887
μ
PD78F0888 CFH 08H
μ
PD78F0889
μ
PD78F0890
Note The μPD78F0889 and μPD78F0890 have internal ROMs of 96 KB and 128
CCH 08H
Note
CCH
04H
Note
CCH
00H
KB, respectively. However, the set value of IMS of these devices is the same
as those of the 48 KB product because banks are used. For how to set the
banks, see 4.3 Memory Bank Select Register (BANK).
User’s Manual U17554EJ4V0UD
41
CHAPTER 3 CPU ARCHITECTURE
Figure 3-1. Memory Map (μPD78F0887)
Data memory
space
RAM space in
which instruction
can be fetched
Program
memory space
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
FA00H
F9FFH
F800H
F7FFH
F000H
EFFFH
C000H
BFFFH
0190H
018FH
0083H
0082H
0000H
Special function registers
(SFR)
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Note 1
AFCAN area
(256 × 8 bits)
Reserved
Internal expansion RAM
2048 × 8 bits
Reserved
Flash memory
49152 × 8 bits
Note 2
FF20H
FF1FH
FE20H
FE1FH
FE10H
FE0FH
Short direct
addressing
BFFFH
1085H
1084H
1080H
107FH
1000H
0FFFH
0800H
07FFH
0085H
0084H
0080H
007FH
0040H
003FH
0000H
Program area
Option byte area
5 × 8 bits
Program area
CALLF entry area
2048 × 8 bits
Program area
1915 × 8 bits
Option byte area
5 × 8 bits
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
Note 3
Note 3
1FFFH
Boot cluster 1
Boot cluster 0
Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled since it is used as the communication command
area (269 bytes).
3. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.8 Security
Setting).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
BFFFH
EC00H
EBFFH
Block 2FH
Note 4
42
07FFH
0400H
03FFH
0000H
Block 01H
Block 00H
User’s Manual U17554EJ4V0UD
1 KB
CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (μPD78F0888)
Data memory
space
RAM space in
which instruction
can be fetched
Program
memory space
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
FA00H
F9FFH
F800H
F7FFH
F000H
EFFFH
0190H
018FH
0083H
0082H
0000H
Special function registers
(SFR)
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Note 1
AFCAN area
(256 × 8 bits)
Reserved
Internal expansion RAM
2048 × 8 bits
Flash memory
61440 × 8 bits
Note 2
FF20H
FF1FH
FE20H
FE1FH
FE10H
FE0FH
Short direct
addressing
EFFFH
1085H
1084H
1080H
107FH
1000H
0FFFH
0800H
07FFH
0085H
0084H
0080H
007FH
0040H
003FH
0000H
Program area
Option byte area
5 × 8 bits
Program area
CALLF entry area
2048 × 8 bits
Program area
1915 × 8 bits
Option byte area
5 × 8 bits
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
Note 3
Note 3
1FFFH
Boot cluster 1
Boot cluster 0
Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled since it is used as the communication command
area (269 bytes).
3. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.8 Security
Setting).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
EFFFH
EC00H
EBFFH
Block 3BH
Note 4
07FFH
0400H
03FFH
0000H
Block 01H
Block 00H
User’s Manual U17554EJ4V0UD
1 KB
43
CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (μPD78F0889)
Data memory
space
RAM space in
which instruction
can be fetched
Program
memory space
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
FA00H
F9FFH
F800H
F7FFH
E800H
E7FFH
C000H
BFFFH
8000H
7FFFH
0190H
018FH
0083H
0082H
0000H
Special function
registers (SFR)
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Note 1
AFCAN area
256 × 8 bits
Reserved
Internal expansion RAM
4096 × 8 bits
Reserved
Flash memory
16384 × 8 bits
(bank 0)
Flash memory
32768 × 8 bits
(common)
Note 2
FF20H
FF1FH
Short direct
addressing
FE20H
FE1FH
FE10H
FE0FH
16384 × 8 bits
(bank 2)
16384 × 8 bits
(bank 3)
16384 × 8 bits
(bank 1)
7FFFH
1085H
1084H
1080H
107FH
1000H
0FFFH
0800H
07FFH
0085H
0084H
0080H
007FH
0040H
003FH
0000H
Program area
Option byte area
5 × 8 bits
Program area
CALLF entry area
2048 × 8 bits
Program area
1915 × 8 bits
Option byte area
5 × 8 bits
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
Note 3
Note 3
1FFFH
Boot cluster 1
Boot cluster 0
Note 4
Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled since it is used as the communication command
area (269 bytes).
3. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.8 Security
Setting).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
44
(Memory bank 0)
Block 2FH
Block 20H
Block 1FH
Block 01H
Block 00H
Bank
area
Common
area
BBFFH
7C00H
7BFFH
1 KB
BFFFH
BC00H
84FFH
83FFH
8000H
7FFFH
07FFH
0400H
03FFH
0000H
(Memory bank 1)
Block 3FH
Block 30H
(Memory bank 2)
Block 4FH
Block 40H
User’s Manual U17554EJ4V0UD
(Memory bank 3)
Block 5FH
Block 50H
CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Memory Map (μPD78F0890)
Data memory
space
RAM space in
which instruction
can be fetched
Program
memory space
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
FA00H
F9FFH
F800H
F7FFH
E000H
DFFFH
C000H
BFFFH
8000H
7FFFH
0190H
018FH
0083H
0082H
0000H
Special function
registers (SFR)
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Note 1
AFCAN area
256 × 8 bits
Reserved
Internal expansion RAM
6144 × 8 bits
Reserved
Flash memory
16384 × 8 bits
(bank 0)
Flash memory
32768 × 8 bits
(common)
Note 2
FF20H
FF1FH
Short direct
addressing
FE20H
FE1FH
FE10H
FE0FH
16384 × 8 bits
(bank 4)
16384 × 8 bits
(bank 2)
16384 × 8 bits
(bank 5)
16384 × 8 bits
(bank 3)
16384 × 8 bits
(bank 1)
7FFFH
1085H
1084H
1080H
107FH
1000H
0FFFH
0800H
07FFH
0085H
0084H
0080H
007FH
0040H
003FH
0000H
Program area
Option byte area
5 × 8 bits
Program area
CALLF entry area
2048 × 8 bits
Program area
1915 × 8 bits
Option byte area
5 × 8 bits
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
Note 3
Note 3
1FFFH
Boot cluster 1
Boot cluster 0
Note 4
Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled since it is used as the communication command
area (269 bytes).
3. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.8 Security
Setting).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
BFFFH
BC00H
Bank
area
Common
area
BBFFH
84FFH
83FFH
7FFFH
7C00H
7BFFH
07FFH
03FFH
1 KB
8000H
0400H
0000H
(Memory bank 0)
Block 2FH
Block 20H
Block 1FH
Block 01H
Block 00H
(Memory bank 1)
Block 3FH
Block 30H
(Memory bank 2)
Block 4FH
. . .
Block 40H
User’s Manual U17554EJ4V0UD
(Memory bank 5)
Block 7FH
Block 70H
45
CHAPTER 3 CPU ARCHITECTURE
Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2)
(1)
μ
PD78F0887, 78F0888
Address Value
0000H to 03FFH 00H 4000H to 43FFH 10H 8000H to 83FFH 20H C000H to C3FFH 30H
0400H to 07FFH 01H 4400H to 47FFH 11H 8400H to 87FFH 21H C400H to C7FFH 31H
0800H to 0BFFH 02H 4800H to 4BFFH 12H 8800H to 8BFFH 22H C800H to CBFFH 32H
0C00H to 0FFFH 03H 4C00H to 4FFFH 13H 8C00H to 8FFFH 23H CC00H to CFFFH 33H
1000H to 13FFH 04H 5000H to 53FFH 14H 9000H to 93FFH 24H D000H to D3FFH 34H
1400H to 17FFH 05H 5400H to 57FFH 15H 9400H to 97FFH 25H D400H to D7FFH 35H
1800H to 1BFFH 06H 5800H to 5BFFH 16H 9800H to 9BFFH 26H D800H to DBFFH 36H
1C00H to 1FFFH 07H 5C00H to 5FFFH 17H 9C00H to 9FFFH 27H DC00H to DFFFH 37H
2000H to 23FFH 08H 6000H to 63FFH 18H A000H to A3FFH 28H E000H to E3FFH 38H
2400H to 27FFH 09H 6400H to 67FFH 19H A400H to A7FFH 29H E400H to E7FFH 39H
2800H to 2BFFH 0AH 6800H to 6BFFH 1AH A800H to ABFFH 2AH E800H to EBFFH 3AH
2C00H to 2FFFH 0BH 6C00H to 6FFFH 1BH AC00H to AFFFH 2BH EC00H to EFFFH 3BH
3000H to 33FFH 0CH 7000H to 73FFH 1CH B000H to B3FFH 2CH
3400H to 37FFH 0DH 7400H to 77FFH 1DH B400H to B7FFH 2DH
3800H to 3BFFH 0EH 7800H to 7BFFH 1EH B800H to BBFFH 2EH
3C00H to 3FFFH 0FH 7C00H to 7FFFH 1FH BC00H to BFFFH 2FH
Block
Number
Address Value
Block
Number
Address Value
Block
Number
Address Value
Remark μPD78F0887: Block numbers 00H to 2FH
μ
PD78F0888: Block numbers 00H to 3BH
Block
Number
46
User’s Manual U17554EJ4V0UD
Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2)
(2)
μ
PD78F0889, 78F0890
CHAPTER 3 CPU ARCHITECTURE
Address Value Block
Number
0000H to 03FFH 00H 8000H to 83FFH 20H 8000H to 83FFH 40H 8000H to 83FFH 60H
0400H to 07FFH 01H 8400H to 87FFH 21H 8400H to 87FFH 41H 8400H to 87FFH 61H
0800H to 0BFFH 02H 8800H to 8BFFH 22H 8800H to 8BFFH 42H 8800H to 8BFFH 62H
0C00H to 0FFFH 03H 8C00H to 8FFFH 23H 8C00H to 8FFFH 43H 8C00H to 8FFFH 63H
1000H to 13FFH 04H 9000H to 93FFH 24H 9000H to 93FFH 44H 9000H to 93FFH 64H
1400H to 17FFH 05H 9400H to 97FFH 25H 9400H to 97FFH 45H 9400H to 97FFH 65H
1800H to 1BFFH 06H 9800H to 9BFFH 26H 9800H to 9BFFH 46H 9800H to 9BFFH 66H
1C00H to 1FFFH 07H 9C00H to 9FFFH 27H 9C00H to 9FFFH 47H 9C00H to 9FFFH 67H
2000H to 23FFH 08H A000H to A3FFH 28H A000H to A3FFH 48H A000H to A3FFH 68H
2400H to 27FFH 09H A400H to A7FFH 29H A400H to A7FFH 49H A400H to A7FFH 69H
2800H to 2BFFH 0AH A800H to ABFFH 2AH A800H to ABFFH 4AH A800H to ABFFH 6AH
2C00H to 2FFFH 0BH AC00H to AFFFH 2BH AC00H to AFFFH 4BH AC00H to AFFFH 6BH
3000H to 33FFH 0CH B000H to B3FFH 2CH B000H to B3FFH 4CH B000H to B3FFH 6CH
3400H to 37FFH 0DH B400H to B7FFH 2DH B400H to B7FFH 4DH B400H to B7FFH 6DH
3800H to 3BFFH 0EH B800H to BBFFH 2EH B800H to BBFFH 4EH B800H to BBFFH 6EH
3C00H to 3FFFH 0FH BC00H to BFFFH
4000H to 43FFH 10H 8000H to 83FFH 30H 8000H to 83FFH 50H 8000H to 83FFH 70H
4400H to 47FFH 11H 8400H to 87FFH 31H 8400H to 87FFH 51H 8400H to 87FFH 71H
4800H to 4BFFH 12H 8800H to 8BFFH 32H 8800H to 8BFFH 52H 8800H to 8BFFH 72H
4C00H to 4FFFH 13H 8C00H to 8FFFH 33H 8C00H to 8FFFH 53H 8C00H to 8FFFH 73H
5000H to 53FFH 14H 9000H to 93FFH 34H 9000H to 93FFH 54H 9000H to 93FFH 74H
5400H to 57FFH 15H 9400H to 97FFH 35H 9400H to 97FFH 55H 9400H to 97FFH 75H
5800H to 5BFFH 16H 9800H to 9BFFH 36H 9800H to 9BFFH 56H 9800H to 9BFFH 76H
5C00H to 5FFFH 17H 9C00H to 9FFFH 37H 9C00H to 9FFFH 57H 9C00H to 9FFFH 77H
6000H to 63FFH 18H A000H to A3FFH 38H A000H to A3FFH 58H A000H to A3FFH 78H
6400H to 67FFH 19H A400H to A7FFH 39H A400H to A7FFH 59H A400H to A7FFH 79H
6800H to 6BFFH 1AH A800H to ABFFH 3AH A800H to ABFFH 5AH A800H to ABFFH 7AH
6C00H to 6FFFH 1BH AC00H to AFFFH 3BH AC00H to AFFFH 5BH AC00H to AFFFH 7BH
7000H to 73FFH 1CH B000H to B3FFH 3CH B000H to B3FFH 5CH B000H to B3FFH 7CH
7400H to 77FFH 1DH B400H to B7FFH 3DH B400H to B7FFH 5DH B400H to B7FFH 7DH
7800H to 7BFFH 1EH B800H to BBFFH 3EH B800H to BBFFH 5EH B800H to BBFFH 7EH
7C00H to 7FFFH 1FH BC00H to BFFFH
Address Value
Block
Number
Memory Bank
0
2FH BC00H to BFFFH
1
3FH BC00H to BFFFH
Address Value
Block
Number
Memory Bank
2
4FH BC00H to BFFFH
3
5FH BC00H to BFFFH
Address Value
Block
Number
Memory Bank
4
6FH
5
7FH
Remark μPD78F0889: Block numbers 00H to 5FH
μ
PD78F0890: Block numbers 00H to 7FH
User’s Manual U17554EJ4V0UD
47
CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
78K0/FE2 products incorporate internal ROM (flash memory), as shown below.
Table 3-3. Internal ROM Capacity
Internal ROM Part Number
Structure Capacity
μ
PD78F0887
μ
PD78F0888 61440 × 8 bits (0000H to EFFFH)
μ
PD78F0889
μ
PD78F0890
Flash memory
49152 × 8 bits (0000H to BFFFH)
98304 × 8 bits
(0000H to 7FFFH (common area: 32 KB) + 8000H to BFFFH (bank area: 16 KB) × 4)
131072 × 8 bits
(0000H to 7FFFH (common area: 32 KB) + 8000H to BFFFH (bank area: 16 KB) × 6)
The internal program memory space is divided into the following areas.
(1) Vector code area
The 64-byte area 0000H to 003FH is reserved as a Vector code area. The program start addresses for branch
upon reset signal input or generation of each interrupt request are stored in the Vector code area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
Table 3-4. Vector Code
Vector Code Address Interrupt Source Vector Code Address Interrupt Source
RESET input, POC, LVI,
WDT
0004H INTLVI 0024H INTP7/INTST61
0006H INTP0 0026H INTTMH1
0008H INTP1 0028H INTTMH0
000AH INTP2/INTTM002 002AH INTTM50
000CH INTP3/INTTM012 002CH INTTM000
000EH INTP4/INTTM003 002EH INTTM010
0010H INTP5/INTTM013 0030H INTAD
0012H INTC0ERR 0032H INTWTI/INTDMU
0014H INTC0WUP 0034H INTTM51
0016H INTC0REC 0036H INTWT
0018H INTC0TRX 0038H INTCSI11
001AH INTSRE60 003AH INTTM001
001CH INTSR60 003CH INTTM011
001EH INTST60 003EH BRK
0020H INTCSI10/INTSRE61 0000H
0022H INTP6/INTSR61
48
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) Option byte area
The option byte area is assigned to the 1-byte area of 0080H. Refer to CHAPTER 23 OPTION BYTE for details.
(4) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
(5) On-chip debug security ID setting area
A 10-byte area of 0085H to 008EH and 1085H to 108EH can be used as an on-chip debug security ID setting
area. Set the on-chip debug security ID of 10 bytes at 0085H to 008EH when the boot swap is not used and at
0085H to 008EH and 1085H to 108EH when the boot swap is used. For details, see CHAPTER 25 ON-CHIP
DEBUG FUNCTION.
μ
3.1.2 Bank area (
The
μ
PD78F0889 has bank areas 0 to 3 and the μPD78F0890 has bank areas 0 to 5 as illustrated below.
PD78F0889 and 78F0890 only)
The banks are selected by a bank select register (BANK) (see 4.3 Memory Bank Select Register (BANK)).
Cautions 1. Instructions cannot be fetched between different memory banks.
2. Branch and access cannot be directly executed between different memory banks. Execute
branch or access between different memory banks via the common area.
3. Allocate interrupt servicing in the common area.
4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0.
Figure 3-5. Internal ROM (Flash Memory) Configuration
(a)
μ
PD78F0889
BFFFH
Bank area 3
16384 × 8 bits
8000H
7FFFH
0000H
Bank area 0
16384 × 8 bits
Bank area 1
16384 × 8 bits
Bank area 2
16384 × 8 bits
Common area
32768 × 8 bits
User’s Manual U17554EJ4V0UD
49
(b) μPD78F0890
BFFFH
8000H
7FFFH
Bank
area 0
16384 ×
8 bits
CHAPTER 3 CPU ARCHITECTURE
Bank
area 1
16384 ×
8 bits
Bank
area 2
16384 ×
8 bits
Common area
32768 × 8 bits
Bank
area 3
16384 ×
8 bits
Bank
area 4
16384 ×
8 bits
Bank
area 5
16384 ×
8 bits
0000H
The following table shows the relations among bank numbers, CPU addresses, and real addresses of the flash
memory.
Table 3-5. Bank Numbers, CPU Addresses, and Real Addresses of Flash Memory
(a)
μ
PD78F0889
Bank No. CPU Address Real Address of Flash Memory
−
0 08000H to 0BFFFH
1 0C000H to 0FFFFH
2 10000H to 13FFFH
3
4 or more Setting prohibited
0000H to 7FFFH (common area) 00000H to 07FFFH
8000H to BFFFH
14000H to 17FFFH
(b)
μ
PD78F0890
Bank No. CPU Address Real Address of Flash Memory
−
0 08000H to 0BFFFH
1 0C000H to 0FFFFH
2 10000H to 13FFFH
3 14000H to 17FFFH
4 18000H to 1BFFFH
5
6 or more Setting prohibited
0000H to 7FFFH (common area) 00000H to 07FFFH
8000H to BFFFH
1C000H to 1FFFFH
50
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
3.1.3 Internal data memory space
78K0/FE2 products incorporate the following RAM.
(1) Internal high-speed RAM
Table 3-6. Internal High-Speed RAM Capacity
Part Number Internal High-Speed RAM
μ
PD78F0887
μ
PD78F0888
μ
PD78F0889
μ
PD78F0890
1024 × 8 bits (FB00H to FEFFH)
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per one bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
(2) Internal expansion RAM
Table 3-7. Internal Expansion RAM Capacity
Part Number Internal Expansion RAM
μ
PD78F0887 2048 × 8 bits (F000H to F7FFH)
μ
PD78F0888
μ
PD78F0889
μ
PD78F0890
4096 × 8 bits (E800H to F7FFH)
6144 × 8 bits (E000H to F7FFH)
The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as
well as a program area in which instructions can be written and executed.
The internal expansion RAM cannot be used as a stack memory.
3.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to
Table 3-8 Special Function Register List in 3.2.3 Special Function Registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0/FE2, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figure 3-6 to 3-9 show correspondence between data memory and addressing. For details of each
addressing mode, refer to 3.4 Operand Address Addressing.
User’s Manual U17554EJ4V0UD
51
FFFFH
CHAPTER 3 CPU ARCHITECTURE
Figure 3-6. Correspondence Between Data Memory and Addressing (μPD78F0887)
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
FA00H
F9FFH
F800H
F7FFH
Special function registers (SFR)
256 × 8 bits
General-purpose registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Note 1
AFCAN area
(256 × 8 bits)
Reserved
Internal expansion RAM
2048 × 8 bits
SFR addressing
FF20H
FF1FH
Register addressing
FE20H
FE1FH
FE10H
FE0FH
Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
F000H
EFFFH
Reserved
C000H
BFFFH
Flash memory
49152 × 8 bits
0190H
018FH
0083H
0082H
0000H
Note 2
Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled since it is used as the communication command
area (269 bytes).
52
User’s Manual U17554EJ4V0UD
FFFFH
CHAPTER 3 CPU ARCHITECTURE
Figure 3-7. Correspondence Between Data Memory and Addressing (μPD78F0888)
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
FA00H
F9FFH
F800H
F7FFH
Special function registers (SFR)
256 × 8 bits
General-purpose registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Note 1
AFCAN area
(256 × 8 bits)
Reserved
Internal expansion RAM
2048 × 8 bits
SFR addressing
FF20H
FF1FH
Register addressing
FE20H
FE1FH
FE10H
FE0FH
Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
F000H
EFFFH
Flash memory
61440 × 8 bits
0190H
018FH
0083H
0082H
0000H
Note 2
Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled since it is used as the communication command
area (269 bytes).
User’s Manual U17554EJ4V0UD
53
FFFFH
CHAPTER 3 CPU ARCHITECTURE
Figure 3-8. Correspondence Between Data Memory and Addressing (μPD78F0889)
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
FA00H
F9FFH
F800H
F7FFH
Special function registers (SFR)
256 × 8 bits
General-purpose registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Note 1
AFCAN area
(256 × 8 bits)
Reserved
Internal expansion RAM
4096 × 8 bits
SFR addressing
FF20H
FF1FH
Register addressing
FE20H
FE1FH
FE10H
FE0FH
16384 × 8 bits
(bank 2)
Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
E800H
E7FFH
Reserved
C000H
BFFFH
Flash memory
16384 × 8 bits
(bank 0)
8000H
7FFFH
0190H
018FH
0083H
0082H
0000H
Flash memory
32768 × 8 bits
(common)
Note 2
16384 × 8 bits
(bank 3)
16384 × 8 bits
(bank 1)
Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled since it is used as the communication command
area (269 bytes).
54
User’s Manual U17554EJ4V0UD
FFFFH
CHAPTER 3 CPU ARCHITECTURE
Figure 3-9. Correspondence Between Data Memory and Addressing (μPD78F0890)
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
FA00H
F9FFH
F800H
F7FFH
Special function registers (SFR)
256 × 8 bits
General-purpose registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Note 1
AFCAN area
(256 × 8 bits)
Reserved
Internal expansion RAM
6144 × 8 bits
SFR addressing
FF20H
FF1FH
Register addressing
FE20H
FE1FH
FE10H
FE0FH
16384 × 8 bits
(bank 4)
16384 × 8 bits
(bank 2)
Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
E000H
DFFFH
Reserved
C000H
BFFFH
Flash memory
16384 × 8 bits
(bank 0)
8000H
7FFFH
0190H
018FH
0083H
0082H
0000H
Flash memory
32768 × 8 bits
(common)
Note 2
16384 × 8 bits
16384 × 8 bits
(bank 3)
16384 × 8 bits
(bank 1)
(bank 5)
Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled since it is used as the communication command
area (269 bytes).
User’s Manual U17554EJ4V0UD
55
CHAPTER 3 CPU ARCHITECTURE
3.2 Processor Registers
78K0/FE2 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset Vector code values at addresses 0000H and 0001H to the program
counter.
Figure 3-10. Format of Program Counter
15 0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
Reset signal generation sets the PSW to 02H.
Figure 3-11. Format of Program Status Word
7 0
PSW IE Z RBS1 AC RBS0 0 ISP CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
Other interrupt requests are all disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgement and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
56
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-
level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H)
(refer to 17.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be
acknowledged. Actual request acknowledgement is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 3-12 Format of Stack Pointer
15 0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-13 and 3-14.
Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
User’s Manual U17554EJ4V0UD
57
CHAPTER 3 CPU ARCHITECTURE
Figure 3-13. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
Register pair higher
Register pair lower
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
PC15 to PC8
PC7 to PC0
(c) Interrupt, BRK instructions (when SP = FEE0H)
SP
FEE0H
FEE0H
SP
FEDDH
FEDFH
FEDEH
FEDDH
PSW
PC15 to PC8
PC7 to PC0
58
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
Figure 3-14. Data to Be Restored from Stack Memory
(a) POP rp instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
Register pair higher
Register pair lower
(b) RET instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
PC15 to PC8
PC7 to PC0
(c) RETI, RETB instructions (when SP = FEDDH)
SP
FEE0H
FEE0H
SP
FEDDH
FEDFH
FEDEH
FEDDH
PSW
PC15 to PC8
PC7 to PC0
User’s Manual U17554EJ4V0UD
59
CHAPTER 3 CPU ARCHITECTURE
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-15. Configuration of General-Purpose Registers
(a) Absolute name
16-bit processing 8-bit processing
FEFFH
FEF8H
FEF0H
FEE8H
FEE0H
BANK0
BANK1
BANK2
BANK3
RP3
RP2
RP1
RP0
15 0 7 0
R7
R6
R5
R4
R3
R2
R1
R0
(b) Function name
16-bit processing 8-bit processing
FEFFH
FEF8H
FEF0H
FEE8H
FEE0H
BANK0
BANK1
BANK2
BANK3
HL
DE
BC
AX
15 0 7 0
H
L
D
E
B
C
A
X
60
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special Function Registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH area.
Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Table 3-8 gives a list of the special function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
by the header file “sfrbit.h” in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols
can be written as an instruction operand.
• R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
User’s Manual U17554EJ4V0UD
61
CHAPTER 3 CPU ARCHITECTURE
Table 3-8. Special Function Register List (1/6)
FF00H Port register 0 P0 R/W
FF01H Port register 1 P1 R/W
FF02H 8-bit timer H compare register 00 CMP00 R/W
FF03H Port register 3 P3 R/W
FF04H Port register 4 P4 R/W
FF05H Port register 5 P5 R/W
FF06H Port register 6 P6 R/W
FF07H Port register 7 P7 R/W
FF08H Port register 8 P8 R/W
FF09H Port register 9 P9 R/W
FF0AH Receive buffer register 60 RXB60 R
FF0BH Transmit buffer register 60 TXB60 R/W
FF0CH Port register 12 P12 R/W
FF0DH Port register 13 P13 R/W
FF0EH 8-bit timer H compare register 10 CMP10 R/W
FF0FH Serial I/O shift register 10 SIO10 R
FF10H
FF11H
FF12H
FF13H
FF14H
FF15H
FF16H 8-bit timer counter 50 TM50 R
FF17H 8-bit timer compare register 50 CR50 R/W
FF18H 10-bit A/D conversion result register ADCR R
FF19H 8-bit A/D conversion result register ADCRH R
FF1AH 8-bit timer H compare register 01 CMP01 R/W
FF1BH 8-bit timer H compare register 11 CMP11 R/W
FF1FH 8-bit timer counter 51 TM51 R
FF20H Port mode register 0 PM0 R/W
FF21H Port mode register 1 PM1 R/W
FF22H A/D port configuration register ADPC R/W
FF23H Port mode register 3 PM3 R/W
FF24H Port mode register 4 PM4 R/W
FF25H Port mode register 5 PM5 R/W
FF26H Port mode register 6 PM6 R/W
FF27H Port mode register 7 PM7 R/W
FF28H Port mode register 8 PM8 R/W
FF29H Port mode register 9 PM9 R/W
16-bit timer counter 00 TM00 R
16-bit timer capture/compare register 000 CR000 R/W
16-bit timer capture/compare register 010 CR010 R/W
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
− √ −
√ √ −
√ √ −
− √ −
− √ −
− − √
− − √
− − √
− √ −
√ √ −
− − √
− √ −
− √ −
− √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
After
Reset
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
00H
00H
0000H
0000H
0000H
00H
00H
0000H
00H
00H
00H
00H
FFH
FFH
00H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
62
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
Table 3-8. Special Function Register List (2/6)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
FF2AH A/D converter mode register ADM R/W
FF2BH Analog input channel specification register ADS R/W
FF2CH Port mode register 12 PM12 R/W
FF2DH Port mode register 13 PM13 R/W
FF2EH
FF2FH
FF30H Pull-up resistor option register 0 PU0 R/W
FF31H Pull-up resistor option register 1 PU1 R/W
FF33H Pull-up resistor option register 3 PU3 R/W
FF34H Pull-up resistor option register 4 PU4 R/W
FF35H Pull-up resistor option register 5 PU5 R/W
FF37H Pull-up resistor option register 7 PU7 R/W
FF38H
FF39H Clock selection register 61 CKSR61 R/W
FF3AH Receive buffer register 61 RXB61 R/W
FF3BH Transmit buffer register 61 TXB61 R/W
FF3CH Pull-up resistor option register 12 PU12 R/W
FF3DH Pull-up resistor option register 13 PU13 R/W
FF3EH Baud rate generator control register 61 BRGC61 R/W
FF3FH Asynchronous serial interface control register 61 ASICL61 R/W
FF40H Clock output selection register CKS R/W
FF41H 8-bit timer compare register 51 CR51 R/W
FF42H Multiplier/divider control register 0 DMUC0 R/W
FF43H 8-bit timer mode control register 51 TMC51 R/W
FF44H
FF45H
FF47H Serial I/O shift register 11 SIO11 R
FF48H External interrupt rising edge enable register EGP R/W
FF49H External interrupt falling edge enable register EGN R/W
FF4AH Multiplication/Division Data Register A0L MDA0L R/W
FF4BH
FF4CH Multiplication/Division Data Register A0H MDA0H R/W
FF4DH
FF4EH Transmit buffer register 11 SOTB11 R/W
FF4FH Input switch control register ISC R/W
FF50H
Asynchronous serial interface operation mode
register 61
Asynchronous serial interface reception error
status register 61
Asynchronous serial interface transmission
status register 61
Remainder data register 0
Asynchronous serial interface operation mode
register 60
ASIM61 R/W
ASIS61 R
ASIF61 R
SDR0
SDR0L
R/W
SDR0H
ASIM60 R/W
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
− √ −
− √ −
− √ −
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ √
− √ −
√ √ −
√ √ −
− √ √
− √ √
− √ −
√ √ −
√ √ −
After
Reset
00H
00H
FFH
FEH
01H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
FFH
16H
00H
00H
00H
00H
0000H
00H
00H
00H
0000H
0000H
00H
00H
01H
User’s Manual U17554EJ4V0UD
63
CHAPTER 3 CPU ARCHITECTURE
Table 3-8. Special Function Register List (3/6)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
FF51H Prescaler mode register 03 PRM03 R/W
FF52H Capture/compare control register 03 CRC03 R/W
FF53H
FF54H 16-bit timer mode control register 02 TMC02 R/W
FF55H
FF56H Clock selection register 60 CKSR60 R/W
FF57H Baud rate generator control register 60 BRGC60 R/W
FF58H Asynchronous serial interface control register 60 ASICL60 R/W
FF59H Prescaler mode register 02 PRM02 R/W
FF5AH
FF5BH
FF5CH Capture/compare control register 02 CRC02 R/W
FF60H
FF61H
FF62H
FF63H
FF64H
FF65H
FF66H
FF67H
FF68H Module Last Out Pointer Register C0LOPT R
FF69H 8-bit timer H mode register 0 TMHMD0 R/W
FF6AH Timer clock selection register 50 TCL50 R/W
FF6BH 8-bit timer mode control register 50 TMC50 R/W
FF6CH 16 bit capture/compare register 002 CR002 R/W
FF6DH
FF6EH CAN Global Macro Clock Selection Register C0GMCS R/W
FF6FH
FF70H
FF71H
FF72H
FF73H
FF74H
FF75H
FF76H
FF77H
FF78H
FF79H
Asynchronous serial interface reception error
status register 60
Asynchronous serial interface transmission
status register 60
16-bit timer counter 02 TM02 R
Module Receive History List Get Pointer
Register
Module Transmission History List Get Pointer
Register
CAN Global Macro Clock Selection C0GMCTRL R/W
CAN Global Macro Automatic Block
Transmission Delay Register
CAN Global Macro Automatic Block
Transmission Register
CAN Module Mask 1 Register L C0MASK1L R/W
CAN Module Mask 1 Register H C0MASK1H R/W
CAN Module Mask 2 Register L C0MASK2L R/W
CAN Module Mask 2 Register H C0MASK2H R/W
CAN Module Mask 3 Register L C0MASK3L R/W
ASIS60 R
ASIF60 R
C0RGPT
C0TGPT R/W
C0GMABT R/W
C0GMABTD R/W
R/W
√ √ −
√ √ −
− √ −
√ √ −
− √ −
− √ −
− √ −
√ √ −
√ √ −
− − √
√ √ −
− − √
− − √
− − √
− − √
− √ −
√ √ −
√ √ −
√ √ −
− − √
− √ −
− √ −
− − √
− − √
− − √
− − √
− − √
After
Reset
00H
00H
00H
00H
00H
00H
FFH
16H
00H
0000H
00H
xx02H
xx02H
0000H
0000H
Undefined
00H
00H
00H
0000H
0FH
00H
Undefined
Undefined
Undefined
Undefined
Undefined
64
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
Table 3-8. Special Function Register List (4/6)
After
Reset
Undefined
FF7AH
CAN Module Mask 3 Register H C0MASK3H R/W
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
− − √
FF7BH
FF7CH
FF7DH
FF7EH
CAN Module Mask 4 Register L
CAN Module Mask 4 Register H C0MASK4H R/W
C0MASK4L R/W
−
−
− − √
√
Undefined
Undefined
FF7FH
FF80H Serial operation mode register 10 CSIM10 R/W
FF81H Serial clock selection register 10 CSIC10 R/W
FF84H Transmit buffer register 10 SOTB10 R/W
FF88H Serial operation mode register 11 CSIM11 R/W
FF89H Serial clock selection register 11 CSIC11 R/W
FF8AH CAN module time stamp register C0TS R/W
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
− − √
00H
00H
00H
00H
00H
0000H
FF8BH
FF8CH Timer clock selection register 51 TCL51 R/W
FF8FH Watch timer operation mode register WTM R/W
FF90H
CAN Module Control Register C0CTRL R/W
√ √ −
√ √ −
− − √
00H
00H
0000H
FF91H
FF92H CAN Module Last Error Code Register C0LEC R/W
FF93H CAN Module Information Register C0INFO R
FF94H
CAN Module Error Counters C0ERC R
− √ −
− √ −
− − √
00H
00H
0000H
FF95H
FF96H
CAN Module Interrupt Enable Register C0IE R/W
− − √
0000H
FF97H
FF98H
CAN Module Interrupt Pending Register C0INTS R/W
− − √
0000H
FF99H
FF9BH Watchdog timer enable register WDTE R/W
FF9CH
CAN Module Bit Rate Register C0BTR R/W
− √ −
− − √
1AH/9AH
Note1
370FH
FF9DH
FF9EH CAN Module bit rate Prescaler register C0BRP R/W
FF9FH CAN Module Last In Pointer Register C0LIPT R
FFA0H Internal oscillator mode register RCM R/W
FFA1H Main clock mode register MCM R/W
FFA2H Main OSC control register MOC R/W
FFA3H Oscillation stabilization time counter status register OSTC R
FFA4H Oscillation stabilization time select register OSTS R/W
FFA5H 16-bit timer output control register 02 TOC02 R/W
FFA6H 16-bit timer counter 03 TM03 R
− √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− − √
FFH
Undefined
Note2
00H
00H
80H
00H
05H
00H
0000H
FFA7H
Notes 1. The reset value of WDTE is determined by setting of option byte.
2. The value of this register is 00H immediately after a reset release but automatically changes to 80H after
internal high-speed oscillator has been stabilized.
User’s Manual U17554EJ4V0UD
65
CHAPTER 3 CPU ARCHITECTURE
Tables 3-8. Special Function Register List (5/6)
FFA8H
16-bit timer capture/compare register 003 CR003 R/W
FFA9H
FFAAH
16-bit timer capture/compare register 013 CR013 R/W
FFABH
FFACH Reset control flag register RESF R
FFADH 16-bit timer mode control register 03 TMC03 R/W
FFAEH MDB0L
FFAFH
FFB0H
Multiplier/divider data register B0 MDB0
R/W
MDB0H
16-bit timer counter 01 TM01 R
FFB1H
FFB2H
16-bit timer capture/compare register 001 CR001 R/W
FFB3H
FFB4H
16-bit timer capture/compare register 011 CR011 R/W
FFB5H
FFB6H 16-bit timer mode control register 01 TMC01 R/W
FFB7H Prescaler mode register 01 PRM01 R/W
FFB8H Capture/compare control register 01 CRC01 R/W
FFB9H 16-bit timer output control register 01 TOC01 R/W
FFBAH 16-bit timer mode control register 00 TMC00 R/W
FFBBH Prescaler mode register 00 PRM00 R/W
FFBCH Capture/compare control register 00 CRC00 R/W
FFBDH 16-bit timer output control register 00 TOC00 R/W
FFBEH Low-voltage detection register LVIM R/W
FFBFH Low-voltage detection level selection register LVIS R/W
FFC2H Flash status register PFS R/W
FFC4H Flash programming mode control register FLPMC R/W
FFE0H Interrupt request flag register 0L IF0L R/W
FFE1H Interrupt request flag register 0H
FFE2H Interrupt request flag register 1L IF1L R/W
FFE3H Interrupt request flag register 1H
FFE4H Interrupt mask flag register 0L MK0L R/W
FFE5H Interrupt mask flag register 0H
FFE6H Interrupt mask flag register 1L MK1L R/W
FFE7H Interrupt mask flag register 1H
FFE8H Priority specification flag register 0L PR0L R/W
FFE9H Priority specification flag register 0H
IF0
IF0H R/W
IF1
IF1H R/W
MK0
MK0H R/W
MK1
MK1H R/W
PR0
PR0H R/W
Notes 1. This value varies depending on the reset source.
2. Varies depending on the operation mode.
• User mode: 08H
• On-board mode: 0CH
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
− − √
− − √
− √ −
√ √ −
− √ √
− − √
− − √
− − √
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √
√ √
√ √
√
√
√ √
√ √
√
√ √
√ √
√
√ √
√ √ √
√ √
FFH
After
Reset
0000H
0000H
Note 1
00H
00H
0000H
0000H
0000H
0000H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
08H/0CH
00H
00H
00H
00H
FFH
FFH
FFH
DFH
FFH
Note 2
66
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
Tables 3-8. Special Function Register List (6/6)
After
Reset
FFH
FFH
0000H
00H
00H
CFH
0CH
00H
00H
01H
FFEAH Priority specification flag register 1L PR1L R/W
FFEBH Priority specification flag register 1H
FFECH 16-bit timer capture/compare register 012 R/W
FFEDH
FFEEH 8-bit timer H carrier control register 1 TMCYC1 R/W
FFEFH Clock operation mode select register OSCCTL R/W
FFF0H Internal memory size switching register
FFF4H Internal expansion RAM size switching register
FFF9H 16-bit timer output control register 03 TOC03 R/W
FFFAH 8-bit timer H mode register 1 TMHMD1 R/W
FFFBH Processor clock control register PCC R/W
Note
IMS R/W
PR1
PR1H R/W
CR012
Note
IXS R/W
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
√ √
√ √
− − √
√ √ −
√ √ −
− √ −
− √ −
√ √ −
√ √ −
√ √ −
√
Note Regardless of the internal memory capacity, the initial values of the internal memory size switching register
(IMS) and internal expansion RAM size switching register (IXS) of the 78K0/FE2 is fixed (IMS = CFH, IXS =
0CH). Therefore, set the value corresponding to each as indicated below.
Flash Memory Version IMS IXS
μ
PD78F0887 CCH 08H
μ
PD78F0888 CFH 08H
μ
PD78F0889
μ
PD78F0890
CCH 04H
CCH 00H
User’s Manual U17554EJ4V0UD
67
CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by
the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
PC
+
15 0
876
PC indicates the start address
...
of the instruction after the BR instruction.
α
15 0
PC
When S = 0, all bits of are 0.
When S = 1, all bits of are 1.
α
α
S
jdisp8
68
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
70
CALL or BR
Low Addr.
High Addr.
15 0
PC
In the case of CALLF !addr11 instruction
70
15 0
PC
00001
643
10–8
fa
CALLF
fa
7–0
11 10
87
87
User’s Manual U17554EJ4V0UD
69
CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
765 10
Operation code
ta
4–0
111
Effective address
Effective address+1
15 1
01
00000000
Memory (Table)
70
Low Addr.
High Addr.
15 0
PC
87
87
65 0
0
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
07
70
rp
15 0
PC
AX
87
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/FE2 instruction words, the following instructions employ implied addressing.
Instruction Register to Be Specified by Implied Addressing
MULU A register for multiplicand and AX register for product storage
DIVUW AX register for dividend and quotient storage
ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets
ROR4/ROL4 A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
User’s Manual U17554EJ4V0UD
71
CHAPTER 3 CPU ARCHITECTURE
3.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flags
(RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code 0 1100010
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code 1 0000100
Register specify code
72
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
3.4.3 Direct addressing
[Function]
The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code 10001110 OP code
00000000 00H
11111110 FEH
[Illustration]
07
OP code
addr16 (lower)
addr16 (upper)
Memory
User’s Manual U17554EJ4V0UD
73
CHAPTER 3 CPU ARCHITECTURE
3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers
(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. Refer to the [Illustration] shown below.
[Operand format]
Identifier Description
saddr Immediate data that indicate label or FE20H to FF1FH
saddrp Immediate data that indicate label or FE20H to FF1FH (even address only)
[Description example]
MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)
Operation code 1 1110010 OP code
0 0110000 30H (saddr-offset)
[Illustration]
07
OP code
saddr-offset
15
Effective address
1
111111
When 8-bit immediate data is 20H to FFH,
When 8-bit immediate data is 00H to 1FH,
74
87
α
α
= 0
α
= 1
User’s Manual U17554EJ4V0UD
Short direct memory
0
CHAPTER 3 CPU ARCHITECTURE
3.4.5 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special function register name
sfrp
16-bit manipulatable special function register name (even address
only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code 11110110 OP code
00100000 20H (sfr-offset)
[Illustration]
07
Effective address
OP code
sfr-offset
15
1
111111
87
1
SFR
0
User’s Manual U17554EJ4V0UD
75
CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be
carried out for all the memory spaces.
[Operand format]
Identifier Description
[DE], [HL]
−
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code 10000101
[Illustration]
16 08D7
DE
The contents of the memory
addressed are transferred.
A
7 0
E
Memory
The memory address
07
specified with the
register pair DE
76
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
3.4.7 Based addressing
[Function]
8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from
the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
[HL + byte]
−
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code 10101110
00010000
[Illustration]
16 08H7
HL
The contents of the memory
addressed are transferred.
7 0
A
L
Memory
07
+10
User’s Manual U17554EJ4V0UD
77
CHAPTER 3 CPU ARCHITECTURE
3.4.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the base register, that
is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the
sum is used to address the memory. Addition is performed by expanding the B or C register contents as a
positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the
memory spaces.
[Operand format]
Identifier Description
[HL + B], [HL + C]
−
[Description example]
In the case of MOV A, [HL + B]; (selecting B register)
Operation code 10101011
[Illustration]
16 0
78
HL
The contents of the memory
addressed are transferred.
7 0
A
H
+
L
B
Memory
07
07
78
User’s Manual U17554EJ4V0UD
CHAPTER 3 CPU ARCHITECTURE
3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return
instructions are executed or the register is saved / reset upon generation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.
[Description example]
In the case of PUSH DE; (saving DE register)
Operation code 10110101
[Illustration]
Memory 07
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
D
E
User’s Manual U17554EJ4V0UD
79
CHAPTER 4 MEMORY BANK SELECT FUNCTION
(
μ
PD78F0889, 78F0890 ONLY)
4.1 Memory Bank
The
μ
PD78F0889, 78F0890 implement a ROM capacity of 96 KB or 128 KB by selecting a memory bank from a
memory space of 8000H to BFFFH.
The
μ
PD78F0889 has memory banks 0 to 3, and the μPD78F0890 have memory banks 0 to 5, as shown below.
The memory banks are selected by using a memory bank select register (BANK).
Figure 4-1. Internal ROM (Flash Memory) Configuration
(a)
μ
PD78F0889
BFFFH
Bank
area
8000H
7FFFH
(Memory bank 3)
(Memory bank 2)
(Memory bank 1)
Flash memory
16384 × 8 bits
(memory bank 0)
Common
area
0000H
Flash memory
32768 × 8 bits
μ
PD78F0890
(b)
(Memory bank 5)
(Memory bank 4)
(Memory bank 3)
(Memory bank 2)
(Memory bank 1)
BFFFH
Bank
area
8000H
7FFFH
Common
area
0000H
Flash memory
16384 × 8 bits
(memory bank 0)
Flash memory
32768 × 8 bits
80
User’s Manual U17554EJ4V0UD
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
4.2 Difference in Representation of Memory Space
With the 78K0/FE2 products which support the memory bank, addresses can be viewed in the following two
different ways.
• Memory bank number + CPU address
• Flash memory real address (HEX FORMAT [BANK])
Figure 4-2. Address View
(a) Memory bank number + CPU address
Memory bank 5
Memory bank 4
Memory bank 3
Memory bank 2
BFFFH
Bank
area
8000H
7FFFH
Common
area
0000H
Memory bank 1
Memory bank 0
(16 KB)
Common
(32 KB)
“Memory bank number + CPU address” is represented with a vacancy in the address space, while the flash
memory real address is shown with no vacancy in the address space.
“Memory bank number + CPU address” is used for addressing in the user program. For on-board programming
and self programming not using the self programming sample library
Note that the HEX file that is output by the assembler (RA78K0) by default uses the flash memory real address.
For address representation of the other tools such as the simulator and the debugger
Notes 1. “Memory bank number + CPU address” can be used when performing self programming, using the self
programming sample library, because the addresses are automatically translated.
2. SM+ for 78K0/Fx2, ID78K0-QB
(b) Flash memory real address (HEX FORMAT [BANK])
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
00000H
Memory bank 5
(16 KB)
Memory bank 4
(16 KB)
Memory bank 3
(16 KB)
Memory bank 2
(16 KB)
Memory bank 1
(16 KB)
Memory bank 0
(16 KB)
Common
(32 KB)
Note 1
, the flash memory real address is used.
Note 2
, see Table 4-1.
User’s Manual U17554EJ4V0UD
81
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
Table 4-1. Memory Bank Address Representation
Memory Bank Number CPU Address Flash Memory Real Address Address Representation in
Simulator and Debugger
Memory bank 0 08000H-0BFFFH 08000H-0BFFFH
Memory bank 1 0C000H-0FFFFH 18000H-1BFFFH
Memory bank 2 10000H-13FFFH 28000H-2BFFFH
Memory bank 3 14000H-17FFFH 38000H-3BFFFH
Memory bank 4 18000H-1BFFFH 48000H-4BFFFH
Memory bank 5
08000H-0BFFFH
Note 2
1C000H-1FFFFH 58000H-5BFFFH
Notes 1. SM+ for 78K0/Fx2, ID78K0-QB
2. Set the memory bank to be used by the memory bank select register (BANK) (see Figure 4-3).
For details, see the RA78K0 Ver. 3.80 Assembler Package Operation User’s Manual (U17199E).
4.3 Memory Bank Select Register (BANK)
The memory bank select register (BANK) is used to select a memory bank to be used.
BANK can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears BANK to 00H.
Figure 4-3. Format of Memory Bank Select Register (BANK)
Address: FFF3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
BANK 0 0 0 0 0 BANK2 BANK1 BANK0
Note 1
Bank setting BANK2 BANK1 BANK0
μ
PD78F0889
0 0 0 Common area (32 K) + memory bank 0 (16 K)
0 0 1 Common area (32 K) + memory bank 1 (16 K)
0 1 0 Common area (32 K) + memory bank 2 (16 K)
0 1 1 Common area (32 K) + memory bank 3 (16 K)
1 0 0 Common area (32 K) +
1 0 1
Other than above Setting prohibited
Setting prohibited
μ
PD78F0890
memory bank 4 (16 K)
Common area (32 K) +
memory bank 5 (16 K)
Caution Be sure to change the value of the BANK register in the common area (0000H to 7FFFH).
If the value of the BANK register is changed in the bank area (8000H to BFFFH), an inadvertent
program loop occurs in the CPU. Therefore, never change the value of the BANK register in the
bank area.
82
User’s Manual U17554EJ4V0UD
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
4.4 Selecting Memory Bank
The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be
addressed. Therefore, to access a memory bank different from the one currently selected, that memory bank must be
selected by using the BANK register.
The value of the BANK register must not be changed in the bank area (8000H to BFFFH). Therefore, to change
the memory bank, branch an instruction to the common area (0000H to 7FFFH) and change the value of the BANK
register in that area.
Cautions 1. Instructions cannot be fetched between different memory banks.
2. Branching and accessing cannot be directly executed between different memory banks.
Execute branching or accessing between different memory banks via the common area.
3. Allocate interrupt servicing in the common area.
4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0.
4.4.1 Referencing values between memory banks
Values cannot be directly referenced from one memory bank to another.
To access another memory bank from one memory bank, branch once to the common area (0000H to 7FFFH),
change the setting of the BANK register there, and then reference a value.
Bank
area
Common
area
Bank
area
Common
area
Memory bank n
Memory bank m
Referencing value
Memory bank n
Memory bank m
Referencing value
User’s Manual U17554EJ4V0UD
83
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
• Software example (to store a value to be referenced in register A)
RAMD DSEG SADDR
R_BNKA: DS 2 ; Secures RAM for specifying an address at the reference destination.
R_BNKN: DS 1 ; Secures RAM for specifying a memory bank number at the reference destination.
R_BNKRN: DS 1 ; Secures RAM for saving a memory bank number at the reference source.
ETRC CSEG UNIT
ENTRY:
MOV R_BNKN,#BANKNUM DATA1 ; Stores the memory bank number at the reference destination.
MOVW R_BNKA,#DATA1 ; Stores the address at the reference destination.
CALL !BNKRD ; Calls a subroutine for referencing between memory banks.
:
:
BNKC CSEG AT 7000H
BNKRD: ; Subroutine for referencing between memory banks.
PUSH HL ; Saves the contents of the HL register.
MOV A,R_BNKN ; Acquires the memory bank number at the reference destination.
XCH A,BANK ; Swaps the memory bank number at the reference source for that at the reference
; destination
MOV R_BNKRN,A ; Saves the memory bank number at the reference source.
XCHW AX,HL ; Saves the contents of the X register.
MOVW AX,R_BNKA ; Acquires the address at the reference destination.
XCHW AX,HL ; Specifies the address at the reference destination.
MOV A,[HL] ; Reads the target value.
XCH A,R_BNKRN ; Acquires the memory bank number at the reference source.
MOV BANK,A ; Specifies the memory bank number at the reference source.
MOV A,R_BNKRN ; Write the target value to the A register.
POP HL ; Restores the contents of the HL register.
RET ; Return
DATA CSEG BANK3
DATA1: DB 0AAH
END
84
User’s Manual U17554EJ4V0UD
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
4.4.2 Branching instruction between memory banks
Instructions cannot branch directly from one memory bank to another.
To branch an instruction from one memory bank to another, branch once to the common area (0000H to 7FFFH),
change the setting of the BANK register there, and then execute the branch instruction again.
Memory bank n
Bank
area
Common
area
Bank
area
Common
area
Memory bank m
Instruction branch
Memory bank n
Memory bank m
Instruction branch
User’s Manual U17554EJ4V0UD
85
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
• Software example 1 (to branch from all areas)
RAMD DSEG SADDR
R_BNKA: DS 2 ; Secures RAM for specifying a memory bank at the branch destination.
R_BNKN: DS 1 ; Secures RAM for specifying a memory bank number at the branch destination.
RSAVEAX: DS 2 ; Secures RAM for saving the AX register.
ETRC CSEG UNIT
ENTRY:
MOV R_BNKN,#BANKNUM TEST ; Stores the memory bank number at the branch destination in RAM.
MOVW R_BNKA,#TEST ; Stores the address at the branch destination in RAM.
BR !BNKBR ; Branches to inter-memory bank branch processing.
:
:
BNKC CSEG AT 7000H ;
BNKBR:
MOVW RSAVEAX,AX ; Saves the AX register.
MOV A,R_BNKN ; Acquires the memory bank number at the branch destination.
MOV BANK,A ; Specifies the memory bank number at the branch destination.
MOVW AX,R_BNKA ; Specifies the address at the branch destination.
PUSH AX ; Sets the address at the branch destination to stack.
MOVW AX,RSAVEAX ; Restores the AX register.
RET ; Branch
BN3 CSEG BANK3
TEST:
MOV ⋅⋅⋅
:
:
END
• Software example 2 (to branch from common area to any bank area)
ETRC CSEG AT 2000H
ENTRY:
MOV R_BNKN,#BANKNUM TEST ; Stores the memory bank number at the branch destination in RAM.
BR !TEST ; Stores the address at the branch destination in RAM.
BN3 CSEG BANK3
TEST:
MOV ⋅⋅⋅
:
:
END
86
User’s Manual U17554EJ4V0UD
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
4.4.3 Subroutine call between memory banks
Subroutines cannot be directly called between memory banks.
To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the
memory bank at the calling destination by using the BANK register there, execute the CALL instruction, and branch to
the call destination by that instruction.
At this time, save the current value of the BANK register to RAM. Restore the value of the BANK register before
executing the RET instruction.
Memory bank n
Bank
area
Common
area
Bank
area
Common
area
CALL
inst-
ruction
Memory bank m
Memory bank m
CALL instruction
Memory bank n
BR instruction
CALL
instruction
RET instruction
Change BANK and save
memory bank number at
calling source.
RET instruction
User’s Manual U17554EJ4V0UD
87
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
• Software example
RAMD DSEG SADDR
R_BNKA: DS 2 ; Secures RAM for specifying an address at the calling destination.
R_BNKN: DS 1 ; Secures RAM for specifying a memory bank number at the calling destination.
R_BNKRN: DS 1 ; Secures RAM for saving a memory bank number at the calling source.
RSAVEAX: DS 2 ; Secures RAM for saving the AX register.
ETRC CSEG UNIT
ENTRY:
MOV R_BNKN,#BANKNUM TEST ; Store the memory bank number at the calling destination in RAM.
MOVW R_BNKA,#TEST ; Stores the address at the calling destination in RAM.
CALL !BNKCAL ; Branches to an inter-memory bank calling processing routine.
:
:
BNKC CSEG AT 7000H
BNKCAL: ; Inter-memory bank calling processing routine
MOVW RSAVEAX,AX ; Saves the AX register.
MOV A,R_BNKN ; Acquires the memory bank number at the calling destination.
XCH A,BANK ; Changes the bank and acquires the memory bank number at the calling source.
MOV R_BNKRN,A ; Saves the memory bank number at the calling source to RAM.
CALL !BNKCALS ; Calls a subroutine to branch to the calling destination.
MOVW RSAVEAX,AX ; Saves the AX register.
XCH A,R_BNKRN ; Acquires the memory bank number at the calling source.
MOV BANK,A ; Specifies the memory bank number at the calling source.
MOVW RSAVEAX,AX ; Restores the AX register.
RET ; Returns to the calling source.
BNKCALS:
MOVW AX,R_BNKA ; Specifies the address at the calling destination.
PUSH AX ; Sets the address at the calling destination to stack.
MOVW AX,RSAVEAX ; Restores source AX register.
RET AX ; Branches to the calling destination.
BN3 CSEG BANK3
TEST: ;
MOV ⋅⋅⋅
:
:
RET
END
Remark In the software example above, multiplexed processing is not supported.
88
User’s Manual U17554EJ4V0UD
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
4.4.4 Instruction branch to bank area by interrupt
When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the
vector table, but it is difficult to identify the BANK register when the interrupt occurs.
Therefore, specify the branch destination address specified by the vector table in the common area (0000H to
7FFFH), specify the memory bank at the branch destination by using the BANK register in the common area, and
execute the CALL instruction. At this time, save the BANK register value before the change to RAM, and restore the
value of the BANK register before executing the RETI instruction.
Remark Allocate interrupt servicing that requires a quick response in the common area.
Memory bank n
Bank
area
Common
area
Memory bank m
Instruction branch
Vector table
Save the original memory bank number.
Specify the address and memory bank
at the destination, and execute the call
instruction.
• Software example (when using interrupt request of 16-bit timer/event counter 00)
VCTBL CSEG AT 0020H
DW BNKITM000 ; Specifies an address at the timer interrupt destination.
RAMD DSEG SADDR
R_BNKRN: DS 1 ; Secures RAM for saving the memory bank number before the interrupt occurs.
BNKC CSEG AT 7000H
BNKITM000: ; Inter-memory bank interrupt servicing routine
PUSH AX ; Saves the contents of the AX register.
MOV A,BANK
MOV R_BNKRN,A ; Saves the memory bank number before the interrupt to RAM.
MOV BANK,#BANKNUM TEST ; Specifies the memory bank number of the interrupt routine.
CALL !TEST ; Calls the interrupt routine.
MOV A,R_BNKRN ; Restores the memory bank number before the interrupt.
MOV BANK,A
POP AX ; Restores the contents of the AX register.
RETI
BN3 CSEG BANK3
TEST: ; Interrupt servicing routine
MOV ⋅⋅⋅
:
:
RET
END
User’s Manual U17554EJ4V0UD
89
CHAPTER 4 MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY)
Remark Note the following points to use the memory bank select function efficiently.
• Allocate a routine that is used often in the common area.
• If a value that is planned to be referenced is placed in RAM, it can be referenced from all of the areas.
• If the reference destination and the branch destination of the routine placed in a memory bank are
placed in the same memory bank, then the code size and processing are more efficient.
• Allocate interrupt servicing that requires a quick response in the common area.
90
User’s Manual U17554EJ4V0UD
CHAPTER 5 PORT FUNCTIONS
5.1 Port Functions
There are two types of pin I/O buffer power supplies: AV
supplies and the pins is shown below.
Table 5-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P80 to P87, P90 to P93
EVDD Port pins other than P80 to P87, P90 to P93 and P121 to P124
VDD • P121 to P124
• Non-port pins
78K0/FE2 products are provided with the ports shown in Figure 5-1, which enable variety of control operations.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.
The 78K0/FE2 has a total of 55 I/O ports, ports 0, 1, 3 to 9, 12 and 13. The port configuration is shown below.
Figure 5-1. Port Types
REF and EVDD. The relationship between these power
P70
Port 7
P76
P80
Port 8
P87
P90
Port 9
P93
P120
Port 12
P124
P130
Port 13
P132
P00
P01
P05
P06
P10
P17
P30
P33
P40
P43
P50
P53
P60
P63
Port 0
Port 1
Port 3
Port 4
Port 5
Port 6
User’s Manual U17554EJ4V0UD
91
CHAPTER 5 PORT FUNCTIONS
5.2 Port Configuration
Ports include the following hardware.
Table 5-2. Port Configuration
Item Configuration
Control registers
Port Total: 55 (CMOS I/O: 50, CMOS output: 1, N-ch open drain I/O: 4)
Pull-up resistor Total: 34
Port mode register (PM0, PM1, PM3 to PM9, PM12, PM13)
Port register (P0, P1, P3 to P9, P12, P13)
Pull-up resistor option register (PU0, PU1, PU3 to PU5, PU7, PU12, PU13)
92
User’s Manual U17554EJ4V0UD
CHAPTER 5 PORT FUNCTIONS
5.2.1 Port 0
Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00, P01, P05 and P06 pins are used as an input port, use of an on-chip
pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O, serial interface chip select input.
Reset signal generation sets port 0 to input mode.
Figures 5-2 and 5-3 show block diagrams of port 0.
Caution To use P05/SSI11/TI001 as general-purpose ports, set serial operation mode register 11
(CSIM11) to the default status (00H).
Figure 5-2. Block Diagram of P00 and P05
EV
DD
WR
PU
PU0
Internal bus
PU00, PU05
Alternate function
RD
WR
PORT
P0
Output latch
(P00, P05)
WR
PM
PM0
PM00, PM05
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
P-ch
Selector
P00/TI000,
P05/SSI11/TI001
User’s Manual U17554EJ4V0UD
93
CHAPTER 5 PORT FUNCTIONS
Figure 5-3. Block Diagram of P01 and P06
EVDD
WR
PU
PU0
Internal bus
PU01, PU06
Alternate
function
RD
WR
PORT
P0
Output latch
(P01, P06)
WRPM
PM0
PM01, PM06
Alternate
function
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
P-ch
Selector
P01/TI010/TO00,
P06/TI011/TO01
94
User’s Manual U17554EJ4V0UD
CHAPTER 5 PORT FUNCTIONS
5.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
Reset signal generation sets port 1 to input mode.
Figures 5-4 to 5-6 show block diagrams of port 1.
Caution To use P10/SCK10/TxD61 and P12/SO10 as general-purpose ports, set serial operation mode
register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the default status (00H).
Figure 5-4. Block Diagram of P10, P16 and P17
User’s Manual U17554EJ4V0UD
95
CHAPTER 5 PORT FUNCTIONS
Figure 5-5. Block Diagram of P11 and P14
EV
DD
WR
PU
PU1
Internal bus
PU11, PU14
Alternate
function
RD
WR
PORT
P1
Output latch
(P11, P14)
WR
PM
PM1
PM11, PM14
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
P-ch
Selector
P11/SI10/RxD61,
P14/RxD60
96
User’s Manual U17554EJ4V0UD
WR
RD
PORT
WR
Internal bus
WR
CHAPTER 5 PORT FUNCTIONS
Figure 5-6. Block Diagram of P12, P13 and P15
EV
DD
PU
PU1
PU12, PU13,
PU15
Selector
P1
Output latch
(P12, P13, P15)
PM
PM1
PM12, PM13,
PM15
P-ch
P12/SO10,
P13/TxD60,
P15/TOH0
Alternate
function
P1: Port mode register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
User’s Manual U17554EJ4V0UD
97
CHAPTER 5 PORT FUNCTIONS
5.2.3 Port 3
Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified in
1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input and timer I/O.
Reset signal generation sets port 3 to input mode.
Figures 5-7 and 5-8 show block diagrams of port 3.
<R>
Cautions 1. Be sure to pull the P31 pin down before a reset release, to prevent malfunction.
2. Connect P31/TI002/INTP2 as follows when writing the flash memory with a flash programmer.
- P31/TI002/INTP2: Connect to EV
SS via a resistor (10 kΩ: recommended).
The above connection is not necessary when writing the flash memory by means of self
programming.
Remark P31/INTP2/TI002 and P32/INTP3/TI012/TO02 can be used for on-chip debug mode setting when the
on-chip debug function is used. For details, refer to CHAPTER 25 ON-CHIP DEBUG FUNCTION.
Figure 5-7. Block Diagram of P30 and P31
EV
DD
WR
PU
PU3
Internal bus
PU30, PU31
Alternate
function
RD
WR
PORT
P3
Output latch
(P30, P31)
WR
PM
PM3
PM30, PM31
P3: Port register 3
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
P-ch
Selector
P30/INTP1,
P31/INTP2/TI002
98
User’s Manual U17554EJ4V0UD
Internal bus
WR
RD
WR
WRPM
PU
PORT
PU3
PU32, PU33
Alternate
function
P3
Output latch
(P32, P33)
PM3
PM32, PM33
CHAPTER 5 PORT FUNCTIONS
Figure 5-8. Block Diagram of P32 and P33
EVDD
P-ch
Selector
P32/INTP3/TI012/TO02,
P33/INTP4/TI51/TO51
Alternate
function
P3: Port register 3
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
User’s Manual U17554EJ4V0UD
99
CHAPTER 5 PORT FUNCTIONS
5.2.4 Port 4
Port 4 is a 4-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units
using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor
option register 4 (PU4).
Reset signal generation sets port 4 to input mode.
Figure 5-9 shows a block diagram of port 4.
Figure 5-9. Block Diagram of P40 to P43
EV
DD
WR
PU
PU4
RD
WR
WR
PORT
PM
Internal bus
PU40 to PU43
Selector
P4
Output latch
(P40 to P43)
PM4
PM40 to PM43
P-ch
P40 to P43
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
100
User’s Manual U17554EJ4V0UD
Loading...