NEC PD78F0887-A, PD78F0887-A2, PD78F0888-A, PD78F0888-A2, PD78F0889-A User Manual

User’s Manual

78K0/FE2

8-Bit Single-Chip Microcontrollers

μPD78F0887(A) μPD78F0887(A2) μPD78F0888(A) μPD78F0888(A2) μPD78F0889(A) μPD78F0889(A2) μPD78F0890(A) μPD78F0890(A2)

The 78K0/FE2 has an on-chip debug function.

Do not use this product for mass production after the on-chip debug function has been used because its reliability cannot be guaranteed, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning when use this product for mass production after the on-chip debug function has been used.

Document No. U17554EJ4V0UD00 (4th edition)

Date Published March 2007 NS CP(K)

2005

Printed in Japan

[MEMO]

2

User’s Manual U17554EJ4V0UD

NOTES FOR CMOS DEVICES

1VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).

2HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.

3PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.

4STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.

5POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.

6INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

User’s Manual U17554EJ4V0UD

3

EEPROM is trademark of NEC Electronics Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.

Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, inc.

•The information in this document is current as of March, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

•No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.

•NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

•Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

•While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.

•NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.

(Note)

(1)"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries.

(2)"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).

M8E 02. 11-1

4	User’s Manual U17554EJ4V0UD

[MEMO]

User’s Manual U17554EJ4V0UD

5

	INTRODUCTION
Readers	This manual is intended for user engineers who wish to understand the functions of the
	78K0/FE2 and design and develop application systems and programs for these devices.
	The target products are as follows.
	78K0/FE2: μPD78F0887 (A), 78F0888 (A), 78F0889 (A), 78F0890 (A)
	78F0887 (A2), 78F0888 (A2), 78F0889 (A2), 78F0890 (A2)
Purpose	This manual is intended to give users an understanding of the functions described in the
	Organization below.
Organization	The 78K0/FE2 manual are separated into two parts:			this manual and the instructions
	edition (common to the 78K/0 Series).
	78K0/FE2			78K/0 Series
	User’s Manual			User’s Manual
	(This Manual)			Instructions

•Pin functions

•Internal block functions

•Interrupts

•Other on-chip peripheral functions

•Electrical specifications

•CPU functions

•Instruction set

•Explanation of each instruction

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers.

Conventions

6

•When using this manual as the manual for (A) and (A2) grade products:

→Only the quality grade differs between (A) grade products and (A2) grade products.

Read the part number as follows.

•μPD78F0887→ μPD78F0887 (A), 78F0887 (A2)

•μPD78F0888→ μPD78F0888 (A), 78F0888 (A2)

•μPD78F0889→ μPD78F0889 (A), 78F0889 (A2)

•μPD78F0890→ μPD78F0890 (A), 78F0890 (A2)

•To gain a general understanding of functions:

→Read this manual in the order of the CONTENTS. The mark <R> shows major revised points.

•How to interpret the register format:

→For a bit number enclosed in brackets, the bit name is defined as a reserved word in the assembler, and is already defined in the header file named sfrbit.h in the C compiler.

•To check the details of a register when you know the register name:

→Refer to APPENDIX C REGISTER INDEX.

Data significance:	Higher digits on the left and lower digits on the right
Active low representations:		(overscore over pin and signal name)
	×××
Note:	Footnote for item marked with Note in the text.
Caution:	Information requiring particular attention
Remark:	Supplementary information
Numerical representations:	Binary		...×××× or ××××B
	Decimal		...××××
	Hexadecimal		...××××H

User’s Manual U17554EJ4V0UD

<R>

<R>

Related Documents	The related documents indicated in this publication may include preliminary versions.
	However, preliminary versions are not marked as such.
Documents Related to Devices
	Document Name		Document No.
78K0/FE2 User’s Manual			This manual
78K/0 Series Instructions User’s Manual			U12326E
Documents Related to Development Tools (Software) (User’s Manuals)
	Document Name		Document No.
RA78K0 Ver.3.80 Assembler Package		Operation	U17199E
		Language	U17198E
		Structured Assembly Language	U17197E
CC78K0 Ver.3.70 C Compiler		Operation	U17201E
		Language	U17200E
ID78K0-QB Ver. 2.90 Integrated Debugger		Operation	U17437E
PM plus Ver. 5.20			U16934E
Documents Related to Development Tools (Hardware) (User’s Manuals)
	Document Name		Document No.
QB-78K0FX2 In-Circuit Emulator			U17534E
QB-78K0MINI ON-CHIP DEBUG Emulator			U17029E
QB-MINI2 On-Chip Debug Emulator with Programming Function			U18371E
Documents Related to Flash Memory Programming
	Document Name		Document No.
PG-FP4 Flash Memory Programmer User’s Manual			U15260E
PG-FPL3 Flash Memory Programmer User’s Manual			U17454E
Other Documents
	Document Name		Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages −			X13769X
Semiconductor Device Mount Manual			Note
Quality Grades on NEC Semiconductor Devices			C11531E
NEC Semiconductor Device Reliability/Quality Control System			C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)			C11892E

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.

User’s Manual U17554EJ4V0UD

7

				CONTENTS
CHAPTER 1		OUTLINE ............................................................................................................................			17
1.1	Features.........................................................................................................................................				17
1.2	Applications..................................................................................................................................				18
1.3	Ordering Information ...................................................................................................................				18
1.4	Pin Configuration (Top View) ......................................................................................................				19
1.5	Fx2 Series Lineup.........................................................................................................................				21
	1.5.1	78K0/Fx2 product lineup ...................................................................................................................			21
1.6	Block Diagram ..............................................................................................................................				23
1.7	Outline of Functions ....................................................................................................................				24
CHAPTER 2		PIN FUNCTIONS ...............................................................................................................			26
2.1	Pin Function List ..........................................................................................................................				26
2.2	Description of Pin Functions ......................................................................................................				30
	2.2.1	P00, P01, P05, P06 (port 0) ..............................................................................................................			30
	2.2.2	P10 to P17 (port 1) ............................................................................................................................			31
	2.2.3	P30 to P33 (port 3) ............................................................................................................................			32
	2.2.4	P40 to P43 (port 4) ............................................................................................................................			32
	2.2.5	P50 to P53 (port 5) ............................................................................................................................			33
	2.2.6	P60 to P63 (port 6) ............................................................................................................................			33
	2.2.7	P70 to P76 (port 7) ............................................................................................................................			33
	2.2.8	P80 to P87 (port 8) ............................................................................................................................			34
	2.2.9	P90 to P93 (port 9) ............................................................................................................................			34
	2.2.10		P120 to P124 (port 12) ....................................................................................................................		34
	2.2.11		P130 to P132 (port 13) ....................................................................................................................		35
	2.2.12 AVREF...............................................................................................................................................				36
	2.2.13 AVSS ................................................................................................................................................				36
	2.2.14 RESET ............................................................................................................................................				36
	2.2.15 REGC..............................................................................................................................................				36
	2.2.16 VDD and EVDD ..................................................................................................................................				36
	2.2.17 VSS and EVSS...................................................................................................................................				36
	2.2.18 FLMD0 ............................................................................................................................................				36
2.3	Pin I/O Circuits and Recommended Connection of Unused Pins ...........................................				37
CHAPTER 3		CPU ARCHITECTURE ......................................................................................................			41
3.1	Memory Space ..............................................................................................................................				41
	3.1.1	Internal program memory space........................................................................................................			48
	3.1.2 Bank area (μPD78F0889 and 78F0890 only)....................................................................................				49
	3.1.3	Internal data memory space..............................................................................................................			51
	3.1.4	Special function register (SFR) area .................................................................................................			51
	3.1.5 Data memory addressing ..................................................................................................................				51
3.2	Processor Registers ....................................................................................................................				56
	3.2.1	Control registers ................................................................................................................................			56
	3.2.2	General-purpose registers.................................................................................................................			60
	3.2.3	Special Function Registers (SFRs) ...................................................................................................			61
3.3	Instruction Address Addressing.................................................................................................				68
8				User’s Manual U17554EJ4V0UD

	3.3.1	Relative addressing............................................................................................................................	68
	3.3.2	Immediate addressing........................................................................................................................	69
	3.3.3	Table indirect addressing ...................................................................................................................	70
	3.3.4	Register addressing ...........................................................................................................................	70
3.4	Operand Address Addressing ....................................................................................................		71
	3.4.1	Implied addressing .............................................................................................................................	71
	3.4.2	Register addressing ...........................................................................................................................	72
	3.4.3	Direct addressing ...............................................................................................................................	73
	3.4.4	Short direct addressing ......................................................................................................................	74
	3.4.5	Special function register (SFR) addressing........................................................................................	75
	3.4.6	Register indirect addressing...............................................................................................................	76
	3.4.7	Based addressing ..............................................................................................................................	77
	3.4.8	Based indexed addressing.................................................................................................................	78
	3.4.9	Stack addressing................................................................................................................................	79
CHAPTER 4		MEMORY BANK SELECT FUNCTION (μPD78F0889, 78F0890 ONLY) ..................	80
4.1	Memory Bank................................................................................................................................		80
4.2	Difference in Representation of Memory Space .......................................................................		81
4.3	Memory Bank Select Register (BANK).......................................................................................		82
4.4	Selecting Memory Bank...............................................................................................................		83
	4.4.1 Referencing values between memory banks .....................................................................................		83
	4.4.2	Branching instruction between memory banks...................................................................................	85
	4.4.3	Subroutine call between memory banks ............................................................................................	87
	4.4.4	Instruction branch to bank area by interrupt.......................................................................................	89
CHAPTER 5		PORT FUNCTIONS...........................................................................................................	91
5.1	Port Functions..............................................................................................................................		91
5.2	Port Configuration .......................................................................................................................		92
	5.2.1	Port 0 .................................................................................................................................................	93
	5.2.2	Port 1 .................................................................................................................................................	95
	5.2.3	Port 3 .................................................................................................................................................	98
	5.2.4	Port 4 ...............................................................................................................................................	100
	5.2.5	Port 5 ...............................................................................................................................................	101
	5.2.6	Port 6 ...............................................................................................................................................	102
	5.2.7	Port 7 ...............................................................................................................................................	103
	5.2.8	Port 8 ...............................................................................................................................................	108
	5.2.9	Port 9 ...............................................................................................................................................	109
	5.2.10	Port 12 ...........................................................................................................................................	110
	5.2.11	Port 13 ...........................................................................................................................................	113
5.3	Registers Controlling Port Function ........................................................................................		116
5.4	Port Function Operations..........................................................................................................		123
	5.4.1	Writing to I/O port.............................................................................................................................	123
	5.4.2	Reading from I/O port.......................................................................................................................	123
	5.4.3	Operations on I/O port......................................................................................................................	123
5.5	Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)....................................		124
CHAPTER 6		CLOCK GENERATOR ....................................................................................................	125
6.1	Functions of Clock Generator...................................................................................................		125
		User’s Manual U17554EJ4V0UD	9

6.2	Configuration of Clock Generator ............................................................................................		126
6.3	Registers Controlling Clock Generator....................................................................................		128
6.4	System Clock Oscillator ............................................................................................................		137
	6.4.1	X1 oscillator......................................................................................................................................	137
	6.4.2	XT1 oscillator....................................................................................................................................	137
	6.4.3 When subsystem clock is not used ..................................................................................................		140
	6.4.4	Internal high-speed oscillator............................................................................................................	140
	6.4.5	Internal low-speed oscillator.............................................................................................................	140
	6.4.6	Prescaler ..........................................................................................................................................	140
6.5	Clock Generator Operation .......................................................................................................		141
6.6	Controlling Clock........................................................................................................................		145
	6.6.1	Controlling high-speed system clock ................................................................................................	145
	6.6.2	Example of controlling internal high-speed oscillation clock.............................................................	148
	6.6.3	Example of controlling subsystem clock...........................................................................................	150
	6.6.4	Controlling internal low-speed oscillation clock ................................................................................	152
	6.6.5	Clocks supplied to CPU and peripheral hardware ............................................................................	152
	6.6.6	CPU clock status transition diagram.................................................................................................	153
	6.6.7	Condition before changing CPU clock and processing after changing CPU clock ...........................	158
	6.6.8	Time required for switchover of CPU clock and main system clock .................................................	159
	6.6.9	Conditions before clock oscillation is stopped ..................................................................................	160
CHAPTER 7		16-BIT TIMER/EVENT COUNTERS 00 TO 03 ...........................................................	161
7.1	Functions of 16-Bit Timer/Event Counters 00 to 03................................................................		161
7.2	Configuration of 16-Bit Timer/Event Counters 00 to 03 .........................................................		162
7.3	Registers Controlling 16-Bit Timer/Event Counters 00 to 03.................................................		171
7.4	Operation of 16-Bit Timer/Event Counters 00 to 03................................................................		192
	7.4.1	Interval timer operation.....................................................................................................................	192
	7.4.2	PPG output operations .....................................................................................................................	195
	7.4.3	Pulse width measurement operations ..............................................................................................	198
	7.4.4	External event counter operation......................................................................................................	206
	7.4.5	Square-wave output operation .........................................................................................................	209
	7.4.6	One-shot pulse output operation ......................................................................................................	211
7.5	Special Use of TM0n ..................................................................................................................		216
	7.5.1	Rewriting CR01n during TM0n operation .........................................................................................	216
	7.5.2 Setting LVS0n and LVR0n ...............................................................................................................		216
7.6	Cautions for 16-Bit Timer/Event Counters 00 to 03 ................................................................		218
CHAPTER 8		8-BIT TIMER/EVENT COUNTERS 50 AND 51...........................................................	222
8.1	Functions of 8-Bit Timer/Event Counters 50 and 51...............................................................		222
8.2	Configuration of 8-Bit Timer/Event Counters 50 and 51 ........................................................		224
8.3	Registers Controlling 8-Bit Timer/Event Counters 50 and 51................................................		226
8.4	Operations of 8-Bit Timer/Event Counters 50 and 51.............................................................		231
	8.4.1	Operation as interval timer ...............................................................................................................	231
	8.4.2	Operation as external event counter ................................................................................................	233
	8.4.3	Square-wave output operation .........................................................................................................	234
	8.4.4 PWM output operation......................................................................................................................		235
8.5	Cautions for 8-Bit Timer/Event Counters 50 and 51 ...............................................................		239
10		User’s Manual U17554EJ4V0UD

CHAPTER 9		8-BIT TIMERS H0 AND H1 ..........................................................................................	240
9.1 Functions of 8-Bit Timers H0 and H1 .......................................................................................			240
9.2 Configuration of 8-Bit Timers H0 and H1.................................................................................			240
9.3 Registers Controlling 8-Bit Timers H0 and H1........................................................................			244
9.4 Operation of 8-Bit Timers H0 and H1 .......................................................................................			249
	9.4.1	Operation as interval timer/square-wave output...............................................................................	249
	9.4.2 Operation as PWM output mode......................................................................................................		252
	9.4.3	Carrier generator mode operation (8-bit timer H1 only)....................................................................	258
CHAPTER 10		WATCH TIMER .............................................................................................................	265
10.1	Functions of Watch Timer.......................................................................................................		265
10.2	Configuration of Watch Timer.................................................................................................		266
10.3	Register Controlling Watch Timer..........................................................................................		267
10.4	Watch Timer Operations..........................................................................................................		269
	10.4.1	Watch timer operation ....................................................................................................................	269
	10.4.2	Interval timer operation ..................................................................................................................	270
10.5	Cautions for Watch Timer .......................................................................................................		271
CHAPTER 11		WATCHDOG TIMER .....................................................................................................	272
11.1	Functions of Watchdog Timer ................................................................................................		272
11.2	Configuration of Watchdog Timer..........................................................................................		273
11.3	Register Controlling Watchdog Timer ...................................................................................		274
11.4	Operation of Watchdog Timer.................................................................................................		275
	11.4.1	Controlling operation of watchdog timer.........................................................................................	275
	11.4.2	Setting overflow time of watchdog timer.........................................................................................	277
	11.4.3	Setting window open period of watchdog timer..............................................................................	278
CHAPTER 12		CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER...............................................	280
12.1	Functions of Clock Output/Buzzer Output Controller..........................................................		280
12.2	Configuration of Clock Output/Buzzer Output Controller ...................................................		281
12.3	Register Controlling Clock Output/Buzzer Output Controller.............................................		281
12.4	Clock Output/Buzzer Output Controller Operations.............................................................		284
	12.4.1	Clock output operation ...................................................................................................................	284
	12.4.2	Operation as buzzer output............................................................................................................	284
CHAPTER 13		A/D CONVERTER .........................................................................................................	285
13.1	Function of A/D Converter ......................................................................................................		285
13.2	Configuration of A/D Converter..............................................................................................		286
13.3	Registers Used in A/D Converter ...........................................................................................		288
13.4	A/D Converter Operations.......................................................................................................		296
	13.4.1	Basic operations of A/D converter..................................................................................................	296
	13.4.2	Input voltage and conversion results..............................................................................................	298
	13.4.3	A/D converter operation mode .......................................................................................................	299
13.5	How to Read A/D Converter Characteristics Table ..............................................................		301
13.6	Cautions for A/D Converter.....................................................................................................		303
CHAPTER 14		SERIAL INTERFACES UART60 AND UART61..........................................................	307
14.1	Functions of Serial Interfaces UART60 and UART61 ...........................................................		307
		User’s Manual U17554EJ4V0UD	11

14.2	Configurations of Serial Interface UART60 and UART61.....................................................		312
14.3	Registers Controlling Serial Interfaces UART60 and UART61 ............................................		316
14.4	Operations of Serial Interface UART60 and UART61............................................................		335
	14.4.1 Operation stop mode......................................................................................................................		335
	14.4.2	Asynchronous serial interface (UART) mode .................................................................................	336
	14.4.3	Dedicated baud rate generator.......................................................................................................	351
CHAPTER 15		SERIAL INTERFACES CSI10 AND CSI11................................................................	357
15.1	Functions of Serial Interfaces CSI10 and CSI11 ...................................................................		357
15.2	Configuration of Serial Interfaces CSI10 and CSI11.............................................................		358
15.3	Registers Controlling Serial Interfaces CSI10 and CSI11 ....................................................		360
15.4	Operation of Serial Interfaces CSI10 and CSI11....................................................................		365
	15.4.1 Operation stop mode......................................................................................................................		365
	15.4.2	3-wire serial I/O mode ....................................................................................................................	366
CHAPTER 16		CAN CONTROLLER .....................................................................................................	378
16.1	Outline Description ..................................................................................................................		378
	16.1.1	Features .........................................................................................................................................	378
	16.1.2	Overview of functions .....................................................................................................................	379
	16.1.3	Configuration ..................................................................................................................................	380
16.2	CAN Protocol ............................................................................................................................		381
	16.2.1 Frame format..................................................................................................................................		381
	16.2.2 Frame types ...................................................................................................................................		382
	16.2.3 Data frame and remote frame ........................................................................................................		382
	16.2.4	Error frame .....................................................................................................................................	390
	16.2.5	Overload frame...............................................................................................................................	391
16.3	Functions ..................................................................................................................................		392
	16.3.1	Determining bus priority .................................................................................................................	392
	16.3.2	Bit stuffing ......................................................................................................................................	392
	16.3.3	Multi masters..................................................................................................................................	392
	16.3.4	Multi cast ........................................................................................................................................	392
	16.3.5 CAN sleep mode/CAN stop mode function ....................................................................................		392
	16.3.6	Error control function ......................................................................................................................	393
	16.3.7	Baud rate control function ..............................................................................................................	399
16.4	Connection with Target System..............................................................................................		403
16.5	Internal Registers of CAN Controller......................................................................................		404
	16.5.1	CAN controller configuration...........................................................................................................	404
	16.5.2	Register access type ......................................................................................................................	405
	16.5.3	Register bit configuration................................................................................................................	414
16.6	Bit Set/Clear Function..............................................................................................................		418
16.7	Control Registers .....................................................................................................................		420
16.8	CAN Controller Initialization....................................................................................................		455
	16.8.1	Initialization of CAN module ...........................................................................................................	455
	16.8.2	Initialization of message buffer .......................................................................................................	455
	16.8.3	Redefinition of message buffer.......................................................................................................	455
	16.8.4	Transition from initialization mode to operation mode ....................................................................	456
	16.8.5 Resetting error counter C0ERC of CAN module ............................................................................		457
16.9	Message Reception..................................................................................................................		458
12		User’s Manual U17554EJ4V0UD

	16.9.1	Message reception.........................................................................................................................	458
	16.9.2 Receive Data Read ........................................................................................................................		459
	16.9.3	Receive history list function............................................................................................................	460
	16.9.4	Mask function.................................................................................................................................	462
	16.9.5	Multi buffer receive block function ..................................................................................................	464
	16.9.6	Remote frame reception.................................................................................................................	465
16.10 Message Transmission..........................................................................................................			466
	16.10.1	Message transmission .................................................................................................................	466
	16.10.2	Transmit history list function.........................................................................................................	468
	16.10.3	Automatic block transmission (ABT) ............................................................................................	470
	16.10.4	Transmission abort process .........................................................................................................	471
	16.10.5	Remote frame transmission .........................................................................................................	472
16.11 Power Save Modes.................................................................................................................			473
	16.11.1 CAN sleep mode ..........................................................................................................................		473
	16.11.2 CAN stop mode............................................................................................................................		475
	16.11.3 Example of using power saving modes........................................................................................		476
16.12	Interrupt Function ..................................................................................................................		477
16.13 Diagnosis Functions and Special Operational Modes .......................................................			478
	16.13.1 Receive-only mode ......................................................................................................................		478
	16.13.2	Single-shot mode .........................................................................................................................	479
	16.13.3	Self-test mode..............................................................................................................................	480
	16.13.4	Receive/Transmit Operation in Each Operation Mode .................................................................	481
16.14 Time Stamp Function.............................................................................................................			482
	16.14.1	Time stamp function.....................................................................................................................	482
16.15 Baud Rate Settings ................................................................................................................			484
	16.15.1	Baud rate settings ........................................................................................................................	484
	16.15.2	Representative examples of baud rate settings ...........................................................................	488
16.16 Operation of CAN Controller.................................................................................................			492
CHAPTER 17		INTERRUPT FUNCTIONS ............................................................................................	518
17.1 Interrupt Function Types.........................................................................................................			518
17.2 Interrupt Sources and Configuration .....................................................................................			518
17.3	Registers Controlling Interrupt Functions ............................................................................		522
17.4	Interrupt Servicing Operations ...............................................................................................		530
	17.4.1	Maskable interrupt acknowledgement............................................................................................	530
	17.4.2	Software interrupt request acknowledgement ................................................................................	532
	17.4.3	Multiple interrupt servicing .............................................................................................................	533
	17.4.4	Interrupt request hold .....................................................................................................................	536
CHAPTER 18		STANDBY FUNCTION..................................................................................................	537
18.1 Standby Function and Configuration.....................................................................................			537
	18.1.1	Standby function ............................................................................................................................	537
	18.1.2	Registers controlling standby function............................................................................................	537
18.2 Standby Function Operation...................................................................................................			540
	18.2.1 HALT mode....................................................................................................................................		540
	18.2.2 STOP mode ...................................................................................................................................		546

User’s Manual U17554EJ4V0UD

13

CHAPTER 19		RESET FUNCTION........................................................................................................		553
19.1	Register for Confirming Reset Source...................................................................................			561
CHAPTER 20		MULTIPLIER/DIVIDER...................................................................................................		562
20.1	Functions of Multiplier/Divider................................................................................................			562
20.2	Configuration of Multiplier/Divider .........................................................................................			562
20.3	Register Controlling Multiplier/Divider ..................................................................................			566
20.4	Operations of Multiplier/Divider..............................................................................................			567
	20.4.1	Multiplication operation...................................................................................................................		567
	20.4.2	Division operation...........................................................................................................................		569
CHAPTER 21		POWER-ON-CLEAR CIRCUIT......................................................................................		571
21.1	Functions of Power-on-Clear Circuit......................................................................................			571
21.2	Configuration of Power-on-Clear Circuit ...............................................................................			572
21.3	Operation of Power-on-Clear Circuit......................................................................................			572
21.4	Cautions for Power-on-Clear Circuit ......................................................................................			575
CHAPTER 22		LOW-VOLTAGE DETECTOR .......................................................................................		577
22.1	Functions of Low-Voltage Detector........................................................................................			577
22.2	Configuration of Low-Voltage Detector .................................................................................			578
22.3	Registers Controlling Low-Voltage Detector.........................................................................			578
22.4	Operation of Low-Voltage Detector........................................................................................			581
	22.4.1 When used as reset .......................................................................................................................			582
	22.4.2	When used as interrupt ..................................................................................................................		587
22.5	Cautions for Low-Voltage Detector ........................................................................................			592
CHAPTER 23		OPTION BYTE...............................................................................................................		595
23.1	Functions of Option Bytes ......................................................................................................			595
23.2	Format of Option Byte .............................................................................................................			597
CHAPTER 24		FLASH MEMORY..........................................................................................................		600
24.1	Internal Memory Size Switching Register..............................................................................			600
24.2	Internal Expansion RAM Size Switching Register ................................................................			601
24.3	Writing with Flash Memory Programmer ...............................................................................			602
24.4	Programming Environment .....................................................................................................			605
24.5	Communication Mode..............................................................................................................			605
24.6	Connection of Pins on Board..................................................................................................			607
	24.6.1 FLMD0 pin......................................................................................................................................			607
	24.6.2	Serial interface pins........................................................................................................................		607
	24.6.3 RESET pin......................................................................................................................................			609
	24.6.4	Port pins .........................................................................................................................................		609
	24.6.5 REGC pin .......................................................................................................................................			609
	24.6.6	Other signal pins ............................................................................................................................		609
	24.6.7	Power supply..................................................................................................................................		610
24.7	Programming Method ..............................................................................................................			611
	24.7.1	Controlling flash memory................................................................................................................		611
	24.7.2 Flash memory programming mode.................................................................................................			611
14			User’s Manual U17554EJ4V0UD

	24.7.3 Selecting communication mode .....................................................................................................		612
	24.7.4 Communication commands............................................................................................................		613
24.8	Security Settings......................................................................................................................		614
24.9	Processing Time for Each Command When PG-FP4 Is Used (Reference) ........................		616
24.10 Flash Memory Programming by Self-Programming...........................................................			617
	24.10.1	Registers used for self-programming function..............................................................................	624
24.11 Boot Swap Function ..............................................................................................................			628
CHAPTER 25		ON-CHIP DEBUG FUNCTION.....................................................................................	630
25.1	Outline of Functions ................................................................................................................		630
25.2	Connection with MINICUBE ....................................................................................................		631
25.3	Connection Circuit Examples .................................................................................................		632
25.4	On-Chip Debug Security ID.....................................................................................................		634
25.5	Restrictions and Cautions on On-Chip Debug Function .....................................................		634
CHAPTER 26		INSTRUCTION SET ......................................................................................................	635
26.1	Conventions Used in Operation List......................................................................................		635
	26.1.1	Operand identifiers and specification methods ..............................................................................	635
	26.1.2	Description of operation column.....................................................................................................	636
	26.1.3	Description of flag operation column ..............................................................................................	636
26.2	Operation List...........................................................................................................................		637
26.3	Instructions Listed by Addressing Type ...............................................................................		645
CHAPTER 27		ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)..................................	648
27.1	Absolute Maximum Ratings....................................................................................................		648
27.2	Oscillator Characteristics........................................................................................................		650
27.3	DC Characteristics ...................................................................................................................		652
27.4	AC Characteristics ...................................................................................................................		659
27.5	Data Retention Characteristics...............................................................................................		669
27.6	Flash EEPROM Programming Characteristics......................................................................		670
CHAPTER 28		ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)................................	671
28.1	Absolute Maximum Ratings....................................................................................................		671
28.2	Oscillator Characteristics........................................................................................................		673
28.3	DC Characteristics ...................................................................................................................		675
28.4	AC Characteristics ...................................................................................................................		681
28.5	Data Retention Characteristics...............................................................................................		691
28.6	Flash EEPROM Programming Characteristics......................................................................		692
CHAPTER 29		PACKAGE DRAWINGS................................................................................................	693
CHAPTER 30		RECOMMENDED SOLDERING CONDITIONS...........................................................	695
CHAPTER 31		CAUTIONS FOR WAIT ................................................................................................	696
31.1	Cautions for Wait .....................................................................................................................		696
31.2	Peripheral Hardware That Generates Wait ............................................................................		697
31.3	Example of Wait Occurrence ..................................................................................................		699
		User’s Manual U17554EJ4V0UD	15

APPENDIX A		DEVELOPMENT TOOLS...............................................................................................	700
A.1	Software Package ......................................................................................................................		704
A.2	Language Processing Software ...............................................................................................		704
A.3	Control Software........................................................................................................................		705
A.4	Flash Memory Programming Tools..........................................................................................		706
	A.4.1 When using flash memory programmer FG-FP4, FL-PR4, PG-FPL3, and FP-LITE3 ......................		706
	A.4.2 When using on-chip debug emulator with programming function QB-MINI2....................................		706
A.5	Debugging Tools (Hardware)....................................................................................................		707
	A.5.1	When using in-circuit emulator QB-78K0FX2...................................................................................	707
	A.5.2 When using on-chip debug emulator QB-78K0MINI ........................................................................		707
	A.5.3 When using on-chip debug emulator with programming function QB-MINI2....................................		708
A.6	Debugging Tools (Software).....................................................................................................		708
APPENDIX B		NOTES ON TARGET SYSTEM DESIGN ...................................................................	709
APPENDIX C		REGISTER INDEX .........................................................................................................	711
C.1	Register Index (In Alphabetical Order with Respect to Register Names)............................		711
C.2	Register Index (In Alphabetical Order with Respect to Register Symbol)...........................		716
APPENDIX D		REVISION HISTORY .....................................................................................................	721
D.1	Main Revisions in this Edition..................................................................................................		721
D.2	Revision History of Preceding Editions ..................................................................................		722

16	User’s Manual U17554EJ4V0UD

CHAPTER 1 OUTLINE

1.1Features

{Minimum instruction execution time can be changed from high speed (0.1 μs: @ 20 MHz operation with highspeed system clock) to ultra low-speed (122 μs: @ 32.768 kHz operation with subsystem clock)

{General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)

{ROM, RAM capacities

Item	Program Memory		Data Memory
	(ROM)
Part Number			Internal High-Speed RAM	Note	Internal Expansion RAM	Note
μPD78F0887	Flash memoryNote	48 KB	1024 bytes		2048 bytes
μPD78F0888		60 KB
μPD78F0889		96KB			4096 bytes
μPD78F0890		128 KB			6144 bytes

Note The internal flash memory, internal high-speed RAM capacities, and internal expansion RAM capacities can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS).

{On-chip single-power-supply flash memory

{Self-programming (with boot swap function)

{On-chip debug function

{On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)

{Short startup is possible via the CPU default start using the on-chip internal high-speed oscillator

{On-chip watchdog timer (operable with on-chip internal low-speed oscillator clock)

{On-chip multiplier/divider

{On-chip clock output/buzzer output controller

{I/O ports: 55 (N-ch open drain: 4)

{Timer: 10 channels

{Serial interface: 4 channels

(UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI/UART Note: 1 channel, CSI: 1 channel, CAN: 1 channel)

{10-bit resolution A/D converter: 12 channels

{Supply voltage: VDD = 4.0 to 5.5 V when 20 MHz, VDD = 2.7 to 5.5 V when 10 MHz, VDD = 1.8 to 5.5 V when 5 MHz

(with internal high-speed oscillator clock or subsystem clock: VDD = 1.8 to 5.5 V)

{ Operating ambient temperature: TA = −40 to +85°C, −40 to +125°C

Note Select either of the functions of these alternate-function pins.

User’s Manual U17554EJ4V0UD

17

CHAPTER 1 OUTLINE

1.2Applications

{Automotive electrical appliances (Body control, Door control, Front light control)

{Industrial equipment (Industrial robot, Building control)

1.3Ordering Information

• Flash memory version
Part Number	Package	Quality Grade
μPD78F0887GK(A)-GAJ-AX	64-pin plastic LQFP (12x12)	Special
μPD78F0887GK(A2)-GAJ-AX	64-pin plastic LQFP (12x12)	Special
μPD78F0887GB(A)-GAH-AX	64-pin plastic LQFP (Fine pitch) (10x10)	Special
μPD78F0887GB(A2)-GAH-AX	64-pin plastic LQFP (Fine pitch) (10x10)	Special
μPD78F0888GK(A)-GAJ-AX	64-pin plastic LQFP (12x12)	Special
μPD78F0888GK(A2)-GAJ-AX	64-pin plastic LQFP (12x12)	Special
μPD78F0888GB(A)-GAH-AX	64-pin plastic LQFP (Fine pitch) (10x10)	Special
μPD78F0888GB(A2)-GAH-AX	64-pin plastic LQFP (Fine pitch) (10x10)	Special
μPD78F0889GK(A)-GAJ-AX	64-pin plastic LQFP (12x12)	Special
μPD78F0889GK(A2)-GAJ-AX	64-pin plastic LQFP (12x12)	Special
μPD78F0889GB(A)-GAH-AX	64-pin plastic LQFP (Fine pitch) (10x10)	Special
μPD78F0889GB(A2)-GAH-AX	64-pin plastic LQFP (Fine pitch) (10x10)	Special
μPD78F0890GK(A)-GAJ-AX	64-pin plastic LQFP (12x12)	Special
μPD78F0890GK(A2)-GAJ-AX	64-pin plastic LQFP (12x12)	Special
μPD78F0890GB(A)-GAH-AX	64-pin plastic LQFP (Fine pitch) (10x10)	Special
μPD78F0890GB(A2)-GAH-AX	64-pin plastic LQFP (Fine pitch) (10x10)	Special

Remark All these products are lead free products.

18	User’s Manual U17554EJ4V0UD

CHAPTER 1 OUTLINE

1.4Pin Configuration (Top View)

•64-pin plastic LQFP (12x12)

•64-pin plastic LQFP (Fine pitch) (10x10)

	P131/TI003	P132/TI013/TO03 P00/TI000	P01/TI010/TO00 P80/ANI0 P81/ANI1 P82/ANI2 P83/ANI3	P84/ANI4	P85/ANI5 P86/ANI6 P87/ANI7	P90/ANI8	P91/ANI9	P92/ANI10	P93/ANI11
P120/INTP0/EXLVI	64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49									AVSS
	1								48
P43	2								47	AVREF
P42	3								46	P10/SCK10/TxD61
P41	4								45	P11/SI10/RxD61
P40	5								44	P12/SO10
RESET	6								43	P13/TxD60
P124/XT2/EXCLKS	7								42	P14/RxD60
P123/XT1	8								41	P15/TOH0
FLMD0	9								40	P16/TOH1/INTP5
P122/X2/EXCLK	10								39	P17/TI50/TO50
P121/X1	11								38	P30/INTP1
REGC	12								37	P53
VSS	13								36	P52
EVSS	14								35	P51
VDD	15								34	P50
EVDD	16								33	P31/TI002/INTP2
	17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
	P60	P61 P62	P63 P33/TI51/TO51/INTP4 P130 P76/SCK11 P75/SI11	P74/SO11	P73/BUZ/INTP7 P72/PCL/INTP6 P71/CRxD	P70/CTxD	P06/TI011/TO01	P05/SSI11/TI001	P32/TI012/TO02/INTP3

Cautions 1. Make AVSS and EVSS the same potential as VSS.

2.Make EVDD the same potential as VDD.

3.Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF: recommended).

4.ANI0/P80 to ANI11/P93 are set in the analog input mode after release of reset.

User’s Manual U17554EJ4V0UD

19

CHAPTER 1 OUTLINE

Pin Identification
ANI0 to ANI11:	Analog input	P90 to P93:						Port 9
AVREF:	Analog reference voltage	P120 to P124:						Port 12
AVSS:	Analog ground	P130 to P132:						Port 13
BUZ:	Buzzer output	PCL:						Programmable clock output
CRxD:	Receive data for CAN	REGC:						Regulator Capacitance
CTxD:	Transmit data for CAN	RESET:						Reset
EVDD:	Power supply for port	RxD60, RxD61:						Receive data
EVSS:	Ground for port	SCK10,				SCK11:		Serial clock input/output
EXCLK:	External clock input	SI10, SI11:						Serial data input
	(Main system clock)	SO10, SO11:						Serial data output
EXCLKS:	External clock input							Serial interface chip select input
		SSI11:
	(Subsystem clock)	TI000, TI010,
EXLVI:	External potential input	TI001, TI011,
	for low-voltage detector	TI002, TI012,
FLMD0:	Flash programming mode	TI003, TI013,
INTP0 to INTP7: External interrupt input		TI50, TI51:						Timer input
P00, P01,		TO00, TO01,
P05, P06:	Port 0	TO02, TO03
P10 to P17:	Port 1	TO50, TO51,
P30 to P33:	Port 3	TOH0, TOH1:						Timer output
P40 to P43:	Port 4	TxD60, TxD61:						Transmit data
P50 to P53:	Port 5	VDD:						Power supply
P60 to P63:	Port 6	VSS:						Ground
P70 to P76:	Port 7	X1, X2:						Crystal oscillator (high-speed system clock)
P80 to P87:	Port 8	XT1, XT2:						Crystal oscillator (subsystem clock)

20	User’s Manual U17554EJ4V0UD

CHAPTER 1 OUTLINE

1.5 Fx2 Series Lineup

1.5.1 78K0/Fx2 product lineup

•44-pin LQFP (10 × 10 mm 0.8 mm pitch) 78K0/FC2

	μPD78F0881		μPD78F0882		μPD78F0883
	Single-power-supply flash		Single-power-supply flash		Single-power-supply flash
	memory: 32 KB,		memory: 48 KB,		memory: 60KB,
RAM: 2 KB			RAM: 3 KB		RAM: 3 KB

•48-pin LQFP (7 × 7 mm 0.5 mm pitch) 78K0/FC2

	μPD78F0884		μPD78F0885		μPD78F0886
	Single-power-supply flash		Single-power-supply flash		Single-power-supply flash
	memory: 32 KB,		memory: 48 KB,		memory: 60KB,
RAM: 2 KB			RAM: 3 KB		RAM: 3 KB

•64-pin LQFP (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch) 78K0/FE2

			μPD78F0887		μPD78F0888		μPD78F0889		μPD78F0890
			Single-power-supply	flash	Single-power-supply flash		Single-power-supply flash		Single-power-supply	flash
			memory: 48 KB,		memory: 60 KB,		memory: 96 KB,		memory: 128 KB,
			RAM: 3 KB		RAM: 3 KB		RAM: 5 KB		RAM: 7 KB
• 80-pin LQFP (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch)
	78K0/FF2
					μPD78F0891		μPD78F0892		μPD78F0893
					Single-power-supply flash		Single-power-supply flash		Single-power-supply	flash
					memory: 60 KB,		memory: 96 KB,		memory: 128 KB,
					RAM: 3 KB		RAM: 5 KB		RAM: 7 KB

Remark All product with on-chip debug function.

User’s Manual U17554EJ4V0UD

21

CHAPTER 1 OUTLINE

The list of functions in the 78K0/Fx2 is shown below.

				Part Number	78K0/FC2				78K0/FE2		78K0/FF2
	Item
	Number of pins				44 pins		48 pins		64 pins		80 pins
	Internal	Flash memory			32 K/48 K/60 K				48 K/60 K/96 K/128 K		60 K/96 K/128 K
	memory
		RAM			2 K/3 K/3 K				3 K/3 K/5 K/7 K		3 K/5 K/7 K
	(bytes)
	Power supply voltage					VDD = 4.0 to 5.5 V when 20 MHz, VDD = 2.7 to 5.5 V when 10 MHz,
									VDD = 1.8 to 5.5 V when 5 MHz
	Minimum instruction execution time						0.1 μs (when 20 MHz, VDD = 4.0 to 5.5 V)
	Clock	Crystal/ceramic							4 to 20 MHz
		Subclock							32.768 kHz
		Internal low-speed							240 kHz (TYP.)
		oscillator
		Internal high-speed						8 MHz (TYP., VDD = 2.7 to 5.5 V)
		oscillator
	Ports	CMOS I/O			33		36		50		66
		CMOS output						1
		N-ch open-drain I/O			3			4
	Timer	16 bits (TM0)				2 ch Note			4 ch
		8 bits (TM5)							2 ch
		8 bits (TMH)							2 ch
		For watch							1 ch
		WDT							1 ch
	Serial	CAN							1 ch
	interface	3-wire CSI				−			1 ch
		LIN-UART							1 ch
		LIN-UART/CSI							1 ch
	10-bit A/D converter				8 ch		9 ch		12 ch		16 ch
	Interrupts	External						8
<R>
		Internal				24			29
	Reset								Provided
			RESET	pin
		POC					1.59 V ±0.15 V (detection voltage is fixed)
		LVI			4.24/4.09/3.93/3.78/3.62/3.47/3.32/3.16/3.01/2.85/2.70/2.55/2.39/2.24/2.08/1.93 V
									(selectable by software)
		WDT							Provided
	Multiplier/divider								Provided
	Clock output/buzzer output								Provided
	Self-programming function								Provided
	On-chip debug function								Provided
	Standby function								HALT/STOP mode
	Operating ambient temperature							TA = −40 to +85°C, −40 to +125°C

Note Since TM01 does not have the following terminal at 78K0/FC2, the function is restricted in part.

μPD78F0881, 78F0882, and 78F0883: TI001, TI011, TO01

μPD78F0884, 78F0885, and 78F0886: TI001

22	User’s Manual U17554EJ4V0UD

CHAPTER 1 OUTLINE

1.6 Block Diagram

TO00/TI010/P01

16-bit timer/

TI000/P00 (LINSEL)

event counter 00

RxD60/P14 (LINSEL)

TO01/TI011/P06

16-bit timer/

TI001/P05

event counter 01

TO02/TI012/P32

16-bit timer/

TI002/P31

event counter 02

TO03/TI013/P132

16-bit timer/

TI003/P131

event counter 03

TOH0/P15

8-bit timer H0

TOH1/P16

8-bit timer H1

TI50/TO50/P17

8-bit timer/

event counter 50

TI51/TO51/P33

8-bit timer/

event counter 51

Internal low-speed

oscillator

Watchdog timer

Watch timer

RxD60/P14

Serial

interface UART60

TxD60/P13

LINSEL

RxD61/P11

Serial

TxD61/P10

interface UART61

SCK10/P10

Serial

SI10/P11

interface CSI10

SO10/P12

SSI11/P05

SO11/P73

Serial interface

SI11/P74

CSI11

SCK11/P75

ANI0/P80-ANI7/P87

12

ANI8/P90-ANI11/P93

A/D converter

AVREF

AVSS

INTP0/P120 (LINSEL)

RxD60/P14 (LINSEL)

INTP1/P30-	4		Interrupt control
INTP4/P33
INTP5/P16
INTP6/P72	2
INTP7/P73

CRxD/P71

CAN

CTxD/P70

	78K/0	Flash
	CPU
		memory
	core
	Bank
	Internal	Internal
	high-speed	expansion
	RAM	RAM
	VDD, VSS,	FLMD0
	EVDD EVSS

Port 0	4	P00, P01, P05, P06
Port 1	8	P10-P17
	4
Port 3		P30-P33
Port 4	4	P40-P43
Port 5	4	P50-P53
	4
Port 6		P60-P63
Port 7	7	P70-P76
Port 8	8	P80-P87
Port 9	4	P90-P93
Port 12	5	P120-P124

Port 13	P130
2	P131, P132
Buzzer output	BUZ/P73

Clock output control PCL/P72

Multiplier/Divider

Power on clear/		POC/LVI
low voltage							EXLVI/P120
		control
indicator
Reset control
System control			RESET
			X1/P121

X2/EXCLK/P122

Internal high-speed

oscillator XT1/P123 XT2/EXCLKS/P124

On-chip debugger

User’s Manual U17554EJ4V0UD

23

CHAPTER 1 OUTLINE

1.7 Outline of Functions

							(1/2)
	Item	μPD78F0887	μPD78F0888		μPD78F0889		μPD78F0890
Internal	Flash memory	48 K	60 K		96 K		128 K
memory	(self-programming
(bytes)	supported)Note
	Bank	−	−		4		6
	High-speed RAMNote		1 K
	Expansion RAMNote	2 K	2 K		4 K		6 K
Memory space			64 KB
High-speed system clock		Crystal/ceramic oscillation (X1), external main system clock input (EXCLK)
(oscillation frequency)		4 to 20 MHz: VDD = 4.0 to 5.5 V, 4 to 10 MHz: VDD = 2.7 to 5.5 V,
		4 to 5 MHz: VDD = 1.8 to 5.5 V
Internal high-speed oscillation		On-chip internal oscillation (8 MHz (TYP.): VDD = 2.7 to 5.5 V)
clock (oscillation frequency)
Internal low-speed oscillation		On-chip internal oscillation (240 kHz (TYP.))
clock (oscillation frequency)
Subsystem clock		Crystal oscillation (XT1), external subsystem clock input (EXCLKS)
(oscillation frequency)		(32.768 kHz: VDD = 1.8 to 5.5 V)
General-purpose registers		8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution		0.1 μs/0.2 μs/0.4 μs/0.8 μs/1.6 μs (high-speed system clock: @ fXP = 20 MHz operation)
time
		0.25 μs/0.5 μs/1.0 μs/2.0 μs/4.0 μs (TYP.) (internal oscillator clock: @ fRH = 8 MHz (TYP.)
		operation)
		122 μs (subsystem clock: when operating at fXT = 32.768 kHz)
Instruction set		• 16-bit operation

•Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

•Bit manipulate (set, reset, test, and Boolean operation)

•BCD adjust, etc.

I/O ports		Total:		55
		CMOS I/O		50
		CMOS output		1
		N-ch open-drain I/O		4
Timers		•	16-bit timer/event counter:	4 channels
		•	8-bit timer/event counter:	2 channels
		•	8-bit timer:	2 channels
		•	Watch timer	1 channel
		•	Watchdog timer:	1 channel
	Timer outputs	8 (PWM output: 4)
Clock output		• 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
			(high-speed system clock: 10 MHz)
		•	32.768 kHz (subsystem clock: 32.768 kHz)
Buzzer output		1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (high-speed system clock: 10 MHz)
A/D converter		10-bit resolution × 12 channels

Note The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM capacity can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS).

24	User’s Manual U17554EJ4V0UD

CHAPTER 1 OUTLINE

(2/2)

Item

μPD78F0887

μPD78F0888

μPD78F0889

μPD78F0890

Serial interface

CAN

1 ch

3-wire CSI

1 ch

LIN-UART

1 ch

LIN-UART/

1 ch

CSI Note

Multiplier/divider

•

16 bit x 16 bit = 32 bit (Multiplication)

•

32 bit ÷ 32 bit = 32 bit

remainder of 16 bits (Division)

<R>

Vectored

Internal

29

interrupt sources

External

8

Reset

• Reset using RESET pin

•

Internal reset by watchdog timer

•

Internal reset by power-on-clear

•

Internal reset by low-voltage detector

On-chip debug function

Provided

Supply voltage

VDD = 1.8 to 5.5 V

Operating ambient temperature

TA = −40 to +85°C, −40 to +125°C

Package

•

64-pin plastic LQFP(10x10)

•

64-pin plastic LQFP(12x12)

Note Select either of the functions of these alternate-function pins.

An outline of the timer is shown below.

16-Bit Timer/

8-Bit Timer/

8-Bit Timers H0

Watch Timer

Watchdog

Event Counters 00 to 03

Event Counters

and H1

Timer

50 and 51

TM00

TM01

TM02

TM03

TM50

TM51

TMH0

TMH1

Operation

Interval timer

1 ch

1 ch

1 ch

1 ch

1 ch

1 ch

1 ch

1 ch

1 channel Note

1 channel

mode

External event counter

1 ch

1 ch

1 ch

1 ch

1 ch

1 ch

−

−

−

−

Function

Timer output

1

1

1

1

1

1

1

1

−

−

PPG output

1

1

1

1

−

−

−

−

−

−

PWM output

−

−

−

−

1

1

1

1

−

−

Pulse width measurement

2

2

2

2

−

−

−

−

−

−

Square-wave output

1

1

1

1

1

1

1

1

−

−

Interrupt source

2

2

2

2

1

1

1

1

1

−

Note In the watch timer, the watch timer function and interval timer function can be used simultaneously.

Remark TM51 and TMH1 can be used in combination as a carrier generator mode.

User’s Manual U17554EJ4V0UD

25

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these power supplies and the pins is shown below.

	Table 2-1. Pin I/O Buffer Power Supplies
Power Supply		Corresponding Pins
AVREF		P80 to P87, P90 to P93
EVDD		Port pins other than P80 to P87, P90 to P93 and P121 to P124
VDD		• P121 to P124
		• Non-port pins

This section explains the names and functions of the pins of the 78K0/FE2.

(1)Port pins

Table 2-2. Port pins (1/2)

Pin Name	I/O	Function	After Reset		Alternate Function
P00	I/O	Port 0.	Input	TI000
		4-bit I/O port.
P01				TI010/TO00
		Input/output can be specified in 1-bit units.
P05				SSI11/TI001
		Use of an on-chip pull-up resistor can be specified by a
P06				TI011/TO01
		software setting.
	I/O	Port 1.	Input
P10				SCK10/TxD61
		8-bit I/O port.
P11				SI10/RxD61
		Input/output can be specified in 1-bit units.
P12				SO10
		Use of an on-chip pull-up resistor can be specified by a
P13				TxD60
		software setting.
P14				RxD60
P15				TOH0
P16				TOH1/INTP5
P17				TI50/TO50
P30	I/O	Port 3.	Input	INTP1
		4-bit I/O port.
P31				INTP2/TI002
		Input/output can be specified in 1-bit units.
P32				INTP3/TI012/TO02
		Use of an on-chip pull-up resistor can be specified by a
P33		software setting.		INTP4/TI51/TO51
P40 to P43	I/O	Port 4.	Input				−
		4-bit I/O port.
		Input/output can be specified in 1-bit units.
		Use of an on-chip pull-up resistor can be specified by a
		software setting.

26	User’s Manual U17554EJ4V0UD

CHAPTER 2 PIN FUNCTIONS

Table 2-2. Port pins (2/2)

Pin Name	I/O		Function		After Reset	Alternate Function
P50 to P53	I/O	Port 5.			Input			−
		4-bit I/O port.
		Input/output can be specified in 1-bit units.
		Use of an on-chip pull-up resistor can be specified by a
		software setting.
P60 to P63	I/O	Port 6.		N-ch open drain I/O port.	Input			−
		4-bit I/O port
		Input/output can be
		specified in 1-bit units.
P70	I/O	Port 7.			Input	CTxD
		7-bit I/O port.
P71						CRxD
		Input/output can be specified in 1-bit units.
P72						PCL/INTP6
		Use of an on-chip pull-up resistor can be specified by a
P73						BUZ/INTP7
		software setting.
P74						SO11
P75						SI11
P76
							SCK11
P80 to P87	I/O	Port 8.			Input	ANI0 to ANI7
		8-bit I/O port.
		Input/output can be specified in 1-bit units.
P90 to P93	I/O	Port 9.			Input	ANI8 to ANI11
		4-bit I/O port.
		Input/output can be specified in 1-bit units.
P120	I/O	Port 12.			Input	INTP0/EXLVI
		5-bit I/O port.
P121						X1
		Only for P120, use of an on-chip pull-up resistor can be
P122		specified by a software setting.				X2/EXCLK
P123						XT1
P124						XT2/EXCLKS
P130	Output	Port 13.			Output			−
		P130 is 1-bit output-only port.
P131	I/O				Input
		P131 and P132 are 2-bit I/O port.
P132
		P131 and P132 use of an on-chip pull-up resistor can be
		specified by a software setting.

User’s Manual U17554EJ4V0UD

27

CHAPTER 2 PIN FUNCTIONS

(2)Non-port pins

Table 2-3. Non-port pins (1/2)

Pin Name

I/O

Function

After Reset

Alternate Function

INTP0

Input

External interrupt request input for which the valid edge (rising

Input

P120/EXLVI

edge, falling edge, or both rising and falling edges) can be

INTP1

P30

specified

INTP2

P31/TI002

INTP3

P32/TI012/TO02

INTP4

P33/TI51/TO51

INTP5

P16/TOH1

INTP6

P72/PCL

INTP7

P73/BUZ

SI10

Input

Serial data input to serial interface

Input

P11/RxD61

SI11

P75

SO10

Output

Serial data output from serial interface

Input

P12

SO11

P74

I/O

Clock input/output for serial interface

Input

SCK10

P10/TxD61

P76

SCK11

SSI11

Input

Serial interface chip select input

Input

P05/TI001

RxD60

Input

Serial data input to asynchronous serial interface

Input

P14

RxD61

P11/SI10

TxD60

Output

Serial data output from asynchronous serial interface

Input

P13

TxD61

P10/SCK10

TI000

Input

External count clock input to 16-bit timer/event counter 00

Input

P00

Capture trigger input to capture registers (CR000, CR010) of

16-bit timer/event counter 00

External count clock input to 16-bit timer/event counter 01

TI001

P05/SSI11

Capture trigger input to capture registers (CR001, CR011) of

16-bit timer/event counter 01

TI002

External count clock input to 16-bit timer/event counter 02

P31/INTP2

Capture trigger input to capture registers (CR002, CR012) of

16-bit timer/event counter 02

TI003

External count clock input to 16-bit timer/event counter 03

P131

Capture trigger input to capture registers (CR003, CR013) of

16-bit timer/event counter 03

TI010

Capture trigger input to capture register (CR000) of 16-bit

P01/TO00

timer/event counter 00

TI011

Capture trigger input to capture register (CR001) of 16-bit

P06/TO01

timer/event counter 01

TI012

Capture trigger input to capture register (CR002) of 16-bit

P32/TO02/INTP3

timer/event counter 02

TI013

Capture trigger input to capture register (CR003) of 16-bit

P132/TO03

timer/event counter 03

TO00

Output

16-bit timer/event counter 00 output

Input

P01/TI010

TO01

16-bit timer/event counter 01 output

P06/TI011

TO02

16-bit timer/event counter 02 output

P32/TI012/INTP3

28	User’s Manual U17554EJ4V0UD

CHAPTER 2 PIN FUNCTIONS

Table 2-3. Non-port pins (2/2)

Pin Name	I/O	Function	After Reset	Alternate Function
TO03	Output	16-bit timer/event counter 03 output	Input	P132/TI013
TI50	Input	External count clock input to 8-bit timer/event counter 50	Input	P17/TO50
TI51		External count clock input to 8-bit timer/event counter 51		P33/TO51/INTP4
TO50	Output	8-bit timer/event counter 50 output	Input	P17/TI50
TO51		8-bit timer/event counter 51 output		P33/TI51/INTP4
TOH0		8-bit timer H0 output		P15
TOH1		8-bit timer H1 output		P16/INTP5
PCL	Output	Clock output (for trimming of high-speed system clock,	Input	P72/INTP6
		subsystem clock)
BUZ	Output	Buzzer output	Input	P73/INTP7
ANI0 to ANI11	Input	A/D converter analog input	Input	P80 to P87
				P90 to P93
CTxD	Input	CAN transmit data output	Input	P70
CRxD	Output	CAN receive data input	Input	P71
AVREF	Input	A/D converter reference voltage input and positive power	−	−
		supply for port 2
AVSS	−	A/D converter ground potential. Make the same potential as	−	−
		EVSS or VSS.
RESET	Input	System reset input	−	−
X1	Input	Connecting resonator for high-speed system clock	Input	P121
X2	−		Input	P122/EXCLK
XT1	Input	Connecting resonator for subsystem clock	Input	P123
XT2	−		Input	P124/EXCLKS
EXCLK	Input	External clock input for main system clock	Input	P122/X2
EXCLKS	Input	External clock input for subsystem clock	Input	P124/XT2
EXLVI	Input	Potential input for external low-voltage detection	Input	P120/INTP0
VDD	−	Positive power supply (except for ports)	−	−
EVDD	−	Positive power supply for ports	−	−
VSS	−	Ground potential (except for ports)	−	−
EVSS	−	Ground potential for ports	−	−
FLMD0	−	Flash memory programming mode setting.	−	−
REGC	−

User’s Manual U17554EJ4V0UD

29

CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions

2.2.1 P00, P01, P05, P06 (port 0)

P00, P01, P05 and P06 function as a 4-bit I/O port. These pins also function as timer I/O and serial interface chip select input.

The following operation modes can be specified in 1-bit units.

(1)Port mode

P00, P01, P05 and P06 function as 4-bit I/O port. P00, P01, P05 and P06 can be set to input or output in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).

(2)Control mode

P00, P01, P05 and P06 function as timer I/O, and serial interface chip select input.

(a)TI000, TI001

These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit timer/event counters 00 and 01.

(b)TI010, TI011

These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit timer/event counters 00 and 01.

(c)TO00, TO01

These are timer output pins.

(d)SSI11

This is the serial interface chip select input pin.

30	User’s Manual U17554EJ4V0UD