μ
μ
User’s Manual
PD78F0714
8-Bit Single-Chip Microcontroller
PD78F0714
Document No. U16928EJ2V0UD00 (2nd edition)
Date Published September 2007 NS
©
Printed in Japan
2004
[MEMO]
2
User’s Manual U16928EJ2V0UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
IL
(MAX) and VIH (MIN) due to noise, etc., the device may
IL
(MAX) and
DD
or GND
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U16928EJ2V0UD
3
EEPROM is a trademark of NEC Electronics Corporation.
Windows, Windows NT, and Windows XP are registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
®
SuperFlash
is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
4
User’s Manual U16928EJ2V0UD
Caution: This product uses SuperFlash
®
technology licensed from Silicon Storage Technology, inc.
•
The information in this document is current as of August, 2007. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
•
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
•
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8 E 02 . 11-1
User’s Manual U16928EJ2V0UD
5
INTRODUCTION
Readers This manual is intended for user engineers who wish to understand the functions of the
μ
PD78F0714 and design and develop application systems and programs for this
device.
The target product is as follows.
μ
PD78F0714
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text.
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
Decimal
Hexadecimal
μ
PD78F0714 manual is separated into two parts: this manual and the instructions
edition (common to the 78K/0 Series).
μ
PD78F0714
User’s Manual
(This Manual)
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• Electrical specifications
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major
revised points. The revised points can be easily searched by copying an “<R>” in
the PDF file and specifying it in the “Find what:” field.
• How to interpret the register format:
→ For a bit number enclosed in brackets, the bit name is defined as a reserved word
in the assembler, and is already defined in the header file named sfrbit.h in the C
compiler.
• To check the details of a register when you know the register name.
→ See APPENDIX B REGISTER INDEX.
• To know details of the 78K/0 Series instructions.
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
78K/0 Series
User’s Manual
Instructions
• CPU functions
• Instruction set
• Explanation of each instruction
...
×××× or ××××B
...
××××
...
××××H
6
User’s Manual U16928EJ2V0UD
<R>
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
μ
PD78F0714 User’s Manual
78K/0 Series Instructions User’s Manual U12326E
This manual
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
<R>
RA78K0 Ver. 3.80 Assembler Package
ID78K0-QB Ver. 2.94 Integrated Debugger Operation U18330E
PM+ Ver. 5.20 U16934E
Operation U17199E
Language U17198E
Structured Assembly Language U17197E
Operation U17201E CC78K0 Ver. 3.70 C Compiler
Language U17200E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name Document No.
QB-780714 In-Circuit Emulator U17081E
QB-78K0MINI On-Chip Debug Emulator U17029E
QB-78K0MINI2 On-Chip Debug Emulator with Programming Function U18371E
Documents Related to Flash Memory Programming
Document Name Document No.
PG-FP4 Flash Memory Programmer User’s Manual U15260E
Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages −
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
X13769X
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U16928EJ2V0UD
7
CONTENTS
CHAPTER 1 OUTLINE............................................................................................................................. 16
1.1 Features ..................................................................................................................................... 16
1.2 Applications .............................................................................................................................. 17
1.3 Ordering Information ................................................................................................................ 17
1.4 Pin Configuration (Top View)................................................................................................... 18
1.5 Block Diagram........................................................................................................................... 20
1.6 Outline of Functions ................................................................................................................. 21
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 23
2.1 Pin Function List....................................................................................................................... 23
2.2 Description of Pin Functions................................................................................................... 27
2.2.1 P00 to P03 (port 0)....................................................................................................................... 27
2.2.2 P10 to P17 (port 1)....................................................................................................................... 27
2.2.3 P20 to P27 (port 2)....................................................................................................................... 28
2.2.4 P30 to P33 (port 3)....................................................................................................................... 28
2.2.5 P40 to P47 (port 4)....................................................................................................................... 29
2.2.6 P50 to P57 (port 5)....................................................................................................................... 29
2.2.7 P64 to P67 (port 6)....................................................................................................................... 30
2.2.8 P70 to P73 (port 7)....................................................................................................................... 30
2.2.9 TW0TO0/RTP10 to TW0TO5/RTP15........................................................................................... 30
2.2.10 AVREF............................................................................................................................................ 30
2.2.11 AVSS ............................................................................................................................................. 30
2.2.12 RESET ......................................................................................................................................... 30
2.2.13 X1 and X2..................................................................................................................................... 30
2.2.14 VDD and EVDD ............................................................................................................................... 30
2.2.15 VSS and EVSS................................................................................................................................31
2.2.16 FLMD0 ......................................................................................................................................... 31
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................ 32
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 34
3.1 Memory Space........................................................................................................................... 34
3.1.1 Internal program memory space...................................................................................................35
3.1.2 Internal data memory space......................................................................................................... 36
3.1.3 Special function register (SFR) area ............................................................................................36
3.1.4 Data memory addressing ............................................................................................................. 36
3.2 Processor Registers ................................................................................................................. 38
3.2.1 Control registers........................................................................................................................... 38
3.2.2 General-purpose registers............................................................................................................ 42
3.2.3 Special function registers (SFRs)................................................................................................. 43
3.3 Instruction Address Addressing ............................................................................................. 49
3.3.1 Relative addressing...................................................................................................................... 49
3.3.2 Immediate addressing.................................................................................................................. 50
3.3.3 Table indirect addressing ............................................................................................................. 51
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User’s Manual U16928EJ2V0UD
3.3.4 Register addressing ......................................................................................................................52
3.4 Operand Address Addressing................................................................................................. 53
3.4.1 Implied addressing........................................................................................................................53
3.4.2 Register addressing ......................................................................................................................54
3.4.3 Direct addressing ..........................................................................................................................55
3.4.4 Short direct addressing .................................................................................................................56
3.4.5 Special function register (SFR) addressing................................................................................... 57
3.4.6 Register indirect addressing..........................................................................................................58
3.4.7 Based addressing .........................................................................................................................59
3.4.8 Based indexed addressing............................................................................................................60
3.4.9 Stack addressing...........................................................................................................................61
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 62
4.1 Port Functions .......................................................................................................................... 62
4.2 Port Configuration .................................................................................................................... 64
4.2.1 Port 0 ............................................................................................................................................65
4.2.2 Port 1 ............................................................................................................................................66
4.2.3 Port 2 ............................................................................................................................................70
4.2.4 Port 3 ............................................................................................................................................71
4.2.5 Port 4 ............................................................................................................................................73
4.2.6 Port 5 ............................................................................................................................................74
4.2.7 Port 6 ............................................................................................................................................76
4.2.8 Port 7 ............................................................................................................................................77
4.3 Registers Controlling Port Function....................................................................................... 78
4.4 Port Function Operations ........................................................................................................82
4.4.1 Writing to I/O port..........................................................................................................................82
4.4.2 Reading from I/O port....................................................................................................................82
4.4.3 Operations on I/O port...................................................................................................................82
4.5 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) .................................. 83
CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 84
5.1 Functions of Clock Generator ................................................................................................. 84
5.2 Configuration of Clock Generator........................................................................................... 84
5.3 Registers Controlling Clock Generator .................................................................................. 86
5.4 System Clock Oscillator .......................................................................................................... 93
5.4.1 X1 oscillator ..................................................................................................................................93
5.4.2 Examples of Incorrect Resonator Connection...............................................................................94
5.4.3 Internal oscillator...........................................................................................................................95
5.4.4 Prescaler.......................................................................................................................................95
5.5 Clock Generator Operation...................................................................................................... 96
5.6 Time Required to Switch Between Internal Oscillation Clock and X1 Input Clock.......... 101
5.7 Time Required for CPU Clock Switchover ........................................................................... 102
5.8 Clock Switching Flowchart and Register Setting................................................................ 103
5.8.1 Switching from internal oscillation clock to X1 input clock...........................................................103
5.8.2 Switching from X1 input clock to internal oscillation clock...........................................................104
5.8.3 Register settings .........................................................................................................................105
User’s Manual U16928EJ2V0UD
9
CHAPTER 6 10-BIT INVERTER CONTROL TIMER............................................................................. 106
6.1 Outline of 10-Bit Inverter Control Timer ............................................................................... 106
6.2 Function of 10-Bit Inverter Control Timer ............................................................................ 106
6.3 Configuration of 10-Bit Inverter Control Timer.................................................................... 106
6.4 Registers Controlling 10-Bit Inverter Control Timer ........................................................... 110
6.5 Registers Controlling 10-Bit Inverter Control Timer ........................................................... 115
CHAPTER 7 16-BIT UP/DOWN COUNTER ITENC20 .......................................................................... 122
7.1 Functions of 16-Bit Up/Down Counter ITENC20.................................................................. 122
7.2 Configuration of 16-bit Up/Down Counter ITENC20............................................................ 124
7.3 16-Bit Up/down Counter ITENC20 Control Registers.......................................................... 131
7.4 16-Bit Up/down Counter ITENC20 Operations ..................................................................... 139
7.4.1 Basic operation........................................................................................................................... 139
7.4.2 Operation in general-purpose timer mode.................................................................................. 140
7.4.3 Operation in UDC mode............................................................................................................. 143
7.5 Internal Operation of 16-Bit Up/down Counter ITENC20 .................................................... 149
7.5.1 Clearing of count value in UDC mode B..................................................................................... 149
7.5.2 Clearing of count value upon occurrence of compare match...................................................... 150
7.5.3 Transfer operation...................................................................................................................... 150
7.5.4 Interrupt signal output upon compare match.............................................................................. 151
7.5.5 IT20UBD flag (bit 0 of IT20STS register) operation.................................................................... 151
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 00 ........................................................................... 152
8.1 Functions of 16-Bit Timer/Event Counter 00........................................................................ 152
8.2 Configuration of 16-Bit Timer/Event Counter 00 ................................................................. 153
8.3 Registers Controlling 16-Bit Timer/Event Counter 00......................................................... 157
8.4 Operation of 16-Bit Timer/Event Counter 00........................................................................ 163
8.4.1 Interval timer operation............................................................................................................... 163
8.4.2 PPG output operations............................................................................................................... 166
8.4.3 Pulse width measurement operations ........................................................................................ 169
8.4.4 External event counter operation................................................................................................ 177
8.4.5 Square-wave output operation ................................................................................................... 180
8.4.6 One-shot pulse output operation ................................................................................................ 182
8.5 Cautions for 16-Bit Timer/Event Counter 00 ........................................................................ 187
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 190
9.1 Functions of 8-Bit Timer/Event Counters 50 and 51 ........................................................... 190
9.2 Configuration of 8-Bit Timer/Event Counters 50 and 51..................................................... 192
9.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................ 194
9.4 Operations of 8-Bit Timer/Event Counters 50 and 51 ......................................................... 199
9.4.1 Operation as interval timer ......................................................................................................... 199
9.4.2 Operation as external event counter .......................................................................................... 201
9.4.3 Square-wave output operation ................................................................................................... 202
9.4.4 PWM output operation................................................................................................................ 203
9.5 Cautions for 8-Bit Timer/Event Counters 50 and 51............................................................ 207
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User’s Manual U16928EJ2V0UD
CHAPTER 10 8-BIT TIMER H0 ........................................................................................................... 208
10.1 Functions of 8-Bit Timer H0................................................................................................... 208
10.2 Configuration of 8-Bit Timer H0 ............................................................................................ 208
10.3 Registers Controlling 8-Bit Timer H0.................................................................................... 211
10.4 Operation of 8-Bit Timer H0................................................................................................... 214
10.4.1 Operation as interval timer/square-wave output..........................................................................214
10.4.2 Operation as PWM output mode.................................................................................................217
CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 223
11.1 Functions of Watchdog Timer............................................................................................... 223
11.2 Configuration of Watchdog Timer ........................................................................................ 225
11.3 Registers Controlling Watchdog Timer................................................................................ 226
11.4 Operation of Watchdog Timer............................................................................................... 228
11.4.1 Watchdog timer operation when “Internal oscillator cannot be stopped” is selected by option byte ...228
11.4.2 Watchdog timer operation when “internal oscillator can be stopped by software” is selected by
option byte ..................................................................................................................................229
11.4.3 Watchdog timer operation in STOP mode (when “Internal oscillator can be stopped by software” is
selected by option byte) ..............................................................................................................230
11.4.4 Watchdog timer operation in HALT mode (when “Internal oscillator can be stopped by software” is
selected by option byte) ..............................................................................................................232
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 233
12.1 Functions of Clock Output/Buzzer Output Controller ........................................................ 233
12.2 Configuration of Clock Output/Buzzer Output Controller.................................................. 234
12.3 Register Controlling Clock Output/Buzzer Output Controller ........................................... 234
12.4 Clock Output/Buzzer Output Controller Operations........................................................... 237
12.4.1 Clock output operation ................................................................................................................237
12.4.2 Operation as buzzer output.........................................................................................................237
CHAPTER 13 REAL-TIME OUTPUT PORT ....................................................................................... 238
13.1 Function of Real-Time Output Port....................................................................................... 238
13.2 Configuration of Real-Time Output Port .............................................................................. 238
13.3 Registers Controlling Real-Time Output Port...................................................................... 243
13.4 Operation of Real-Time Output Port..................................................................................... 249
13.5 Using Real-Time Output Port ................................................................................................ 259
13.6 Notes on Real-Time Output Port........................................................................................... 260
CHAPTER 14 DC INVERTER CONTROL FUNCTION ......................................................................... 261
CHAPTER 15 A/D CONVERTER ......................................................................................................... 262
15.1 Functions of A/D Converter................................................................................................... 262
15.2 Configuration of A/D Converter ............................................................................................ 263
User’s Manual U16928EJ2V0UD
11
15.3
Registers Used in A/D Converter .......................................................................................... 265
15.4 Relationship Between Input Voltage and A/D Conversion Results................................... 272
15.5 A/D Converter Operations...................................................................................................... 273
15.5.1 Basic operations of A/D converter .............................................................................................. 273
15.5.2 Trigger modes ............................................................................................................................ 275
15.5.3 Operation modes........................................................................................................................ 276
15.5.4 Power-fail monitoring function .................................................................................................... 279
15.6 How to Read A/D Converter Characteristics Table ............................................................. 283
15.7 Cautions for A/D Converter.................................................................................................... 285
CHAPTER 16 SERIAL INTERFACE UART00 .................................................................................... 288
16.1 Functions of Serial Interface UART00 .................................................................................. 288
16.2 Configuration of Serial Interface UART00............................................................................ 289
16.3 Registers Controlling Serial Interface UART00 ................................................................... 292
16.4 Operation of Serial Interface UART00................................................................................... 297
16.4.1 Operation stop mode.................................................................................................................. 297
16.4.2 Asynchronous serial interface (UART) mode ............................................................................. 298
16.4.3 Dedicated baud rate generator................................................................................................... 304
CHAPTER 17 SERIAL INTERFACE CSI10 ........................................................................................ 309
17.1 Functions of Serial Interface CSI10 ...................................................................................... 309
17.2 Configuration of Serial Interface CSI10 ................................................................................ 310
17.3 Registers Controlling Serial Interface CSI10 ....................................................................... 312
17.4 Operation of Serial Interface CSI10....................................................................................... 316
17.4.1 Operation stop mode.................................................................................................................. 316
17.4.2 3-wire serial I/O mode ................................................................................................................ 317
CHAPTER 18 MULTIPLIER/DIVIDER ................................................................................................... 325
18.1 Functions of Multiplier/Divider .............................................................................................. 325
18.2 Configuration of Multiplier/Divider........................................................................................ 325
18.3 Register Controlling Multiplier/Divider ................................................................................. 330
18.4 Operations of Multiplier/Divider ............................................................................................ 331
18.4.1 Multiplication operation............................................................................................................... 331
18.4.2 Division operation....................................................................................................................... 333
CHAPTER 19 INTERRUPT FUNCTIONS............................................................................................. 335
19.1 Interrupt Function Types........................................................................................................ 335
19.2 Interrupt Sources and Configuration.................................................................................... 335
19.3 Registers Controlling Interrupt Functions ........................................................................... 339
19.4 Interrupt Servicing Operations.............................................................................................. 347
19.4.1 Non-maskable interrupt request acknowledgment operation...................................................... 347
19.4.2 Maskable interrupt request acknowledgement ........................................................................... 349
19.4.3 Software interrupt request acknowledgment .............................................................................. 351
19.4.4 Multiple interrupt servicing.......................................................................................................... 352
19.4.5 Interrupt request hold ................................................................................................................. 355
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CHAPTER 20 STANDBY FUNCTION .................................................................................................. 356
20.1 Standby Function and Configuration ................................................................................... 356
20.1.1 Standby function .........................................................................................................................356
20.1.2 Registers controlling standby function.........................................................................................358
20.2 Standby Function Operation ................................................................................................. 360
20.2.1 HALT mode.................................................................................................................................360
20.2.2 STOP mode ................................................................................................................................364
CHAPTER 21 RESET FUNCTION ....................................................................................................... 368
21.1 Register for Confirming Reset Source ................................................................................. 375
CHAPTER 22 POWER-ON-CLEAR CIRCUIT ..................................................................................... 376
22.1 Functions of Power-on-Clear Circuit.................................................................................... 376
22.2 Configuration of Power-on-Clear Circuit ............................................................................. 377
22.3 Operation of Power-on-Clear Circuit .................................................................................... 377
22.4 Cautions for Power-on-Clear Circuit .................................................................................... 378
CHAPTER 23 LOW-VOLTAGE DETECTOR ....................................................................................... 380
23.1 Functions of Low-Voltage Detector...................................................................................... 380
23.2 Configuration of Low-Voltage Detector................................................................................ 380
23.3 Registers Controlling Low-Voltage Detector....................................................................... 381
23.4 Operation of Low-Voltage Detector ...................................................................................... 382
23.5 Cautions for Low-Voltage Detector ...................................................................................... 386
CHAPTER 24 OPTION BYTES ............................................................................................................ 390
CHAPTER 25 FLASH MEMORY.......................................................................................................... 391
25.1 Internal Memory Size Switching Register ............................................................................ 391
25.2 Writing with Flash Memory Programmer ............................................................................. 392
25.3 Programming Environment ................................................................................................... 396
25.4 Communication Mode ............................................................................................................ 396
25.5 Processing of Pins on Board ................................................................................................ 399
25.5.1 FLMD0 pin ..................................................................................................................................399
25.5.2 FLMD1 pin ..................................................................................................................................399
25.5.3 Serial interface pins.....................................................................................................................400
25.5.4 RESET pin ..................................................................................................................................402
25.5.5 Port pins......................................................................................................................................402
25.5.6 Other signal pins .........................................................................................................................402
25.5.7 Power supply ..............................................................................................................................402
25.6 Programming Method ............................................................................................................ 403
25.6.1 Controlling flash memory ............................................................................................................403
25.6.2 Flash memory programming mode .............................................................................................403
User’s Manual U16928EJ2V0UD
13
25.6.3 Selecting communication mode.................................................................................................. 404
25.6.4 Communication commands........................................................................................................ 405
25.7 Flash Memory Programming by Self-Writing....................................................................... 406
25.7.1 Registers used for self-programming function ............................................................................ 407
25.8 Boot Swap Function ............................................................................................................... 411
25.8.1 Outline of boot swap function ..................................................................................................... 411
25.8.2 Memory map and boot area ....................................................................................................... 412
CHAPTER 26 ON-CHIP DEBUG FUNCTION ..................................................................................... 413
CHAPTER 27 INSTRUCTION SET....................................................................................................... 414
27.1 Conventions Used in Operation List..................................................................................... 414
27.1.1 Operand identifiers and specification methods........................................................................... 414
27.1.2 Description of operation column ................................................................................................. 415
27.1.3 Description of flag operation column .......................................................................................... 415
27.2 Operation List.......................................................................................................................... 416
27.3 Instructions Listed by Addressing Type .............................................................................. 424
CHAPTER 28 ELECTRICAL SPECIFICATIONS ................................................................................. 427
CHAPTER 29 PACKAGE DRAWINGS ................................................................................................ 440
CHAPTER 30 CAUTIONS FOR WAIT................................................................................................. 441
30.1 Cautions for Wait .................................................................................................................... 441
30.2 Peripheral Hardware That Generates Wait........................................................................... 442
30.3 Example of Wait Occurrence ................................................................................................. 443
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 444
A.1 Software Package...................................................................................................................... 448
A.2 Language Processing Software............................................................................................... 448
A.3 Control Software........................................................................................................................ 449
A.4 Flash Memory Programming Tools ......................................................................................... 450
A.4.1 When using flash memory programmer PG-FP5, FL-PR5, PG-FP4, FL-PR4, and PG-FPL ......... 450
A.4.2 When using on-chip debug emulator with programming function QB-MINI2 ................................. 450
A.5 Debugging Tools (Hardware)................................................................................................. 451
A.5.1 When using in-circuit emulator QB-780714 ................................................................................... 451
A.5.2 When using on-chip debug emulator QB-78K0MINI...................................................................... 451
A.5.3 When using on-chip debug emulator with programming function QB-MINI2 ................................. 452
A.6 Debugging Tools (Software)..................................................................................................... 452
14
User’s Manual U16928EJ2V0UD
APPENDIX B REGISTER INDEX ......................................................................................................... 453
B.1 Register Index (In Alphabetical Order with Respect to Register Names)......................... 453
B.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................ 457
APPENDIX C REVISION HISTORY ..................................................................................................... 461
C.1 Major Revisions in This Edition............................................................................................... 461
User’s Manual U16928EJ2V0UD
15
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.1
clock) to low-speed (8.33
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ On-chip multiplier/divider
• 16 bits × 16 bits = 32 bits (multiplication)
• 32 bits ÷ 16 bits = 32 bits, 16 bits remainder (division)
{ ROM, RAM capacities
μ
s: @ 240 kHz operation with internal oscillation clock)
μ
s: @ 20 MHz operation with X1 input
Part Number
μ
PD78F0714
Item
Flash memory 32 KB 1024 bytes
Program Memory
(ROM)
{ On-chip single-power-supply flash memory
{ Self-programming (with boot swap function)
{ On-chip debug function
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ Short startup is possible via the CPU default start using the internal oscillator
{ On-chip watchdog timer (operable with internal oscillation clock)
{ On-chip clock output/buzzer output controller00
{ On-chip real-time output ports
{ I/O ports: 48
{ Timer: 7 channels
{ Serial interface: 2 channels (UART: 1 channel, CSI: 1 channel)
{ 10-bit resolution A/D converter: 8 channels
{ Supply voltage: V
{ Operating ambient temperature: T
DD = 4.0 to 5.5 V
A = −40 to +85°C
Data Memory
(Internal High-Speed RAM)
16
User’s Manual U16928EJ2V0UD
CHAPTER 1 OUTLINE
<R>
1.2 Applications
{ Household electrical appliances
• Refrigerator
• Dish washer
• Washing machine, Dryer
• Outdoor air conditioner units
• Microwave ovens, electric rice cookers
{ Industrial equipment
• Pumps
1.3 Ordering Information
Part Number Package
μ
PD78F0714GK-9ET 64-pin plastic TQFP (fine pitch) (12 × 12)
User’s Manual U16928EJ2V0UD
17
1.4 Pin Configuration (Top View)
• 64-pin plastic TQFP (fine pitch) (12 × 12)
CHAPTER 1 OUTLINE
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P73
P72
P71
P70
P67
P66
P65
P64
AVREF
AVSS
FLMD0
VDD
VSS
X1
X2
RESET
ADTRG/INTP3/P03
INTP2/P02
INTP1/P01
TW0TOFFP/INTP0/P00
BUZ/P30
PCL/P31
P32
P33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
646362616059585756555453525150
171819202122232425262728293031
SS
DD
EV
EV
49
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P47/RTP07
P46/RTP06
P45/RTP05
P44/RTP04
P43/RTP03
P42/RTP02
P41/RTP01
P40/RTP00
P17/SO10/FLMD1
P16/SI10
P15/SCK10
P14/TxD00
P13/RxD00
P12
P11
P10
Caution Connect the AV
18
SS pin to VSS.
P50/TI50/TO50
P51/TI51/TO51
P54/TI001/TO00
P53/TI000/INTP5
P52/TOH0/INTP4
P55/TIT20IUD/INTP6
P56/TIT20CUD/TIT20CC0/INTP7
P57/TIT20CLR/TIT20CC1/TIT20TO
User’s Manual U16928EJ2V0UD
TW0TO0/RTP10
TW0TO1/RTP11
TW0TO2/RTP12
TW0TO3/RTP13
TW0TO4/RTP14
TW0TO5/RTP15
CHAPTER 1 OUTLINE
Pin Identification
ADTRG: A/D trigger input
ANI0 to ANI7: Analog input
AV
REF: Analog reference voltage
AVSS: Analog ground
BUZ: Buzzer output
EV
DD: Power supply for port
EVSS: Ground for port
FLMD0, FLMD1: Flash programming mode
INTP0 to INTP7: External interrupt input
P00 to P03: Port 0
P10 to P17: Port 1
P20 to P27: Port 2
P30 to P33: Port 3
P40 to P47: Port 4
P50 to P57: Port 5
P64 to P67: Port 6
P70 to P73: Port 7
PCL: Programmable clock output
RESET: Reset
RTP00 to RTP07: Real-time output port
RxD00: Receive data
SCK10 Serial clock input/output
SI10: Serial data input
SO10: Serial data output
TI000, TI001: Timer input
TI50, TI51: Timer input
TIT20CLR: Up/down counter clear
TIT20CUD: Up/down counter clock select
TIT20CC0, TIT20CC1: Up/down counter capture input
TIT20IUD: Up/down counter clock
TIT20TO: Up/down counter output
TO00: Timer output
TO50, TO51: Timer output
TOH0: Timer output
TW0TO0 to TW0TO5: Timer output
TW0TOFFP: Timer output off
TxD00: Transmit data
V
DD: Power supply
VSS: Ground
X1, X2: Crystal oscillator (X1 input clock)
RTP10 to RTP15: Real-time output port
User’s Manual U16928EJ2V0UD
19
1.5 Block Diagram
CHAPTER 1 OUTLINE
TW0TO0 to TW0TO5
TW0TOFFP/P00
TIT20CLR/TIT20CC1/
TIT20CUD/TIT20CC0/P56
TIT20TO/P57
TIT20IUD/P55
TO00/TI001/P54
TI000/P53
TI50/TO50/P50
TI51/TO51/P51
TOH0/P52
RTP00/P40 to RTP07/P47
RTP10 to RTP15
10-bit INVERTER
6
CONTROL TIMER
W0
16-bit UP/DOWN
COUNTER
ITENC20
16-bit TIMER/
EVENT COUNTER 00
8-bit TIMER/
EVENT COUNTER 50
8-bit TIMER/
EVENT COUNTER 51
8-bit TIMER
WATCH TIMER
WATCHDOG TIMER
8
REAL-TIME
OUTPUT PORT
6
H0
78K/0
CPU
CORE
FLASH
MEMORY
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
RESET CONTROL
4
P00 to P03
8
P10 to P17
8
P20 to P27
4
P30 to P33
8
P40 to P47
8
P50 to P57
4
P64 to P67
4
P70 to P73
BUZ/P30
PCL/P31
POC/LVI
CONTROL
RxD00/P13
TxD00/P14
SI10/P16
SO10/P17
SCK10/P15
ADTRG/P03
ANI0/P20 to
ANI7/P27
AV
REF
AV
INTP0/P00 to
INTP3/P03
INTP4/P52,
INTP5/P53
INTP6/P55,
INTP7/P56
INTERNAL
HIGH-SPEED
RAM
INTERNAL
OSCILLATOR
SERIAL
INTERFACE UART0
SERIAL
SYSTEM
CONTROL
RESET
X1
X2
INTERFACE CSI10
8
A/D CONVERTER
SS
4
INTERRUPT
2
CONTROL
2
MULTIPLIER &
DIVIDER
VDD,
EV
VSS,
FLMD0,
SS
DD
EV
FLMD1
20
User’s Manual U16928EJ2V0UD
CHAPTER 1 OUTLINE
1.6 Outline of Functions
Item
Flash memory (self-
memory
programming supported)
High-speed RAM 1 KB
Memory space 64 KB
X1 input clock (oscillation frequency) Ceramic/crystal/external clock oscillation
Internal oscillation clock (oscillation
frequency)
General-purpose registers
Minimum instruction execution time
Instruction set
I/O ports
32 KB Internal
[20 MHz (V
DD = 4.0 to 5.5 V)]
Internal oscillator (240 kHz (TYP.))
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
0.1 μs/0.2 μs/0.4 μs/0.8 μs/1.6 μs (X1 input clock: @ fXP = 20 MHz operation)
8.3 μs/16.6 μs/33.2 μs/66.4 μs/132.8 μs (TYP.) ( Internal oscillation clock: @ fR = 240
kHz (TYP.) operation)
• 16-bit operation • Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation) • BCD adjust, etc.
Total: 48
μ
PD78F0714
<R>
CMOS I/O 40
CMOS input 8
Timers • 10-bit inverter control timer: 1 channel
• 16-bit up/down counter: 1 channel
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• 8-bit timer: 1 channel
• Watchdog timer: 1 channel
Timer outputs 11 (inverter control output: 6)
Clock output 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz, 20MHz
(X1 input clock: 20 MHz)
Buzzer output 2.44 kHz, 4.88 kHz, 9.77 kHz, 19.5kHz (X1 input clock: 20 MHz)
Real-time output ports
• 8 bits × 1 or 4 bits × 2
• 6 bits × 1 or 4 bits × 2
A/D converter
10-bit resolution × 8 channels
Serial interface • UART mode: 1 channel
• 3-wire serial I/O mode: 1 channel
Multiplier/divider
• 16 bits × 16 bits = 32 bits (multiplication)
• 32 bits ÷ 16 bits = 32 bits remainder of 16 bits (division)
Internal Non-maskable: 1, Maskable: 19 Vectored
interrupt sources
Reset
External 8
• Reset using RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
Supply voltage VDD = 4.0 to 5.5 V
T
Operating ambient temperature
Package
A = −40 to +85°C
64-pin plastic TQFP (fine pitch) (12 × 12)
User’s Manual U16928EJ2V0UD
21
An outline of the timer is shown below.
10-Bit Inverter
Control Timer
Operation
mode
Function
Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel
External
event counter
Timer output 6 outputs 1 output 1 output 1 output 1 output 1 output
PPG output
PWM output 6 outputs 1 output
Pulse width
measurement
Square-wave
output
Watchdog
Timer
Interrupt
source
−
− −
− −
−
− − − − − −
4 4 2 1 1 1
CHAPTER 1 OUTLINE
16-Bit Up/down
Counter
ITENC20
1 channel 1 channel 1 channel 1 channel
1 output 1 output 1 output 1 output 1 output
16-Bit Timer/
Event Counter
00
1 output
−
2 inputs
8-Bit Timer/
Event Counters
50 and 51
TM50 TM51
− − − −
1 output 1 output 1 output
− − − −
8-Bit Timer
Watchdog
H0
− −
Timer
1 channel
−
−
−
−
−
22
User’s Manual U16928EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these
power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P20 to P27
EVDD Port pins other than P20 to P27
VDD Pins other than port pins
(1) Port pins (1/2)
Pin Name I/O Function After Reset Alternate Function
P00 INTP0/TW0TOFFP
P01 INTP1
P02 INTP2
P03
P10
P11
P12
P13 RxD00
P14 TxD00
P15 SCK10
P16 SI10
P17
P20 to P27 Input Port 2.
P30 BUZ
P31 PCL
P32
P33
P40 to P47 I/O Port 4.
I/O Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
I/O Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
8-bit input-only port.
I/O Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
INTP3/ADTRG
Input
SO10/FLMD1
Input ANI0 to ANI7
Input
Input RTP00 to RTP07
−
−
−
−
−
User’s Manual U16928EJ2V0UD
23
CHAPTER 2 PIN FUNCTIONS
(1) Port pins (2/2)
Pin Name I/O Function After Reset Alternate Function
P50 TI50/TO50
P51 TI51/TO51
P52 TOH0/INTP4
P53 TI000/INTP5
24
User’s Manual U16928EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins (1/2)
Pin Name I/O Function After Reset Alternate Function
INTP0 P00/TW0TOFFP
INTP1 P01
INTP2 P02
INTP3 P03/ADTRG
INTP4 P52/TOH0
INTP5 P53/TI000
INTP6 P55/TIT20IUD
INTP7
SI10 Input Serial data input to serial interface Input P16
SO10 Output Serial data output from serial interface Input P17/FLMD1
SCK10 I/O Clock input/output for serial interface Input P15
RxD00 Input Serial data input to asynchronous serial interface Input P13
TxD00 Output Serial data output from asynchronous serial interface Input P14
TW0TOFFP Input External input to stop 10-bit inverter control timer output Input P00/INTP0
TW0TO0TW0TO5
TIT20IUD External count clock input to 16-bit up/down counter P55/INTP6
TIT20CUD Count operation switching input to 16-bit up/down counter P56/TIT20CC0
TIT20CC0 P56/TIT20CUD
TIT20CC1
TIT20CLR
TIT20TO Output Pulse signal output of 16-bit up/down counter Input P57/TIT20CLR
TI000 External count clock input to 16-bit timer/event counter 00
TI001
TO00 Output 16-bit timer/event counter 00 output Input P54/TI001
TI50 External count clock input to 8-bit timer/event counter 50 P50/TO50
TI51
TO50 8-bit timer/event counter 50 output P50/TI50
TO51 8-bit timer/event counter 51 output P51/TI51
TOH0
Input External interrupt request input for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be
specified
Output 10-bit inverter control timer output Output RTP10-RTP15
Input
External capture trigger input to 16-bit up/down counter
External clear input to 16-bit up/down counter
Input
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
Input
External count clock input to 8-bit timer/event counter 51
Output
8-bit timer H0 output
Input
Input
Input
Input
Input
P56/TIT20CC0
/TIT20CUD
/INTP7
/INTP7
P57/TIT20CLR
/TIT20TO
P57/TIT20CC1
/TIT20TO
/TIT20CC1
P53/INTP5
P54/TO00
P51/TO51
P52/INTP4
User’s Manual U16928EJ2V0UD
25
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins (2/2)
Pin Name I/O Function After Reset Alternate Function
PCL Output Clock output (for trimming of X1 input clock) Input P31
BUZ Output Buzzer output Input P30
RTP00 to
RTP07
RTP10 to
RTP15
ADTRG Input A/D converter trigger input Input P03/INTP3
ANI0 to ANI7 Input A/D converter analog input Input P20 to P27
AVREF Input A/D converter reference voltage input and positive power supply
AVSS
RESET Input System reset input
X1 Input
X2
VDD
EVDD
VSS
EVSS
FLMD0
FLMD1 Input
Output Real-time output port 0 output Input P40 to P47
Output Real-time output port 1 output Output TW0TO0 to
TW0TO5
− −
for port 2
−
A/D converter ground potential. Make the same potential as
SS or VSS.
EV
Connecting resonator for X1 input clock oscillation
−
−
Positive power supply (except for ports)
−
Positive power supply for ports
−
Ground potential (except for ports)
−
Ground potential for ports
− − −
Flash memory programming mode setting
− −
− −
− −
− −
− −
− −
− −
− −
Input P17/SO10
26
User’s Manual U16928EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 to P03 (port 0)
P00 to P03 function as a 4-bit I/O port. These pins also function as external interrupt request input, timer output
stop external signal, and A/D converter trigger input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P03 function as a 4-bit I/O port. P00 to P03 can be set to input or output in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 to P03 function as external interrupt request input, timer output stop external signal, and A/D converter
trigger input.
(a) INTP0 to INTP3
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified. INTP2 also functions as an external trigger signal input pin of the
real-time output port when a valid edge is input.
(b) TW0TOFFP
This is an external input pin to stop timer output (TW0TO0 to TW0TO5).
(c) ADTRG
This is an external trigger signal input pin of the A/D converter.
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as pins for serial interface data I/O, clock I/O,
and flash memory programming mode setting.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as serial interface data I/O and clock I/O.
(a) SI10
This is a serial interface serial data input pin.
(b) SO10
This is a serial interface serial data output pin.
(c) SCK10
This is a serial interface serial clock I/O pin.
(d) RxD00
This is the serial data input pin of the asynchronous serial interface.
User’s Manual U16928EJ2V0UD
27
(e) TxD00
This is the serial data output pin of the asynchronous serial interface.
(f) FLMD1
This pin sets the flash memory programming mode.
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an 8-bit input-only port.
<R>
Caution Use P20 to P27 at EV
(2) Control mode
P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input
pins, see (5) ANI0/P20 to ANI7/P27 in 15.6 Cautions for A/D Converter.
2.2.4 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for clock output, and buzzer output.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as clock output, and buzzer output pins.
(a) BUZ
This is a buzzer output pin.
(b) PCL
This is a clock output pin.
Caution Be sure to pull down P31 after reset to prevent malfunction.
Remark The P31 and P32 pins of the
CHAPTER 2 PIN FUNCTIONS
DD = AVREF when using them in the port mode.
μ
PD78F0714 can be used to set the on-chip debug mode when the
on-chip debug function is used. For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
28
User’s Manual U16928EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.2.5 P40 to P47 (port 4)
P40 to P47 function as an 8-bit I/O port. These pins also function as real-time output port pins.
The following operation modes can be specified.
(1) Port mode
P40 to P47 function as an 8-bit I/O port. P40 to P47 can be set to input or output in 1-bit units using port mode
register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
(2) Control mode
P40 to P47 function as the pins for the real-time output port (RTP00 to RTP07) that outputs data in
synchronization with a trigger.
2.2.6 P50 to P57 (port 5)
P50 to P57 function as an 8-bit I/O port. These pins also function as external interrupt request input and timer I/O.
The following operation modes can be specified.
(1) Port mode
P50 to P57 function as an 8-bit I/O port. P50 to P57 can be set to input or output in 1-bit units using port mode
register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5).
(2) Control mode
P50 to P57 function as the pins for the external interrupt request input and timer I/O.
(a) INTP4 to INTP7
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI50, TI51
These are the pins for inputting an external count clock to 8-bit timer/event counter 50 and 51.
(c) TO50, TO51
These are timer output pins from 8-bit timer/event counters 50 and 51.
(d) TI000
This is the pin for inputting an external count clock to 16-bit timer/event counters 00 and is also for inputting a
capture trigger signal to the capture registers (CR00, CR01).
(e) TI001
This is the pin for inputting a capture trigger signal to the capture register (CR00) of 16-bit timer/event
counters 00.
(f) TO00, TOH0
These are timer output pins from 16-bit timer/event counter 00 and 8-bit timer H0.
(g) TIT20IUD
This is the pin for inputting an external count clock to 16-bit up/down counter ITENC20.
(h) TIT20IUD
This is the pin for inputting an count operation switching signal to 16-bit up/down counter ITENC20.
User’s Manual U16928EJ2V0UD
29
CHAPTER 2 PIN FUNCTIONS
(i) TIT20CLR
This is the pin for inputting a clear signal to 16-bit up/down counter ITENC20.
(j) TIT20CC0, TIT20CC1
These are the pins for inputting an external capture trigger to 16-bit up/down counter ITENC20.
(k) TIT20TO
This is a 16-bit up/down counter ITENC20 output pin.
2.2.7 P64 to P67 (port 6)
P64 to P67 function as a 4-bit I/O port. P64 to P67 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
Use of an on-chip pull-up resistor can be specified for P64 to P67 by pull-up resistor option register 6 (PU6).
2.2.8 P70 to P73 (port 7)
P70 to P73 function as a 4-bit I/O port. P70 to P73 can be set to input or output in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
2.2.9 TW0TO0/RTP10 to TW0TO5/RTP15
These are 10-bit inverter control timer output pins.
And, these pins function also as real-time output port pins.
2.2.10 AV
REF
This is the A/D converter reference voltage input pin.
When the A/D converter is not used, connect this pin directly to EV
DD or VDD
Note
.
Note Connect port 2 directly to EV
DD when it is used as a digital port.
2.2.11 AV
SS
This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with
the same potential as the EV
SS pin or VSS pin.
2.2.12 RESET
This is the active-low system reset input pin.
2.2.13 X1 and X2
These are the pins for connecting a resonator for the X1 input clock.
When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin.
Remark The X1 and X2 pins of the product with an on-chip debug function (part number pending) can be used to
set the on-chip debug mode when the on-chip debug function is used. For details, see CHAPTER 26
ON-CHIP DEBUG FUNCTION.
2.2.14 V
DD and EVDD
DD is the positive power supply pin for other than ports.
V
EV
DD is the positive power supply pin for ports.
30
User’s Manual U16928EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.2.15 VSS and EVSS
V
SS is the ground potential pin for other than ports.
EVSS is the ground potential pin for ports.
2.2.16 FLMD0
This pin sets the flash memory programming mode.
Connect FLMD0 to a flash memory programmer in the flash memory programming mode, and to EV
normal operation mode.
SS or VSS in the
User’s Manual U16928EJ2V0UD
31
CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.
See Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-2. Pin I/O Circuit Types
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/INTP0/TW0TOFFP
P01/INTP1
P02/INTP2
P03/INTP3/ADTRG
P10
P11
P12
P13/RxD00
P14/TxD00 5-H
P15/ SCK10
P16/SI10
P17/SO10/FLMD1 5-H
P20/ANI0 to P27/ANI7 9-C Input Connect to EVDD or EVSS.
P30/BUZ
P31/PCL
P32
P33
P40/RTP00 to P47/RTP07
P50/TI50/TO50
P51/TI51/TO51
P52/TOH0/INTP4
P53/TI000/INTP5
P54/TI001/TO00
P55/TIT20IUD/INTP6
P56/TIT20CUD/TIT20CC0/INTP7
P57/TIT20CLR/TIT20CC1/TIT20TO
P64 to P67
P70 to P73
TW0TO0/RTP10-TW0TO5/RTP15 4-B Output Leave open.
RESET 2 Input
AVREF Connect directly to EVDD or VDD
AVSS Connect directly to EVSS or VSS.
FLMD0
8-C
8-C
5-H
8-C
5-H
− −
I/O Input: Independently connect to EV
Output: Leave open.
I/O Input: Independently connect to EV
Output: Leave open.
−
Note
Connect to EVSS or VSS.
DD or EVSS via a resistor.
DD or EVSS via a resistor.
.
Note Connect port 2 directly to EV
32
DD when it is used as a digital port.
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List
Type 2
Type 8-C
EV
DD
IN
Schmitt-triggered input with hysteresis characteristics
Type 4-B
EV
DD
Data
Output
P-ch
N-ch
disable
OUT
Pullup
enable
Data
Output
disable
Type 9-C
IN
P-ch
N-ch
AV
SS
(threshold voltage)
V
V
P-ch
DD
P-ch
IN/OUT
N-ch
Comparator
+
Ð
REF
Type 5-H
Pullup
enable
Data
Output
disable
Input
enable
V
DD
P-ch
N-ch
EV
Input
enable
DD
P-ch
IN/OUT
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
μ
PD78F0714 products can access a 64 KB memory space. Figures 3-1 shows the memory map.
Caution Because the initial value of the internal memory size switching register (IMS) is CFH, set to C8H
by initialization.
Figure 3-1. Memory Map (
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
Special function registers
(SFR)
256 × 8 bits
General-purpose
registers
32 × 8 bits
μ
PD78F0714)
Note 1
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
Data memory
space
Reserved
8000H
7FFFH
Flash memory
32768 × 8 bits
Note 2
0084H
0083H
0000H
7FFFH
1000H
0FFFH
0800H
07FFH
0084H
0083H
0081H
0080H
007FH
0040H
003FH
0000H
Program area
CALLF entry area
Program area
Note 2
Option bite reservation
area (Reserved)
Option bite area
CALLT table area
Vector table area
Notes 1. This area occupies 9 bytes (planned) during on-chip debugging because it is used as a backup area
for user data during communication.
2. This area cannot be used during on-chip debugging because it is used as a communication command
area (256 bytes to 1 KB).
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3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
μ
PD78F0714 products incorporate internal ROM (flash memory), as shown below.
Table 3-1. Internal ROM Capacity
Internal ROM Part Number
Structure Capacity
μ
PD78F0714
Flash memory
32768 × 8 bits (0000H to 7FFFH)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon reset signal input or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
Table 3-2. Vector Table
Vector Table Address Interrupt Source Vector Table Address Interrupt Source
RESET input, POC, LVI,
WDT
0004H INTLVI 0024H INTCC11
0006H INTP0 0026H
0008H INTP1 0028H INTTM00
000AH INTP2 002AH INTTM01
000CH INTP3 002CH INTSRE00
000EH INTP4 002EH INTSR00
0010H INTP5 0030H INTST00
0012H INTP6 0032H INTTM50
0014H INTP7 0034H INTTM51
0016H INTTW0UD 0036H INTTMH0
0018H INTTW0CM3 0038H INTCSI10
001AH INTTW0CM4 003AH INTDMU
001CH INTTW0CM5 003CH INTAD
001EH INTCM10
0020H INTCM11 0000H
0022H INTCC10
Note
−
Note There is no interrupt request corresponding to vector table address 0026H.
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) Option byte area
The 1-byte area 0080H is reserved as a option byte area. For details, see CHAPTER 24 OPTION BYTE.
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CHAPTER 3 CPU ARCHITECTURE
(4) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
3.1.2 Internal data memory space
μ
PD78F0714 products incorporate the following RAMs.
(1) Internal high-speed RAM
The internal high-speed RAM is allocated to the area FB00H to FEFFH in a 1024 × 8 bits configuration.
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per one bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
3.1.3 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (see
Table 3-3 Special Function Register List in 3.2.3 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.4 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
μ
PD78F0714, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figure 3-2 shows correspondence between data memory and addressing. For details of each
addressing mode, see 3.4 Operand Address Addressing.
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Figure 3-2. Correspondence Between Data Memory and Addressing (μPD78F0714)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
FE20H
FE1FH
FB00H
FAFFH
Special function registers (SFR)
256 × 8 bits
General-purpose registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Note 1
Reserved
SFR addressing
Register addressing
Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
8000H
7FFFH
Flash memory
32768 × 8 bits
Note 2
0084H
0083H
0000H
Notes 1. This area occupies 9 bytes (planned) during on-chip debugging because it is used as a backup area
for user data during communication.
2. This area cannot be used during on-chip debugging because it is used as a communication command
area (256 bytes to 1 KB).
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CHAPTER 3 CPU ARCHITECTURE
3.2 Processor Registers
The
μ
PD78F0714 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-3. Format of Program Counter
15 0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 3-4. Format of Program Status Word
7 0
PSW IE Z RBS1 AC RBS0 0 ISP CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupts are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
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CHAPTER 3 CPU ARCHITECTURE
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-
level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H)
(see 19.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) cannot be acknowledged.
Actual interrupt request acknowledgment is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction
execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 3-5. Format of Stack Pointer
15 0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-6 and 3-7.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using
the stack.
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-6. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
Register pair higher
Register pair lower
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
PC15 to PC8
PC7 to PC0
(c) Interrupt, BRK instructions (when SP = FEE0H)
SP
FEE0H
FEE0H
SP
FEDDH
FEDFH
FEDEH
FEDDH
PSW
PC15 to PC8
PC7 to PC0
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-7. Data to Be Restored from Stack Memory
(a) POP rp instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
Register pair higher
Register pair lower
(b) RET instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
PC15 to PC8
PC7 to PC0
(c) RETI, RETB instructions (when SP = FEDDH)
SP
FEE0H
FEE0H
SP
FEDDH
FEDFH
FEDEH
FEDDH
PSW
PC15 to PC8
PC7 to PC0
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CHAPTER 3 CPU ARCHITECTURE
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-8. Configuration of General-Purpose Registers
(a) Absolute name
16-bit processing 8-bit processing
FEFFH
FEF8H
FEF0H
FEE8H
FEE0H
BANK0
BANK1
BANK2
BANK3
RP3
RP2
RP1
RP0
15 0 7 0
R7
R6
R5
R4
R3
R2
R1
R0
(b) Function name
16-bit processing 8-bit processing
FEFFH
FEF8H
FEF0H
FEE8H
FEE0H
BANK0
BANK1
BANK2
BANK3
HL
DE
BC
AX
15 0 7 0
H
L
D
E
B
C
A
X
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3.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH area.
Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Table 3-3 gives a list of the special function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
as an sfr variable by the #pragma sfr directive for the CC78K0. When using the RA78K0 or ID78K0-QB,
symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon RESET input.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Register List (1/5)
FF00H Port register 0 P0 R/W
FF01H Port register 1 P1 R/W
FF02H Port register 2 P2 R
FF03H Port register 3 P3 R/W
FF04H Port register 4 P4 R/W
FF05H Port register 5 P5 R/W
FF06H Port register 6 P6 R/W
FF07H Port register 7 P7 R/W
FF08H
FF09H
FF0AH 10-bit buffer register 1
10-bit buffer register 0
TW0BF
CM0
TW0BF
CM1
FF0BH
FF0CH 10-bit buffer register 2
TW0BF
CM2
FF0DH
FF0EH 10-bit buffer register 3
TW0BF
CM3
FF0FH
FF10H
16-bit up/down counter
IT20
UDC
FF11H
FF12H
16-bit compare register 0
IT20
CM0
FF13H
FF14H
16-bit compare register 1
IT20
CM1
FF15H
FF16H
16-bit timer counter 00 TM00 R
TW0BF
CM0L
−
TW0BF
CM1L
−
TW0BF
CM2L
−
TW0BF
CM3L
−
IT20
UDCL
−
IT20
CM0L
−
IT20
CM1L
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF17H
FF18H
FF19H
FF1AH
Receive buffer register 0 RXB00 R
Transmit shift register 0 TXS00 W
A/D conversion result register ADCR R
FF1BH
FF1FH Serial I/O shift register 10 SIO10 R
FF20H Port mode register 0 PM0 R/W
FF21H Port mode register 1 PM1 R/W
FF23H Port mode register 3 PM3 R/W
FF24H Port mode register 4 PM4 R/W
FF25H Port mode register 5 PM5 R/W
FF26H Port mode register 6 PM6 R/W
FF27H Port mode register 7 PM7 R/W
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
−
√
−
− √ √
−
− √ √
−
− √ √
−
−
√
−
−
√
−
−
√
−
− − √
− √ −
− √ −
− − √
− √ −
√ √
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
After
Reset
00H
00H
Undefined
00H
00H
00H
00H
00H
√
0000H
0000H
0000H
00FFH
√
√
√
0000H
0000H
0000H
0000H
FFH
FFH
Undefined
00H
−
FFH
FFH
FFH
FFH
FFH
FFH
FFH
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Table 3-3. Special Function Register List (2/5)
FF28H DC control register 00 DCCTL00 R/W
FF2AH 8-bit timer H mode register 0 TMHMD0 R/W
FF2CH 8-bit timer counter 50 TM50 R
FF2DH 8-bit timer compare register 50 CR50 R/W
FF2EH
Timer clock selection register 50 TCL50 R/W
FF2FH 8-bit timer mode control register 50 TMC50 R/W
FF30H Pull-up resistor option register 0 PU0 R/W
FF31H Pull-up resistor option register 1 PU1 R/W
FF33H Pull-up resistor option register 3 PU3 R/W
FF34H Pull-up resistor option register 4 PU4 R/W
FF35H Pull-up resistor option register 5 PU5 R/W
FF36H Pull-up resistor option register 6 PU6 R/W
FF37H Pull-up resistor option register 7 PU7 R/W
FF38H DC control register 01 DCCTL01 R/W
FF3AH Prescaler mode register IT20PRM R/W
FF3BH Status register IT20STS R
FF3CH 8-bit timer counter 51 TM51 R
FF3DH 8-bit timer compare register 51 CR51 R/W
FF3EH
Timer clock selection register 51 TCL51 R/W
FF3FH 8-bit timer mode control register 51 TMC51 R/W
FF40H Clock output selection register CKS R/W
FF48H External interrupt rising edge enable register EGP R/W
FF49H External interrupt falling edge enable register EGN R/W
FF50H
FF51H
FF52H
FF53H
FF54H
10-bit buffer register 4
10-bit buffer register 5
TW0BF
CM4
TW0BF
CM5
10-bit compare register 0 TW0CM0
TW0BF
CM4L
−
TW0BF
CM5L
−
R/W
R/W
R/W
FF55H
FF56H
10-bit compare register 1 TW0CM1 R/W
FF57H
FF58H
10-bit compare register 2 TW0CM2 R/W
FF59H
FF5AH
10-bit compare register 3 TW0CM3
R/W
FF5BH
FF5CH
10-bit compare register 4 TW0CM4 R/W
FF5DH
FF5EH
10-bit compare register 5 TW0CM5 R/W
FF5FH
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
√ √ −
√ √ −
− √ −
− √ −
− √
−
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
− √ −
− √
−
√ √ −
√ √ −
√ √ −
√ √ −
−
√
√
−
−
√
√
−
− − √
− − √
− − √
− − √
− − √
− − √
After
Reset
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
07H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
0000H
0000H
00FFH
0000H
0000H
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CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Register List (3/5)
FF60H Remainder data register 0
FF61H
FF62H Multiplication/division data register A0
FF63H
FF64H
FF65H
FF66H Multiplication/division data register B0
SDR0
MDA0L
MDA0H
MDB0
FF67H
SDR0L
SDR0H
MDA0LL
MDA0LH
MDA0HL
MDA0HH
MDB0L
MDB0H
R
R/W
R/W
R/W
FF68H Multiplier/divider control register 0 DMUC0 R/W
FF6AH Capture/compare control register 00 CRC00 R/W
FF6BH 16-bit timer output control register 00 TOC00 R/W
FF6CH
FF6DH
FF6EH
A/D converter mode register ADM R/W
Analog input channel specification register ADS R/W
Power-fail comparison mode register PFM R/W
FF6FH Power-fail comparison threshold register PFT R/W
FF70H Asynchronous serial interface operation mode
ASIM00 R/W
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
− √ √
− √
− √ √
− √
− √ √
− √
− √ √
− √
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √
√ √ −
00H
00H
00H
00H
−
After
Reset
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
01H
register 00
FF71H Baud rate generator control register 00 BRGC00 R/W
FF73H Asynchronous serial interface reception error
ASIS00 R
− √ −
− √ −
1FH
00H
status register 00
FF78H Low-voltage detection register LVIM R/W
FF7AH 16-bit timer capture/compare register 00 CR00 R/W
√ √ −
− − √
Note
00H
0000H
FF7BH
FF7CH 16-bit timer capture/compare register 01 CR01 R/W
− − √
0000H
FF7DH
FF7EH 16-bit timer mode control register 00 TMC00 R/W
FF7FH Prescaler mode register 00 PRM00 R/W
FF80H Serial operation mode register 10 CSIM10 R/W
FF81H Serial clock selection register 10 CSIC10 R/W
FF84H Transmit buffer register 10 SOTB10 R/W
FF88H Inverter timer control register TW0C R/W
FF89H Inverter timer mode register TW0M R/W
FF8AH Dead time reload register TW0DTIME R/W
FF8BH A/D trigger select register TW0TRGS R/W
FF8CH Inverter timer output control register TW0OC R/W
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
00H
00H
00H
00H
Undefined
00H
00H
FFH
00H
00H
Note This value is 83H only after a LVI reset.
46
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CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Register List (4/5)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After
1 Bit 8 Bits 16 Bits Reset
FF90H 16-bit timer capture/compare register 0
FF91H
FF92H 16-bit timer capture/compare register 1
FF93H
FF94H Capture/compare control register IT20CCR R/W
FF95H Timer unit mode register IT20TUM R/W
FF96H Timer control register IT20TMC R/W
FF97H Effective edge select register IT20SESA R/W
FF98H Watchdog timer mode register WDTM R/W
FF99H Watchdog timer enable register WDTE R/W
FF9EH 8-bit timer H compare register 00 CMP00 R/W
FF9FH 8-bit timer H compare register 01 CMP01 R/W
FFA0H Internal oscillation mode register RCM R/W
FFA1H Main clock mode register MCM R/W
FFA2H Main OSC control register MOC R/W
FFA3H Oscillation stabilization time counter status register OSTC R
FFA4H Oscillation stabilization time select register OSTS R/W
FFAAH Noise eliminate time select register NRC1 R/W
FFACH Reset control flag register RESF R
FFB0H Real-time output buffer register 0L RTBL00 R/W
FFB2H Real-time output buffer register 0H RTBH00 R/W
FFB4H Real-time output port mode register 0 RTPM00 R/W
FFB5H Real-time output port control register 0 RTPC00 R/W
FFB8H Real-time output buffer register 1L RTBL01 R/W
FFBAH Real-time output buffer register 1H RTBH01 R/W
FFBCH Real-time output port mode register 1 RTPM01 R/W
FFBDH Real-time output port control register 1 RTPC01 R/W
FFC0H Flash protect command register PFCMD W
FFC2H Flash status register PFS R/W
FFC4H Flash programming mode control register FLPMC R/W
IT20C
C0
IT20C
C1
IT20C
C0L
−
IT20C
C1L
−
R/W
R/W
− √ √
−
− √ √
−
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
− √ −
− √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
√ √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
0000H
0000H
9AH
00H
Undefined
0XH
Notes 1. This value varies depending on the reset source.
2. Differs depending on the operation mode.
• User mode: 08H
• On-board mode: 0CH
00H
00H
00H
00H
67H
00H
00H
00H
00H
00H
00H
05H
00H
Note 1
00H
00H
00H
00H
00H
00H
00H
00H
00H
Note 2
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CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Register List (5/5)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After
1 Bit 8 Bits 16 Bits Reset
FFE0H Interrupt request flag register 0L IF0 IF0L R/W
FFE1H Interrupt request flag register 0H IF0H R/W
FFE2H Interrupt request flag register 1L IF1 IF1L R/W
FFE3H Interrupt request flag register 1H IF1H R/W
FFE4H Interrupt mask flag register 0L MK0 MK0L R/W
FFE5H Interrupt mask flag register 0H MK0H R/W
FFE6H Interrupt mask flag register 1L MK1 MK1L R/W
FFE7H Interrupt mask flag register 1H MK1H R/W
FFE8H Priority specification flag register 0L PR0 PR0L R/W
FFE9H Priority specification flag register 0H PR0H R/W
FFEAH Priority specification flag register 1L PR1 PR1L R/W
FFEBH Priority specification flag register 1H PR1H R/W
FFF0H Internal memory size switching register
FFFBH Processor clock control register PCC R/W
FFFDH System wait control register VSWC R/W
Note
IMS R/W
√ √ √
√ √
√ √ √
√ √
√ √ √
√ √
√ √ √
√ √
√ √ √
√ √
√ √ √
√ √
− √ −
√ √ −
√ √ −
00H
00H
00H
00H
FFH
FFH
FFH
DFH
FFH
FFH
FFH
FFH
CFH
00H
00H
Note Because the initial value of the internal memory size switching register (IMS) is CFH, set to C8H by
initialization.
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3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by
the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
PC
+
15 0
876
PC indicates the start address
...
of the instruction after the BR instruction.
α
15 0
PC
When S = 0, all bits of are 0.
When S = 1, all bits of are 1.
α
α
S
jdisp8
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CHAPTER 3 CPU ARCHITECTURE
3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
70
CALL or BR
Low Addr.
High Addr.
15 0
PC
In the case of CALLF !addr11 instruction
15 0
PC
00001
87
70
643
10–8
fa
CALLF
fa
7–0
11 10
87
50
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CHAPTER 3 CPU ARCHITECTURE
<R>
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 0040H to 007FH, which is indicated by
addr5, and allows branching to the entire memory space.
[Illustration]
addr5
Operation code
Effective address
15 1
01
00000000
765 10
ta4-0
15 1
01
00000000
8765 0
0
111
87
ta
4-0
65 0
0
have the same value
The effective address and addr5
...
Effective address+1
Memory (Table)
70
Low Addr.
High Addr.
15 0
PC
87
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CHAPTER 3 CPU ARCHITECTURE
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
07
rp
15 0
PC
AX
87
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3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the
μ
PD78F0714 instruction words, the following instructions employ implied addressing.
Instruction Register to Be Specified by Implied Addressing
MULU A register for multiplicand and AX register for product storage
DIVUW AX register for dividend and quotient storage
ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets
ROR4/ROL4 A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
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CHAPTER 3 CPU ARCHITECTURE
3.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flags
(RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code 0 1100010
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code 1 0000100
Register specify code
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3.4.3 Direct addressing
[Function]
The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code 1 0 0 0 1 1 1 0 OP code
00000000 00H
11111110 FEH
[Illustration]
07
OP code
addr16 (lower)
addr16 (upper)
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers
(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to
1FH, bit 8 is set to 1. Refer to the [Illustration].
[Operand format]
Identifier Description
saddr Immediate data that indicate label or FE20H to FF1FH
saddrp Immediate data that indicate label or FE20H to FF1EH (even address only)
[Description example]
MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)
Operation code 1 1110010 OP code
0 0110000 30H (saddr-offset)
[Illustration]
07
OP code
saddr-offset
15
Effective address
1
111111
When 8-bit immediate data is 20H to FFH,
When 8-bit immediate data is 00H to 1FH,
56
87
α
α
= 0
α
= 1
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0
CHAPTER 3 CPU ARCHITECTURE
3.4.5 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special function register name
sfrp 16-bit manipulatable special function register name (even address only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code 1 1 1 1 0 1 1 0 OP code
0 0 1 0 0 0 0 0 20H (sfr-offset)
[Illustration]
07
Effective address
OP code
sfr-offset
15
1
111111
87
1
SFR
0
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CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be
carried out for all the memory spaces.
[Operand format]
Identifier Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code 10000101
[Illustration]
16 08D7
DE
The contents of the memory
addressed are transferred.
7 0
A
E
Memory
The memory address
07
specified with the
register pair DE
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3.4.7 Based addressing
[Function]
8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from
the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
−
[HL + byte]
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CHAPTER 3 CPU ARCHITECTURE
3.4.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the base register, that
is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the
sum is used to address the memory. Addition is performed by expanding the B or C register contents as a
positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the
memory spaces.
[Operand format]
Identifier Description
−
[HL + B], [HL + C]
[Description example]
In the case of MOV A, [HL + B] (selecting B register)
Operation code 10101011
[Illustration]
16 0
78
HL
The contents of the memory
addressed are transferred.
7 0
A
H
+
L
B
Memory
07
07
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3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return
instructions are executed or the register is saved/reset upon generation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.
[Description example]
In the case of PUSH DE (saving DE register)
Operation code 1 0 1 1 0 1 0 1
[Illustration]
Memory 07
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
D
E
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
There are two types of pin I/O buffer power supplies: AV
supplies and the pins is shown below.
Table 4-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P20 to P27
EVDD Port pins other than P20 to P27
Note Connect AV
REF to EVDD when port 2 is used as a digital port.
μ
PD78F0714 products are provided with the ports shown in Figure 4-1, which enable variety of control operations.
The functions of each port are shown in Table 4-2.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, see CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
REF and EVDD. The relationship between these power
Note
Port 5
Port 6
Port 7
P50
P57
P64
P67
P70
P73
P00
Port 0
P03
P10
Port 1
P17
P20
Port 2
P27
P30
Port 3
P33
P40
62
Port 4
P47
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Table 4-2. Port Functions
Pin Name I/O Function After Reset Alternate Function
P00 INTP0/TW0TOFFP
P01 INTP1
P02 INTP2
P03
P10
P11
P12
P13 RxD00
P14 TxD00
P15 SCK10
P16 SI10
P17
P20 to P27 Input
P30 BUZ
P31 PCL
P32
P33
P40 to P47 I/O
P50 TI50/TO50
P51 TI51/TO51
P52 TOH0/INTP4
P53 TI000/INTP5
P54 TI001/TO00
P55 TIT20IUD/INTP6
P56
P57
P64 to P67 I/O
P70 to P73 I/O
I/O
I/O
I/O
I/O
Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 2.
8-bit input-only port.
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 4.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 5.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 6.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 7.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
INTP3/ADTRG
Input
SO10/FLMD1
Input ANI0 to ANI7
Input
Input RTP00 to RTP07
Input
TIT20CUD
/TIT20CC0/INTP7
TIT20CLR
/TIT20CC1
/TIT20TO
Input
Input
−
−
−
−
−
−
−
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CHAPTER 4 PORT FUNCTIONS
4.2 Port Configuration
Ports consist of the following hardware.
Table 4-3. Port Configuration
Item Configuration
Control registers
Port Total: 48 (CMOS I/O: 40, CMOS input: 8)
Pull-up resistor Total: 40 (software control: 40)
Port mode register (PM0, PM1, PM3 to PM7)
Port register (P0 to P7)
Pull-up resistor option register (PU0, PU1, PU3 to PU7)
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4.2.1 Port 0
Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 0 (PU0).
This port can also be used for external interrupt request input, timer output stop external signal, and A/D converter
trigger input.
RESET input sets port 0 to input mode.
Figure 4-2 shows a block diagram of port 0.
Figure 4-2. Block Diagram of P00 to P03
EV
DD
WR
PU
PU0
Internal bus
PU00 to PU03
Alternate
function
RD
PORT
WR
Output latch
(P00 to P03)
WR
PM
PM0
PM00 to PM03
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
P-ch
Selector
P00/INTP0/TW0TOFFP,
P01/INTP1,
P02/INTP2,
P03/INTP3/ADTRG
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CHAPTER 4 PORT FUNCTIONS
4.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 1 (PU1).
This port can also be used for serial interface data I/O, clock I/O, and flash memory programming mode setting.
RESET input sets port 1 to input mode.
Figures 4-3 to 4-6 show block diagrams of port 1.
Caution When P15/SCK10, P16/SI10, and P17/SO10 are used as general-purpose ports, do not write to
serial clock selection register 10 (CSIC10).
Figure 4-3. Block Diagram of P10 toP13 and P16
EV
DD
PU
WR
PU1
PU10 to PU13,
PU16
Alternate
function
P-ch
RD
Internal bus
WR
PORT
Output latch
(P10 to P13, P16)
WR
PM
PM1
PM10 to PM13,
PM16
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
Selector
P10 to P12,
P13/RxD00,
P16/SI10
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CHAPTER 4 PORT FUNCTIONS
Figure 4-4. Block Diagram of P14
EV
DD
WR
PU
PU1
PU14
RD
PORT
WR
Internal bus
WR
PM
Output latch
(P14)
PM1
PM14
Alternate
function
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
P-ch
Selector
P14/TxD00
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CHAPTER 4 PORT FUNCTIONS
Figure 4-5. Block Diagram of P15
EV
DD
WR
PU
PU1
PU15
Alternate
function
RD
PORT
WR
Internal bus
Output latch
(P15)
WR
PM
PM1
PM15
Alternate
function
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
P-ch
Selector
P15/SCK10
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CHAPTER 4 PORT FUNCTIONS
Figure 4-6. Block Diagram of P17
EV
DD
WR
PU
PU1
Internal bus
PU17
Alternate
function
RD
PORT
WR
Output latch
(P17)
WR
PM
PM1
PM17
Alternate
function
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
P-ch
Selector
P17/SO10/FLMD1
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CHAPTER 4 PORT FUNCTIONS
4.2.3 Port 2
Port 2 is an 8-bit input-only port.
This port can also be used for A/D converter analog input.
Figure 4-7 shows a block diagram of port 2.
Figure 4-7. Block Diagram of P20 to P27
RD
<R>
Internal bus
A/D converter
RD: Read signal
Caution Use P20 to P27 at EV
P20/ANI0 to P27/ANI7
DD = AVREF when using them in the port mode.
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4.2.4 Port 3
Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 3 (PU3).
This port can also be used for buzzer output, and clock output.
RESET input sets port 3 to input mode.
Figures 4-8 and 4-9 show block diagrams of port 3.
Caution Be sure to pull down P31 after reset to prevent malfunction.
Remark The P31/INTP2 and P32/INTP3 pins of the
μ
PD78F0714 can be used to set the on-chip debug mode
when the on-chip debug function is used. For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
Figure 4-8. Block Diagram of P30 and P31
EV
DD
WR
PU
PU3
PU30, PU31
RD
Internal bus
WR
PORT
Output latch
(P30, P31)
WR
PM
PM3
PM30, PM31
Alternate
function
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
P-ch
Selector
P30/BUZ,
P31/PCL
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CHAPTER 4 PORT FUNCTIONS
Figure 4-9. Block Diagram of P32 and P33
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CHAPTER 4 PORT FUNCTIONS
4.2.5 Port 4
Port 4 is an 8-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units
using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor
option register 4 (PU4).
This port can also be used as real-time output ports.
RESET input sets port 4 to input mode.
Figure 4-10 shows a block diagram of port 4.
Figure 4-10. Block Diagram of P40 to P47
EV
DD
WR
PU
PU4
PU40 to PU47
RD
Internal bus
WR
PORT
Output latch
(P40 to P47)
WR
PM
PM4
PM40 to PM47
Alternate
function
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
P-ch
Selector
P40/RTP00P47/RTP07
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4.2.6 Port 5
Port 5 is an 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units
using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up
resistor option register 5 (PU5).
This port can also be used as external interrupt request input, timer I/O.
RESET input sets port 5 to input mode.
Figures 4-11 and 4-12 show block diagrams of port 5.
Figure 4-11. Block Diagram of P50 to P52, P54, and P57
EV
DD
WR
PU
PU5
PU50 to PU52,
PU54, PU57
Alternate
function
RD
P-ch
Internal bus
PORT
WR
Output latch
(P50 to P52, P54, P57)
WR
PM
PM5
PM50 to PM52,
PM54, PM57
Alternate
function
PU5: Pull-up resistor option register 5
PM5: Port mode register 5
RD: Read signal
WR××: Write signal
Selector
P50/TI50/TO50,
P51/TI51/TO51,
P52/TOH0/INTP4,
P54/TI001/TO00,
P57/TIT20CLR/
TIT20CC1/TIT20TO
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Figure 4-12. Block Diagram of P53, P55, and P56
EV
DD
WR
PU
PU5
PU53, PU55,
PU56
Alternate
function
RD
P-ch
Internal bus
PORT
WR
Output latch
(P53, P55, P56)
WR
PM
PM5
PM53, PM55,
PM56
PU5: Pull-up resistor option register 5
PM5: Port mode register 5
RD: Read signal
WR××: Write signal
Selector
P53/TI000/INTP5,
P55/TIT20IUD/INTP6,
P56/TIT20CUD/
TIT20CC0/INTP7
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CHAPTER 4 PORT FUNCTIONS
4.2.7 Port 6
Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units
using port mode register 6 (PM6). When used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 6 (PU6).
RESET input sets port 6 to input mode.
Figure 4-13 shows a block diagram of port 6.
Figure 4-13. Block Diagram of P64 to P67
EV
DD
PU
WR
PU6
PU64 to PU67
RD
Internal bus
WR
PORT
Output latch
(P64 to P67)
WR
PM
PM6
PM64 to PM67
PU6: Pull-up resistor option register 6
PM6: Port mode register 6
RD: Read signal
WR××: Write signal
P-ch
Selector
P64 to P67
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4.2.8 Port 7
Port 7 is an 4-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units
using port mode register 7 (PM7). When the P70 to P73 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 7 (PU7).
RESET input sets port 7 to input mode.
Figure 4-14 shows a block diagram of port 7.
Figure 4-14. Block Diagram of P70 to P73
EV
DD
PU
WR
PU7
PU70 to PU73
RD
Internal bus
WR
PORT
Output latch
(P70 to P73)
WR
PM
PM7
PM70 to PM73
PU7: Pull-up resistor option register 7
PM7: Port mode register 7
RD: Read signal
WR××: Write signal
P-ch
Selector
P70 to P73
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4.3 Registers Controlling Port Function
Port functions are controlled by the following three types of registers.
• Port mode registers (PM0, PM1, PM3 to PM7)
• Port registers (P0 to P7)
• Pull-up resistor option registers (PU0, PU1, PU3 to PU7)
(1) Port mode registers (PM0, PM1, PM3 to PM7)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table
4-4.
Figure 4-15. Format of Port Mode Register
Symbol
PM0
7
1
6
1
5
1
4
1
3
PM032PM021PM010PM00
Address
FF20H
After reset
FFH
R/W
R/W
PM1
PM3
PM4
PM5
PM6
PM7
7
PM17
7
1
7
PM47
7
PM57
7
PM67
7
1
6
PM165PM154PM143PM132PM121PM110PM10 FF21H FFH R/W
6
1
6
PM465PM454PM443PM432PM421PM410PM40 FF24H FFH R/W
6
PM565PM554PM543PM532PM521PM510PM50 FF25H FFH R/W
6
PM665PM654PM64
6
1
5
1
5
1
PMmn
0 Output mode (output buffer on)
1 Input mode (output buffer off)
4
1
4
1
3
PM332PM321PM310PM30 FF23H FFH R/W
3
1
3
PM732PM721PM710PM70 FF27H FFH R/W
2
1
Pmn pin I/O mode selection
(m = 0, 1, 3 to 7; n = 0 to 7)
1
1
0
1 FF26H FFH R/W
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Table 4-4. Settings of Port Mode Register and Output Latch When Using Alternate Function
Pin Name
INTP0
TW0TOFFP
P01 INTP1
P02 INTP2
INTP3
ADTRG
P13 RxD00
P14 TxD00
P15 SCK10
P16 SI10
SO10
FLMD1
P20-P27 ANI0-ANI7
P30 BUZ
P31 PCL
P40-P47 RTP00-RTP07
TI50
TO50
TI51
TO51
INTP4
TOH0
INTP5
Alternate Function
Function Name I/O
Input
Input
Input
Input
Input
Input
Input
Output
Input
Output
Input
Output
Input
Input
Output
Output
Output
Input
Output
Input
Output
Input
Output
Input
PM×× P××
1 × P00
1 ×
1 ×
1 ×
1 × P03
1 ×
1 ×
0 1
1 ×
0 1
1 ×
0 0 P17
1 ×
1 ×
0 0
0 0
0 0
1 × P50
0 0
1 × P51
0 0
1 × P52
0 0
1 × ×
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CHAPTER 4 PORT FUNCTIONS
(2) Port registers (P0 to P7)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output
latch is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H (but P2 is undefined).
Figure 4-16. Format of Port Register
Symbol
P0
7
0
6
0
5
0
4
0
3
P03
2
P02
1
P01
0
P00
Address
FF00H
After reset
00H (output latch)
R/W
R/W
P1
P2
P3
P4
P5
P6
P7
7
P17
7
P27
7
0
7
P47
7
P57
7
P67
7
0
6
P16
6
P26
6
0
6
P46
6
P56
6
P66
6
0
5
P15
5
P25
5
0
5
P45
5
P55
5
P65
5
0
4
P14
4
P24
4
0
4
P44
4
P54
4
P64
4
0
3
P13
3
P23
3
P33
3
P43
3
P53
3
0
3
P73
2
P12
2
P22
2
P32
2
P42
2
P52
2
0
2
P72
1
P11
1
P21
1
P31
1
P41
1
P51
1
0
1
P71
m = 0 to 7; n = 0 to 7
0 Output 0 Input low level
1 Output 1 Input high level
Pmn
Output data control (in output mode) Input data read (in input mode)
0
P10 FF01H 00H (output latch) R/W
0
P20 FF02H Undefined
0
P30 FF03H 00H (output latch) R/W
0
P40 FF04H 00H (output latch) R/W
0
P50 FF05H 00H (output latch) R/W
0
0 FF06H 00H (output latch) R/W
0
P70 FF07H 00H (output latch) R/W
R
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(3) Pull-up resistor option registers (PU0, PU1, and PU3 to PU7)
These registers specify whether the on-chip pull-up resistors of P00 to P03, P10 to P17, P30 to P33, P40 to P47,
P50 to P57, P64 to P67, P70 to P73 are to be used or not. On-chip pull-up resistors can be used in 1-bit units
only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified.
On-chip pull-up resistors cannot be connected for bits set to output mode and bits used as alternate-function
output pins, regardless of the settings of PU0, PU1, and PU3 to PU7.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 4-17. Format of Pull-up Resistor Option Register
Symbol
PU0
7
0
6
0
5
0
4
0
3
PU032PU021PU010PU00
Address
FF30H
After reset
00H
R/W
R/W
PU1
PU3
PU4
PU5
PU6
PU7
7
PU17
7
0
7
PU47
7
PU57
7
PU67
7
0
6
PU165PU154PU143PU132PU121PU110PU10 FF31H 00H R/W
6
0
6
PU465PU454PU443PU432PU421PU410PU40 FF34H 00H R/W
6
PU565PU554PU543PU532PU521PU510PU50 FF35H 00H R/W
6
PU665PU654PU64
6
0
5
0
5
0
4
0
4
0
PUmn
0 On-chip pull-up resistor not connected
1 On-chip pull-up resistor connected
3
PU332PU321PU310PU30 FF33H 00H R/W
3
0
3
PU732PU721PU710PU70 FF37H 00H R/W
Pmn pin on-chip pull-up resistor selection
2
0
(m = 0, 1, 3 to 7; n = 0 to 7)
1
0
0
0 FF36H 00H R/W
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the
port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins,
the output latch contents for pins specified as input are undefined, even for bits other than the
manipulated bit.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does
not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the
output latch, but since the output buffer is off, the pin status does not change.
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<R>
4.5 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the
output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example> When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level
via a 1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the
output latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses
of P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at
this time, the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
Figure 4-18. Bit Manipulation Instruction (P10)
1-bit manipulation
P10
Low-level output
P11 to P17
Pin status: High-level
instruction
(set1 P1.0)
is executed for P10
bit.
P10
P11 to P17
μ
PD78F0714.
High-level output
Pin status: High-level
Port 1 output latch
00000000
1-bit manipulation instruction for P10 bit
<1> Port register 1 (P1) is read in 8-bit units.
• In the case of P10, an output port, the value of the port output latch (0) is read.
• In the case of P11 to P17, input ports, the pin status (1) is read.
<2> Set the P10 bit to 1.
<3> Write the results of <2> to the output latch of port register 1 (P1)
in 8-bit units.
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11111111
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CHAPTER 5 CLOCK GENERATOR
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following two system clock oscillators are available.
• X1 oscillator
The X1 oscillator oscillates a clock of f
XP = 5.0 to 20.0 MHz. Oscillation can be stopped by executing the STOP
instruction or setting the main OSC control register (MOC) and processor clock control register (PCC).
• Internal oscillator
The Internal oscillator oscillates a clock of f
R = 240 kHz (TYP.). Oscillation can be stopped by setting the
internal oscillation mode register (RCM) when “Can be stopped by software” is set by an option byte and the X1
input clock is used as the CPU clock.
Remarks 1. f
XP: X1 input clock oscillation frequency
2. fR: internal oscillation clock frequency
5.2 Configuration of Clock Generator
The clock generator consists of the following hardware.
Table 5-1. Configuration of Clock Generator
Control registers
Oscillator
Item Configuration
Processor clock control register (PCC)
Internal oscillation mode register (RCM)
Main clock mode register (MCM)
Main OSC control register (MOC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
System wait control register (VSWC)
X1 oscillator
Internal oscillator
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Figure 5-1. Block Diagram of Clock Generator
Internal bus
Oscillation
stabilization time
select register
(OSTS)
OSTS1 OSTS0OSTS2
3
X1 oscillation
MOST
MOST
MOST
14
13
15
Oscillation
stabilization
MOST
time counter
16
status
register
(OSTC)
PCC2
3
Processor clock
control register
(PCC)
PCC1 PCC0
Controller
Control signal
C
P
U
CPU clock
(f
CPU
)
STOP
MSTOP
Main OSC
control
register
(MOC)
MCS
Main clock
mode register
(MCM)
MCM0
stabilization time counter
MOST
11
X1
X2
X1 oscillator
oscillator
Option byte
(LSROSC)
1: Cannot be stopped
0: Can be stopped
Internal oscillation
mode register (RCM)
Internal
RSTOP
f
XP
Operation
clock switch
f
R
Internal bus
Prescaler
f
X
8-bit timer 51,
watchdog timer
f
X
2
Prescaler
f
X
f
X
2
3
2
2
f
X
4
2
Prescaler
Clock to peripheral
hardware
Selector
f
CPU
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5.3 Registers Controlling Clock Generator
The following seven registers are used to control the clock generator.
• Processor clock control register (PCC)
• Internal oscillation mode register (RCM)
• Main clock mode register (MCM)
• Main OSC control register (MOC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• System wait control register (VSWC)
(1) Processor clock control register (PCC)
The PCC register is used to set the CPU clock division ratio.
The PCC is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PCC to 00H.
Figure 5-2. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PCC 0 0 0 0 0 PCC2 PCC1 PCC0
CPU clock (fCPU) selection
0 0 0 fX fR fXP
0 0 1 fX/2 fR/2 fXP/2
0 1 0 fX/22
0 1 1 fX/23
1 0 0 fX/24
Other than above Setting prohibited
Note Setting prohibited.
Caution Be sure to clear bit 3 to 7 to 0.
Remarks 1. MCM0: Bit 0 of main clock mode register (MCM)
2. f
3. f
4. f
PCC2 PCC1 PCC0
MCM0 = 0 MCM0 = 1
Note
−
Note
−
Note
−
X: Main system clock oscillation frequency (X1 input clock oscillation frequency or internal
XP/2
f
XP/2
f
XP/2
f
2
3
4
oscillation clock frequency)
R: Internal oscillation clock frequency
XP: X1 input clock oscillation frequency
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The fastest instruction can be executed in 2 clocks of the CPU clock in the μPD78F0714. Therefore, the
relationship between the CPU clock (fCPU) and minimum instruction execution time is as shown in the Table 5-2.
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU)
fX
fX/2
fX/22
fX/23
fX/24
X1 Input Clock
At 20 MHz Operation At 16 MHz Operation At 240 kHz (TYP.) Operation
0.1
μ
s 0.125
0.2
μ
s 0.25
0.4
μ
s 0.5
0.8
μ
s 1.0
1.6
μ
s 2.0
Minimum Instruction Execution Time: 2/fCPU
Note 1
Internal Oscillation Clock
μ
s 8.3
μ
s 16.6
μ
s −
μ
s −
μ
s −
μ
s (TYP.)
μ
s (TYP.)
Note 2
Note 2
Note 2
Note 1
Notes 1. The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/internal oscillation
clock) (see Figure 5-4).
2. Setting prohibited.
(2) Internal oscillation mode register (RCM)
This register sets the operation mode of internal oscillator.
This register is valid when “Can be stopped by software” is set for internal oscillator by an option byte, and the X1
input clock is selected as the CPU clock. If “Cannot be stopped” is selected for internal oscillator by an option
byte, settings for this register are invalid.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-3. Format of Internal Oscillation Mode Register (RCM)
Address: FFA0H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
RCM 0 0 0 0 0 0 0 RSTOP
RSTOP Internal oscillator oscillating/stopped
0 Internal oscillator oscillating
1 Internal oscillator stopped
Caution Make sure that the bit 1 (MCS) of the main clock mode register (MCM) is 1 before
setting RSTOP.
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CHAPTER 5 CLOCK GENERATOR
(3) Main clock mode register (MCM)
This register sets the CPU clock (X1 input clock/internal oscillation clock).
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-4. Format of Main Clock Mode Register (MCM)
Address: FFA1H After reset: 00H R/W
Symbol 7 6 5 4 3 2 <1> <0>
MCM 0 0 0 0 0 0 MCS MCM0
Note
MCS CPU clock status
0 Operates with internal oscillation clock
1 Operates with X1 input clock
MCM0 Selection of source clock to CPU
0 Internal oscillation clock
1 X1 input clock
Note Bit 1 is read-only.
Caution When internal oscillation clock is selected as the source clock to the CPU, the
divided clock of the internal oscillator output (f
X) is supplied to the peripheral
hardware (fX = 240 kHz (TYP.)).
Operation of the peripheral hardware with internal oscillation clock cannot be
guaranteed. Therefore, when internal oscillation clock is selected as the source
clock to the CPU, do not use peripheral hardware. In addition, stop the peripheral
hardware before switching the source clock to the CPU from the X1 input clock to
the internal oscillation clock. Note, however, that the following peripheral hardware
can be used when the CPU operates on the internal oscillation clock.
• Watchdog timer
• 8-bit timer 51 when f
7
R/2
is selected as count clock
• Peripheral hardware selecting external clock as the clock source
(Except when external count clock of 16-bit up/down counter ITENC20 or 16-
bit timer/event counter 00 is selected)
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(4) Main OSC control register (MOC)
This register selects the operation mode of the X1 input clock.
This register is used to stop the X1 oscillator operation when the CPU is operating with the internal oscillation
clock. Therefore, this register is valid only when the CPU is operating with the internal oscillation clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-5. Format of Main OSC Control Register (MOC)
Address: FFA2H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
MOC MSTOP 0 0 0 0 0 0 0
MSTOP Control of X1 oscillator operation
0 X1 oscillator operating
1 X1 oscillator stopped
Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting
MSTOP.
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CHAPTER 5 CLOCK GENERATOR
(5) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 input clock oscillation stabilization time counter. If the internal oscillation clock
is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction, MSTOP = 1 clear
OSTC to 00H.
Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16
Oscillation stabilization time status
1 0 0 0 0 211/fXP min.
1 1 0 0 0 213/fXP min.
1 1 1 0 0 214/fXP min.
1 1 1 1 0 215/fXP min. 1.64 ms min.
1 1 1 1 1 216/fXP min. 3.27 ms min.
MOST11 MOST13 MOST14 MOST15 MOST16
fXP = 20 MHz
102.4
μ
s min.
409.6
μ
s min.
819.2
μ
s min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. If the STOP mode is entered and then released while the internal oscillation clock
is being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
3. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
90
Remark f
X1 pin voltage
waveform
a
XP: X1 input clock oscillation frequency
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CHAPTER 5 CLOCK GENERATOR
(6) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 oscillation stabilization wait time when STOP mode is released.
The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU
clock. After STOP mode is released with internal oscillation clock selected as CPU clock, the oscillation
stabilization time must be confirmed by OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H After reset: 05H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
0 0 1 211/fXP
0 1 0 213/fXP
0 1 1 214/fXP
1 0 0 215/fXP 1.64 ms
1 0 1 216/fXP 3.27 ms
Other than above Setting prohibited
OSTS2 OSTS1 OSTS0
fXP = 20 MHz
102.4
μ
s
409.6
μ
s
819.2
μ
s
Cautions 1. If the STOP mode is entered and then released while the internal oscillation
clock is being used as the CPU clock, set the oscillation stabilization time as
follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
2. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remark fXP: X1 input clock oscillation frequency
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(7) System wait control register (VSWC)
This register is used to control wait states when a high-speed CPU and a low-speed peripheral I/O are connected.
VSWC can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-8. Format of System Wait Control Register (VSWC)
Address: FFFDH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
VSWC 0 0 0 0 0 0 PDW1 0
PDW1 Control of system clock data wait
0 No wait
1 Two wait states inserted
Cautions 1. Be sure to insert two wait states if the minimum instruction execution time is
μ
0.125
s or less (fXP = 16 MHz or more).
2. Be sure to clear bits 0 and 2 to 7 to 0.
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CHAPTER 5 CLOCK GENERATOR
5.4 System Clock Oscillator
5.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 20 MHz) connected to the X1
and X2 pins.
An external clock can be input to the X1 oscillator. In this case, input the clock signal to the X1 pin and input the
inverse signal to the X2 pin.
Figure 5-9 shows examples of the external circuit of the X1 oscillator.
Figure 5-9. Examples of External Circuit of X1 Oscillator
(a) Crystal, ceramic oscillation (b) External clock
V
SS
X1
X2
Crystal resonator or
ceramic resonator
Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
Figure 5-9 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
External
clock
X1
X2
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5.4.2 Examples of Incorrect Resonator Connection
Figure 5-10 shows examples of incorrect resonator connection.
Figure 5-10. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring (b) Crossed signal line
PORT
SS
X1 X1V
X2V
SS
X2
(c) Wiring near high alternating current (d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
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Figure 5-10. Examples of Incorrect Resonator Connection (2/2)
(e) Signals are fetched
V
SS
X1 X2
CHAPTER 5 CLOCK GENERATOR
5.4.3 Internal oscillator
μ
Internal oscillator is incorporated in the
PD78F0714.
“Can be stopped by software” or “Cannot be stopped” can be selected by an option byte. The internal oscillation
clock always oscillates after RESET release (240 kHz (TYP.)).
5.4.4 Prescaler
The prescaler generates various clocks by dividing the X1 oscillator output when the X1 input clock is selected as
the source clock to the CPU.
Caution When the internal oscillation clock is selected as the source clock to the CPU, the prescaler
generates various clocks by dividing the internal oscillator output (f
X = 240 kHz (TYP.)).
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CHAPTER 5 CLOCK GENERATOR
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode.
• X1 input clock f
• Internal oscillation clock f
• CPU clock f
• Clock to peripheral hardware
The CPU starts operation when the on-chip internal oscillator starts outputting after reset release in the
μ
PD78F0714, thus enabling the following.
(1) Enhancement of security function
When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input
clock is damaged or badly connected and therefore does not operate after reset is released. However, the start
clock of the CPU is the on-chip internal oscillation clock, so the device can be started by the internal oscillation
clock after reset release. Consequently, the system can be safely shut down by performing a minimum operation,
such as acknowledging a reset source by software or performing safety processing when there is a malfunction.
(2) Improvement of performance
Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total
performance can be improved.
A timing diagram of the CPU default start using internal oscillator is shown in Figure 5-11.
XP
R
CPU
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X1 input clock
XP
)
(f
Internal oscillation
clock (f
R
)
CHAPTER 5 CLOCK GENERATOR
Figure 5-11. Timing Diagram of CPU Default Start Using Internal Oscillator
RESET
CPU clock
Internal oscillation clock
Operation
stopped: 17/f
X1 oscillation stabilization time: 211/fXP to 216/f
R
Note
XP
Switched by software
X1 input clock
Note Check using the oscillation stabilization time counter status register (OSTC).
(a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is cleared to 0 and the
internal oscillation clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of
the internal oscillation clock have elapsed after RESET release (or clock supply to the CPU stops for 17
clocks). During the RESET period, oscillation of the X1 input clock and internal oscillation clock is stopped.
(b) After RESET release, the CPU clock can be switched from the internal oscillation clock to the X1 input clock
using bit 0 (MCM0) of the main clock mode register (MCM) after the X1 input clock oscillation stabilization
time has elapsed. At this time, check the oscillation stabilization time using the oscillation stabilization time
counter status register (OSTC) before switching the CPU clock. The CPU clock status can be checked using
bit 1 (MCS) of MCM.
(c) Internal oscillator can be set to stopped/oscillating using the internal oscillation mode register (RCM) when
“Can be stopped by software” is selected for the internal oscillation clock by an option byte, if the X1 input
clock is used as the CPU clock. Make sure that MCS is 1 at this time.
(d) When internal oscillation clock is used as the CPU clock, the X1 input clock can be set to stopped/oscillating
using the main OSC control register (MOC). Make sure that MCS is 0 at this time.
(e) The oscillation stabilization time (2
11
/fXP, 213/fXP, 214/fXP, 215/fXP, 216/fXP) selected by the oscillation stabilization
time select register (OSTS) is secured when releasing STOP mode while the X1 input clock is being used as
the CPU clock.
In addition, when RESET is released, and when the STOP mode is released while the internal oscillation
clock is being used as the CPU clock, there is no oscillation stabilization time wait.
When switching to the X1 input clock as the CPU clock, check the oscillation stabilization time by using the
oscillation stabilization time counter status register (OSTC).
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A status transition diagram of this product is shown in Figure 5-12, and the relationship between the operation
clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown
in Tables 5-3 and 5-4, respectively.
Figure 5-12. Status Transition Diagram (1/2)
(1) When “Internal oscillator can be stopped by software” is selected by option byte
Note 4
HALT
Interrupt
instruction
Interrupt
Interrupt
HALT
instruction
HALT instruction
HALT
instruction
InterruptHALT
Status 4
CPU clock: f
f
XP
: Oscillating
XP
fR: Oscillation stopped
RSTOP = 0
RSTOP = 1
Note 1
Status 3
CPU clock: f
fXP: Oscillating
f
R
: Oscillating
XP
MCM0 = 0
MCM0 = 1
Note 2
Status 2
CPU clock: f
fXP: Oscillating
f
R
: Oscillating
MSTOP = 1
R
MSTOP = 0
Note 3
Status 1
CPU clock: f
fXP: Oscillation stopped
fR: Oscillating
STOP
Interrupt
STOP
instruction
Interrupt
STOP
instruction
Interrupt
instruction
Interrupt
STOP
instruction
Note 4
STOP
Reset release
Note 5
Reset
Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
2. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
3. When shifting from status 2 to status 1, make sure that MCS is 0.
4. When “Internal oscillator can be stopped by software” is selected by an option byte, the watchdog
timer stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog
timer. However, oscillation of internal oscillator does not stop even in the HALT and STOP modes if
RSTOP = 0.
5. All reset sources (RESET input, POC, LVI, and WDT)
R
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CHAPTER 5 CLOCK GENERATOR
Figure 5-12. Status Transition Diagram (2/2)
(2) When “Internal oscillator cannot be stopped” is selected by option byte
HALT
Interrupt
HALT
Interrupt
HALT
instruction
Interrupt
HALT instruction
instruction
Status 3
CPU clock: f
f
XP
: Oscillating
f
R
: Oscillating
XP
MCM0 = 0
MCM0 = 1
Note 1
Status 2
CPU clock: f
fXP: Oscillating
f
R
: Oscillating
R
MSTOP = 1
MSTOP = 0
Note 2
Status 1
CPU clock: f
fXP: Oscillation stopped
fR: Oscillating
R
STOP
instruction
Reset release
Interrupt
Reset
Note 4
STOP
instruction
Interrupt
STOP
instruction
STOP
Interrupt
Note 3
Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
2. When shifting from status 2 to status 1, make sure that MCS is 0.
3. The watchdog timer operates using Internal oscillation clock even in STOP mode if “Internal oscillator
cannot be stopped” is selected by an option byte. Internal oscillation clock division can be selected
as the count source of 8-bit timer 51 (TM51), so clear the watchdog timer using the TM51 interrupt
request before watchdog timer overflow. If this processing is not performed, an internal reset signal
is generated at watchdog timer overflow after STOP instruction execution.
4. All reset sources (RESET input, POC, LVI, and WDT)
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Table 5-3. Relationship Between Operation Clocks in Each Operation Status
Status
Operation
Mode
Reset Stopped
STOP
HALT Oscillating
X1 Oscillator Internal Oscillator
MSTOP = 0 MSTOP = 1
Stopped
Stopped
Note 3
Note 1
RSTOP = 0 RSTOP = 1
Oscillating Oscillating
Note 2
Stopped
Note 4
CPU Clock After
Internal oscillation
clock
Note 5 Stopped
Note 6
Release
Prescaler Clock
Supplied to Peripherals
MCM0 = 0 MCM0 = 1
Stopped
Internal
oscillation
clock
X1
Notes 1. When “Cannot be stopped” is selected for internal oscillator by an option byte.
2. When “Can be stopped by software” is selected for internal oscillator by an option byte.
3. Only when internal oscillator is oscillating.
4. Only when X1 oscillator is oscillating.
5. Operates using the CPU clock at STOP instruction execution.
6. Operates using the CPU clock at HALT instruction execution.
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for internal oscillator by
an option byte.
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
RSTOP: Bit 0 of the internal oscillation mode register (RCM)
MCM0: Bit 0 of the main clock mode register (MCM)
Table 5-4. Oscillation Control Flags and Clock Oscillation Status
X1 Oscillator Internal Oscillator
RSTOP = 0 Stopped Oscillating MSTOP = 1
RSTOP = 1 Setting prohibited
RSTOP = 0 Oscillating MSTOP = 0
RSTOP = 1
Oscillating
Stopped
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for internal
oscillator by an option byte.
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
RSTOP: Bit 0 of the internal oscillation mode register (RCM)
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