NEC PD78054Y, uPD78058Y, uPD78P054, PD78058Y, uPD78056 User Manual

User’s Manual

µ

PD78054, 78054Y SUBSERIES

8-BIT SINGLE-CHIP MICROCONTROLLERS

µ

PD78052

µ

PD78053

µ

PD78054

µ

PD78P054

µ

PD78055

µ

PD78056

µ

PD78058

µ

PD78P058

µ

PD78052(A)

µ

PD78053(A)

µ

PD78054(A)

Document No. U11747EJ5V0UM00 (5th edition)
Date Published April 1998 N CP (K)

µ

PD78052Y

µ

PD78053Y

µ

PD78054Y

µ

PD78055Y

µ

PD78056Y

µ

PD78058Y

µ

PD78P058Y

©

Printed in Japan

1992

[MEMO]

2

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

DD or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

3

FIP, EEPROM, IEBus, QTOP are trademarks of NEC Corporation.
MS-DOS, Windows, and Widows NT are either registered trademarks or trademarks of Microsoft
Corporation in the United States and/or other countries.
IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Sun OS is a trademark of Sun Microsystems, Inc.
Ethernet is a trademark of XEROX Corporation.
NEWS and NEWS-OS are trademarks of SONY Corporation.
OSF/Motif is a trademark of Open Software Foundation, Inc.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

License not needed:µPD78P054KK-T, 78P058KK-T, 78P058YKK-T
The customer must judge the need for license:

µ

PD78052GC-×××-8BT, 78052GK-×××-BE9, 78052YGC-×××-8BT

µ

PD78053GC-×××-8BT, 78053GK-×××-BE9, 78053YGC-×××-8BT

µ

PD78054GC-×××-8BT, 78054GK-×××-BE9, 78054YGC-×××-8BT

µ

PD78P054GC-3B9, 78P054GC-8BT, 78P054GK-BE9

µ

PD78055GC-×××-8BT, 78055GK-×××-BE9, 78055YGC-×××-8BT

µ

PD78056GC-×××-8BT, 78056GK-×××-BE9, 78056YGC-×××-8BT

µ

PD78058GC-×××-8BT, 78058GK-×××-BE9, 78058YGC-×××-8BT

µ

PD78P058GC-8BT, 78P058YGC-8BT

µ

PD78052GC(A)-×××-3B9, 78053GC(A)-×××-3B9, 78054GC(A)-×××-3B9

4

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these

components in an I

2

C system, provided that the system conforms to the I2C Standard Specification as defined

by Philips.

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard”, “Special”, and “Specific”. The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program” for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M7 96.5

5

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: [phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil
Tel: [phone]
Fax: [phone]

J98. 2

6

Major Revisions in This Edition

Page Description

Throughout Addition of µPD78052(A),78053(A), 78054(A) to the applicable types

Deletion of µPD78P054Y from the applicable types
Deletion of the following package from the µPD78052, 78053, 78054, 78055, 78056, 78058, 78P058, 78054Y
Subseries:

• 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)
p. 233 Addition of Figure 9-10. Square-Wave Output Operation Timing
p. 238 Addition of Figure 9-13. Square-Wave Output Operation Timing
p. 296 Addition of Note to Figure 16-4. Serial Operating Mode Register 0 Format
p. 430, 435 Addition of (4) Synchronization control and (5) Automatic transmit/receive Interval time to 18.4.3 3-wire

serial I/O mode operation with automatic transmit/receive function

p. 439 Addition of precaution to 19.1 (3) 3-wire serial I/O mode (MSB-/LSB-first switchable)
p. 444 Change of Figure 19-3. Serial Operating Mode Register 2 Format
p. 446 Change of Table 19-2. Serial Interface Channel 2 Operating Mode Settings
p. 465 Correction of Figure 19-10. Receive Error Timing
p. 474 Addition of 19.4.4 Limitations when UART mode is used
p. 577, 578 Addition of APPENDIX A DIFFERENCES BETWEEN µPD78054, 78054Y SUBSERIES AND µPD78058F,

78058FY SUBSERIES

p. 579 to APPENDIX B DEVELOPMENT TOOL

592 Entire revision: Support for in-circuit emulator IE-78K0-NS

p. 593, 594 APPENDIX C EMBEDDED SOFTWARE

Entire revision: Deletion of fuzzy inference development support system

The mark shows major revised points.

7

[MEMO]

8

PREFACE

Readers This manual has been prepared for user engineers who want to understand the

functions of the µPD78054 and 78054Y Subseries and design and develop its
application systems and programs.
The target products are the products of the following subseries.

µ

PD78054 Subseries :µPD78052, 78053, 78054, 78P054, 78055, 78056,

•

µ

PD78058, 78P058, 78052(A), 78053(A), 78054(A)

• µPD78054Y Subseries :µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y,

µ

PD78058Y, 78P058Y

Caution Of the above members, the following devices with the suffix KK-T should be

used only for experiment or function evaluation, because they are not intended
for use in equipment that will be mass-produced and require high reliability.

µ

PD78P054KK-T, 78P058KK-T, 78P058YKK-T

Purpose This manual is intended for users to understand the functions described in the

Organization below.

Organization The

and the instruction edition (common to the 78K/0 Series).

Pin functions CPU functions
Internal block functions Instruction set
Interrupt Explanation of each instruction
Other on-chip peripheral functions

µ

PD78054, 78054Y Subseries manual is separated into two parts: this manual

µ

PD78054, 78054Y 78K/0 Series

Subseries User’s Manual

User’s Manual Instruction

(This manual)

9

How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic

circuits and microcontrollers.

For users who use this document as the manual for the µPD78052(A), 78053(A),
and 78054(A):

µ

→ The only differences between the

µ

PD78052(A), 78053(A), 78054(A) are the quality grades and packages. (refer
to 1.9 Differences between Standard Quality Grade Products and (A) Products).
For the (A) products, read the part numbers in the following manner.

µ

PD78052 → µPD78052(A)

µ

PD78053 → µPD78053(A)

µ

PD78054 → µPD78054(A)
When you want to understand the functions in general:
→ Read this manual in the order of the contents.
To know the µPD78054 and 78054Y Subseries instruction function in detail:
→ Refer to the 78K/0 Series User's Manual: Instructions (U12326E)
How to interpret the register format:

For the circled bit number, the bit name is defined as a reserved word in

→

RA78K/
To learn the function of a register whose register name is known:
→ Refer to Appendix D Register Index.
To know the electrical specifications of the µPD78054 and 78054Y Subseries:
→ Refer to separately available Data Sheet.
To know application examples of the functions provided in the µPD78054 and
78054Y Subseries:
→ Refer to Application Note separately provided.

0, and in CC78K/0, already defined in the header file named sfrbit.h.

PD78052, 78053, and 78054 and the

Caution The application examples in this manual are created for “Standard” quality

grade products for general electric equipment. When using the application
examples in this manual for purposes which require “Special” quality grades,
thoroughly examine the quality grade of each part and circuit actually used.

10

Chapter Organization: This manual divides the descriptions for the µPD78054 and 78054Y Subseries into different

chapters as shown below. Read only the chapters related to the device you use.

µ

Chapter

Chapter 1 Outline (µPD78054 Subseries) √ —
Chapter 2 Outline (µPD78054Y Subseries) — √
Chapter 3 Pin Function (µPD78054 Subseries) √ —
Chapter 4 Pin Function (µPD78054Y Subseries) — √
Chapter 5 CPU Architecture √√
Chapter 6 Port Functions √√

Chapter 7 Clock Generator √√
Chapter 8 16-Bit Timer/Event Counter √√
Chapter 9 8-Bit Timer/Event Counters 1 and 2 √√
Chapter 10 Watch Timer √√
Chapter 11 Watchdog Timer √√
Chapter 12 Clock Output Control Circuit √√
Chapter 13 Buzzer Output Control Circuit √√
Chapter 14 A/D Converter √√
Chapter 15 D/A Converter √√
Chapter 16 Serial Interface Channel 0 (µPD78054 Subseries) √ —
Chapter 17 Serial Interface Channel 0 (µPD78054Y Subseries) — √
Chapter 18 Serial Interface Channel 1 √√
Chapter 19 Serial Interface Channel 2 √√
Chapter 20 Real-Time Output Port √√
Chapter 21 Interrupt and Test Functions √√
Chapter 22 External Device Expansion Function √√
Chapter 23 Standby Function √√
Chapter 24 Reset Function √√
Chapter 25 ROM Correction √√
Chapter 26µPD78P054, µPD78P058 √√
Chapter 27 Instruction Set √√

PD78054µPD78054Y

Subseries Subseries

11

Differences between µPD78054 and µPD78054Y Subseries:

The µPD78054 and µPD78054Y Subseries are different in the following functions
of the serial interface channel 0.

Modes of serial interface channel 0

3-wire serial I/O mode √√
2-wire serial I/O mode √√
SBI (serial bus interface) mode √ —

I2C (Inter IC) bus mode — √
√ : Supported
— : Not supported

µ

PD78054

Subseries Subseries

Legend Data significant : Left: higher digit, right: lower digit

Active low : ××× (top bar over pin or signal name)
Note : Footnote
Caution : Important information
Remark : Supplement
Numerical notation : Binary ... ×××× or ××××B

Decimal ... ××××
Hexadecimal ... ××××H

µ

PD78054Y

12

Related Documents The related documents indicated in this publication may include preliminary

versions. However, preliminary versions are not marked as such.

Related documents for µPD78054 Subseries

Document name

µ

PD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet U12327J U12327E

µ

PD78052(A), 78053(A), 78054(A) Data Sheet U12171J U12171E

µ

PD78P054, 78P058 Data Sheet U10417J U10417E

µ

PD78054, 78054Y Subseries User’s Manual U11747J This manual
78K/0 Series User’s Manual, Instruction U12326J U12326E
78K/0 Series Instruction Table U10903J —
78K/0 Series Instruction Set U10904J —

µ

PD78054 Subseries Special Function Register Table U10102J —
78K/0 Series Application Note Basics (III) U10182J U10182E

Floating-point operation program IEA-718 IEA-1289

Document No.

Japanese English

Related documents for µPD78054Y Subseries

Document name

µ

PD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y Data Sheet U10906J U10906E

µ

PD78P058Y Data Sheet U10907J U10907E

µ

PD78054, 78054Y Subseries User’s Manual U11747J This manual
78K/0 Series User’s Manual, Instruction U12326J U12326E

78K/0 Series Instruction Table U10903J —
78K/0 Series Instruction Set U10904J —

µ

PD78054Y Subseries Special Function Register Table U10087J —
78K/0 Series Application Note Basics (III) U10182J U10182E

Document No.

Japanese English

Caution The above documents are subject to change without prior notice. Be sure to use the latest version

document when starting design.

13

Development Tool Documents (User’s Manuals)

Document name

RA78K0 Assembler Package Operation U11802J U11802E

Assembly Language U11801J U11801E

Structured Assembly U11789J U11789E
RA78K Series Structured Assembler Preprocessor U12323J EEU-1402
CC78K0 C Compiler Operation U11517J U11517E

Language U11518J U11518E
CC78K0 C Compiler Application Note Programming know-how U13034J EEA-1208
CC78K Series Library Source File U12322J —
PG-1500 PROM Programmer U11940J U11940E
PG-1500 Controller PC-9800 Series (MS-DOS™) Base EEU-704 EEU-1291
PG-1500 Controller IBM PC Series (PC DOS™) Base EEU-5008 U10540E

IE-78K0-NS
IE-78001-R-A
IE-780308-NS-EM1

IE-780308-R-EM U11362J U11362E
EP-78230 EEU-985 EEU-1515
EP-78054GK-R EEU-932 EEU-1468
SM78K0 System Simulator Windows™ Base Reference U10181J U10181E
SM78K Series System Simulator External component user U10092J U10092E

open interface specifications
ID78K0-NS Integrated Debugger Reference U12900J

To be prepared To be prepared
To be prepared To be prepared
To be prepared To be prepared

Document No.

Japanese English

To be prepared

ID78K0 Integrated Debugger EWS Base Reference U11151J —
ID78K0 Integrated Debugger PC Base Reference U11539J U11539E
ID78K0 Integrated Debugger Windows Base Guide U11649J U11649E

Caution The above documents are subject to change without prior notice. Be sure to use the latest version

document when starting design.

14

Documents for Embedded Software (User’s Manual)

Document name

78K/0 Series Real-Time OS Basics U11537J U11537E

Installation U11536J U11536E

OS for 78K/0 Series MX78K0 Basics U12257J U12257E

Document No.

Japanese English

Other Documents

Document name

IC PACKAGE MANUAL C10943X
Semiconductor Device Mounting Technology Manual C10535J C10535E

Quality Grade on NEC Semiconductor Devices C11531J C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E
Guide to Quality Assurance for Semiconductor Devices — MEI-1202
Microcontroller Related Product Guide—Third Party Manufacturers U11416J —

Document No.

Japanese English

Caution The above documents are subject to change without prior notice. Be sure to use the latest version

document when starting design.

15

[MEMO]

16

TABLE OF CONTENTS

CHAPTER 1 GENERAL (µPD78054 Subseries) ............................................................................ 37

1.1 Features ............................................................................................................................. 37

1.2 Applications ...................................................................................................................... 38

1.3 Ordering Information ........................................................................................................ 38

1.4 Quality Grade .................................................................................................................... 39

1.5 Pin Configuration (Top View)........................................................................................... 40

1.6 78K/0 Series Expansion ................................................................................................... 43

1.7 Block Diagram ................................................................................................................... 45

1.8 Outline of Function ........................................................................................................... 46

1.9 Differences between Standard Quality Grade Products and (A) Products ................. 48

1.10 Mask Options .................................................................................................................... 48

CHAPTER 2 GENERAL (µPD78054Y Subseries).......................................................................... 49

2.1 Features ............................................................................................................................. 49

2.2 Applications ...................................................................................................................... 50

2.3 Ordering Information ........................................................................................................ 50

2.4 Quality Grade .................................................................................................................... 50

2.5 Pin Configuration (Top View)........................................................................................... 51

2.6 78K/0 Series Expansion ................................................................................................... 54

2.7 Block Diagram ................................................................................................................... 56

2.8 Outline of Function ........................................................................................................... 57

2.9 Mask Options .................................................................................................................... 58

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) .................................................................... 59

3.1 Pin Function List ............................................................................................................... 59

3.1.1 Normal operating mode pins ............................................................................................... 59

3.1.2 PROM programming mode pins (PROM versions only) ...................................................... 63

3.2 Description of Pin Functions ........................................................................................... 64

3.2.1 P00 to P07 (Port 0) .............................................................................................................. 64

3.2.2 P10 to P17 (Port 1) .............................................................................................................. 65

3.2.3 P20 to P27 (Port 2) .............................................................................................................. 65

3.2.4 P30 to P37 (Port 3) .............................................................................................................. 66

3.2.5 P40 to P47 (Port 4) .............................................................................................................. 67

3.2.6 P50 to P57 (Port 5) .............................................................................................................. 67

3.2.7 P60 to P67 (Port 6) .............................................................................................................. 67

3.2.8 P70 to P72 (Port 7) .............................................................................................................. 68

3.2.9 P120 to P127 (Port 12) ........................................................................................................ 69

3.2.10 P130 and P131 (Port 13) ..................................................................................................... 69

3.2.11 AV

3.2.12 AVREF1 .................................................................................................................................. 69

3.2.13 AV

3.2.14 AVSS ..................................................................................................................................... 70

3.2.15 RESET................................................................................................................................. 70

3.2.16 X1 and X2 ............................................................................................................................ 70

3.2.17 XT1 and XT2 ....................................................................................................................... 70

REF0 .................................................................................................................................. 69

DD ..................................................................................................................................... 70

17

3.2.18 V

DD ....................................................................................................................................... 70

3.2.19 VSS ....................................................................................................................................... 70

3.2.20 V

PP (PROM versions only) ................................................................................................... 70

3.2.21 IC (Mask ROM version only)................................................................................................70

3.3 Input/output Circuits and Recommended Connection of Unused Pins ...................... 71

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries).................................................................. 75

4.1 Pin Function List ............................................................................................................... 75

4.1.1 Normal operating mode pins ............................................................................................... 75

4.1.2 PROM programming mode pins (PROM versions only) ...................................................... 79

4.2 Description of Pin Functions ........................................................................................... 80

4.2.1 P00 to P07 (Port 0) .............................................................................................................. 80

4.2.2 P10 to P17 (Port 1) .............................................................................................................. 81

4.2.3 P20 to P27 (Port 2) .............................................................................................................. 81

4.2.4 P30 to P37 (Port 3) .............................................................................................................. 82

4.2.5 P40 to P47 (Port 4) .............................................................................................................. 82

4.2.6 P50 to P57 (Port 5) .............................................................................................................. 83

4.2.7 P60 to P67 (Port 6) .............................................................................................................. 83

4.2.8 P70 to P72 (Port 7) .............................................................................................................. 84

4.2.9 P120 to P127 (Port 12) ........................................................................................................ 84

4.2.10 P130 and P131 (Port 13) ..................................................................................................... 85

4.2.11 AV

REF0 .................................................................................................................................. 85

4.2.12 AVREF1 .................................................................................................................................. 85

4.2.13 AV

DD ..................................................................................................................................... 85

4.2.14 AVSS ..................................................................................................................................... 85

4.2.15 RESET................................................................................................................................. 85

4.2.16 X1 and X2 ............................................................................................................................ 86

4.2.17 XT1 and XT2 ....................................................................................................................... 86

4.2.18 V

4.2.19 V

DD ....................................................................................................................................... 86

SS ....................................................................................................................................... 86

4.2.20 VPP (PROM versions only) ................................................................................................... 86

4.2.21 IC (Mask ROM version only)................................................................................................86

4.3 Input/output Circuits and Recommended Connection of Unused Pins ...................... 87

CHAPTER 5 CPU ARCHITECTURE................................................................................................ 91

5.1 Memory Spaces................................................................................................................. 91

5.1.1 Internal program memory space.......................................................................................... 99

5.1.2 Internal data memory space ................................................................................................ 100

5.1.3 Special Function Register (SFR) area ................................................................................. 100

5.1.4 External memory space ....................................................................................................... 100

5.1.5 Data memory addressing .................................................................................................... 101

5.2 Processor Registers ......................................................................................................... 109

5.2.1 Control registers .................................................................................................................. 109

5.2.2 General registers ................................................................................................................. 112

5.2.3 Special Function Register (SFR) ......................................................................................... 114

5.3 Instruction Address Addressing ..................................................................................... 118

5.3.1 Relative addressing ............................................................................................................. 118

5.3.2 Immediate addressing ......................................................................................................... 119

18

5.3.3 Table indirect addressing..................................................................................................... 120

5.3.4 Register addressing............................................................................................................. 120

5.4 Operand Address Addressing ......................................................................................... 121

5.4.1 Implied addressing .............................................................................................................. 121

5.4.2 Register addressing............................................................................................................. 122

5.4.3 Direct addressing................................................................................................................. 123

5.4.4 Short direct addressing........................................................................................................ 124

5.4.5 Special-Function Register (SFR) addressing ...................................................................... 125

5.4.6 Register indirect addressing ................................................................................................ 126

5.4.7 Based addressing ................................................................................................................ 127

5.4.8 Based indexed addressing .................................................................................................. 128

5.4.9 Stack addressing ................................................................................................................. 128

CHAPTER 6 PORT FUNCTIONS .................................................................................................... 129

6.1 Port Functions................................................................................................................... 129

6.2 Port Configuration ............................................................................................................ 134

6.2.1 Port 0 ................................................................................................................................... 134

6.2.2 Port 1 ................................................................................................................................... 136

µ

6.2.3 Port 2 (

6.2.4 Port 2 (µPD78054Y Subseries) ........................................................................................... 139

6.2.5 Port 3 ................................................................................................................................... 141

6.2.6 Port 4 ................................................................................................................................... 142

6.2.7 Port 5 ................................................................................................................................... 143

6.2.8 Port 6 ................................................................................................................................... 144

6.2.9 Port 7 ................................................................................................................................... 146

6.2.10 Port 12 ................................................................................................................................. 148

6.2.11 Port 13 ................................................................................................................................. 149

PD78054 Subseries).............................................................................................. 137

6.3 Port Function Control Registers ..................................................................................... 150

6.4 Port Function Operations................................................................................................. 156

6.4.1 Writing to input/output port................................................................................................... 156

6.4.2 Reading from input/output port ............................................................................................ 156

6.4.3 Operations on input/output port ........................................................................................... 157

6.5 Selection of Mask Option ................................................................................................. 157

CHAPTER 7 CLOCK GENERATOR................................................................................................ 159

7.1 Clock Generator Functions .............................................................................................. 159

7.2 Clock Generator Configuration ....................................................................................... 159

7.3 Clock Generator Control Register ................................................................................... 161

7.4 System Clock Oscillator ................................................................................................... 165

7.4.1 Main system clock oscillator ................................................................................................ 165

7.4.2 Subsystem clock oscillator .................................................................................................. 166

7.4.3 Scaler................................................................................................................................... 168

7.4.4 When no subsystem clocks are used .................................................................................. 168

7.5 Clock Generator Operations ............................................................................................ 169

7.5.1 Main system clock operations ............................................................................................. 170

7.5.2 Subsystem clock operations ................................................................................................ 171

7.6 Changing System Clock and CPU Clock Settings ......................................................... 171

7.6.1 Time required for switchover between system clock and CPU clock .................................. 171

7.6.2 System clock and CPU clock switching procedure.............................................................. 173

19

CHAPTER 8 16-BIT TIMER/EVENT COUNTER ............................................................................. 175

8.1 Outline of Timers Incorporated in the µPD78054, 78054Y Subseries .......................... 175

8.2 16-Bit Timer/Event Counter Functions ........................................................................... 177

8.3 16-Bit Timer/Event Counter Configuration ..................................................................... 179

8.4 16-Bit Timer/Event Counter Control Registers .............................................................. 182

8.5 16-Bit Timer/Event Counter Operations.......................................................................... 191

8.5.1 Interval timer operations ...................................................................................................... 191

8.5.2 PWM output operations ....................................................................................................... 193

8.5.3 PPG output operations ........................................................................................................ 196

8.5.4 Pulse width measurement operations ................................................................................. 197

8.5.5 External event counter operation......................................................................................... 204

8.5.6 Square-wave output operation ............................................................................................ 206

8.5.7 One-shot pulse output operation ......................................................................................... 208

8.6 16-Bit Timer/Event Counter Operating Precautions ...................................................... 212

CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 .............................................................. 215

9.1 8-Bit Timer/Event Counters 1 and 2 Functions .............................................................. 215

9.1.1 8-bit timer/event counter mode ............................................................................................ 215

9.1.2 16-bit timer/event counter mode .......................................................................................... 218

9.2 8-Bit Timer/Event Counters 1 and 2 Configurations...................................................... 220

9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers ................................................. 223

9.4 8-Bit Timer/Event Counters 1 and 2 Operations ............................................................ 228

9.4.1 8-bit timer/event counter mode ............................................................................................ 228

9.4.2 16-bit timer/event counter mode .......................................................................................... 234

9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2 .......................................................... 238

CHAPTER 10 WATCH TIMER ........................................................................................................... 241

10.1 Watch Timer Functions .................................................................................................... 241

10.2 Watch Timer Configuration .............................................................................................. 242

10.3 Watch Timer Control Registers ....................................................................................... 242

10.4 Watch Timer Operations................................................................................................... 246

10.4.1 Watch timer operation.......................................................................................................... 246

10.4.2 Interval timer operation ........................................................................................................ 246

CHAPTER 11 WATCHDOG TIMER ................................................................................................... 247

11.1 Watchdog Timer Functions.............................................................................................. 247

11.2 Watchdog Timer Configuration ....................................................................................... 249

11.3 Watchdog Timer Control Registers................................................................................. 250

11.4 Watchdog Timer Operations ............................................................................................ 253

11.4.1 Watchdog timer operation.................................................................................................... 253

11.4.2 Interval timer operation........................................................................................................ 254

CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT ..................................................................... 255

12.1 Clock Output Control Circuit Functions ......................................................................... 255

12.2 Clock Output Control Circuit Configuration................................................................... 256

12.3 Clock Output Function Control Registers...................................................................... 257

20

CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT.................................................................... 261

13.1 Buzzer Output Control Circuit Functions ............................................................................. 261

13.2 Buzzer Output Control Circuit Configuration ....................................................................... 261

13.3 Buzzer Output Function Control Registers .......................................................................... 262

CHAPTER 14 A/D CONVERTER....................................................................................................... 265

14.1 A/D Converter Functions.................................................................................................. 265

14.2 A/D Converter Configuration ........................................................................................... 265

14.3 A/D Converter Control Registers..................................................................................... 269

14.4 A/D Converter Operations................................................................................................ 273

14.4.1 Basic operations of A/D converter ....................................................................................... 273

14.4.2 Input voltage and conversion results ................................................................................... 275

14.4.3 A/D converter operating mode............................................................................................. 276

14.5 A/D Converter Cautions ................................................................................................... 278

CHAPTER 15 D/A CONVERTER....................................................................................................... 281

15.1 D/A Converter Functions.................................................................................................. 281

15.2 D/A Converter Configuration ........................................................................................... 282

15.3 D/A Converter Control Registers..................................................................................... 284

15.4 Operations of D/A Converter ........................................................................................... 285

15.5 Cautions Related to D/A Converter ................................................................................. 286

CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)...................................... 287

16.1 Serial Interface Channel 0 Functions.............................................................................. 288

16.2 Serial Interface Channel 0 Configuration ....................................................................... 290

16.3 Serial Interface Channel 0 Control Registers................................................................. 294

16.4 Serial Interface Channel 0 Operations............................................................................ 301

16.4.1 Operation stop mode ........................................................................................................... 301

16.4.2 3-wire serial I/O mode operation ......................................................................................... 302

16.4.3 SBI mode operation ............................................................................................................. 307

16.4.4 2-wire serial I/O mode operation ......................................................................................... 333

16.4.5 SCK0/P27 pin output manipulation...................................................................................... 339

CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) ................................... 341

17.1 Serial Interface Channel 0 Functions.............................................................................. 342

17.2 Serial Interface Channel 0 Configuration ....................................................................... 344

17.3 Serial Interface Channel 0 Control Registers................................................................. 348

17.4 Serial Interface Channel 0 Operations............................................................................ 356

17.4.1 Operation stop mode ........................................................................................................... 356

17.4.2 3-wire serial I/O mode operation ......................................................................................... 357

17.4.3 2-wire serial I/O mode operation ......................................................................................... 361

2

17.4.4 I

17.4.5 Cautions on use of I2C bus mode ........................................................................................ 385

17.4.6 Restrictions in I2C bus mode ............................................................................................... 388

17.4.7 SCK0/SCL/P27 pin output manipulation.............................................................................. 390

C bus mode operation ....................................................................................................... 367

21

CHAPTER 18 SERIAL INTERFACE CHANNEL 1 ............................................................................ 393

18.1 Serial Interface Channel 1 Functions.............................................................................. 393

18.2 Serial Interface Channel 1 Configuration ....................................................................... 394

18.3 Serial Interface Channel 1 Control Registers................................................................. 397

18.4 Serial Interface Channel 1 Operations............................................................................ 405

18.4.1 Operation stop mode ........................................................................................................... 405

18.4.2 3-wire serial I/O mode operation ......................................................................................... 406

18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function ......................... 409

CHAPTER 19 SERIAL INTERFACE CHANNEL 2 ............................................................................ 439

19.1 Serial Interface Channel 2 Functions.............................................................................. 439

19.2 Serial Interface Channel 2 Configuration ....................................................................... 440

19.3 Serial Interface Channel 2 Control Registers................................................................. 444

19.4 Serial Interface Channel 2 Operation.............................................................................. 452

19.4.1 Operation stop mode ........................................................................................................... 452

19.4.2 Asynchronous serial interface (UART) mode ...................................................................... 454

19.4.3 3-wire serial I/O mode ......................................................................................................... 467

19.4.4 Limitations when UART mode is used................................................................................. 474

CHAPTER 20 REAL-TIME OUTPUT PORT ...................................................................................... 477

20.1 Real-Time Output Port Functions.................................................................................... 477

20.2 Real-Time Output Port Configuration ............................................................................. 478

20.3 Real-Time Output Port Control Registers....................................................................... 480

CHAPTER 21 INTERRUPT AND TEST FUNCTIONS....................................................................... 483

21.1 Interrupt Function Types.................................................................................................. 483

21.2 Interrupt Sources and Configuration.............................................................................. 484

21.3 Interrupt Function Control Registers.............................................................................. 488

21.4 Interrupt Servicing Operations ........................................................................................ 497

21.4.1 Non-maskable interrupt request acknowledge operation .................................................... 497

21.4.2 Maskable interrupt request acknowledge operation ............................................................ 500

21.4.3 Software interrupt request acknowledge operation ............................................................. 503

21.4.4 Multiple interrupt servicing ................................................................................................... 503

21.4.5 Interrupt request reserve ..................................................................................................... 506

21.5 Test Functions................................................................................................................... 507

21.5.1 Registers controlling the test function.................................................................................. 507

21.5.2 Test input signal acknowledge operation............................................................................. 509

CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ......................................................... 511

22.1 External Device Expansion Functions............................................................................ 511

22.2 External Device Expansion Function Control Register................................................. 516

22.3 External Device Expansion Function Timing................................................................. 518

22.4 Example of Connection with Memory............................................................................. 523

CHAPTER 23 STANDBY FUNCTION................................................................................................ 525

23.1 Standby Function and Configuration.............................................................................. 525

23.1.1 Standby function .................................................................................................................. 525

23.1.2 Standby function control register ......................................................................................... 526

22

23.2 Standby Function Operations.......................................................................................... 527

23.2.1 HALT mode.......................................................................................................................... 527

23.2.2 STOP mode ......................................................................................................................... 530

CHAPTER 24 RESET FUNCTION..................................................................................................... 533

24.1 Reset Function.................................................................................................................. 533

CHAPTER 25 ROM CORRECTION................................................................................................... 537

25.1 ROM Correction Functions .............................................................................................. 537

25.2 ROM Correction Configuration........................................................................................ 537

25.3 ROM Correction Control Registers ................................................................................. 539

25.4 ROM Correction Application............................................................................................ 540

25.5 ROM Correction Example................................................................................................. 543

25.6 Program Execution Flow.................................................................................................. 544

25.7 Cautions on ROM Correction........................................................................................... 546

CHAPTER 26 µPD78P054, 78P058.................................................................................................. 547

26.1 Memory Size Switching Register (µPD78P054).............................................................. 549

26.2 Memory Size Switching Register (µPD78P058).............................................................. 550

26.3 Internal Expansion RAM Size Switching Register......................................................... 551

26.4 PROM Programming......................................................................................................... 552

26.4.1 Operating modes ................................................................................................................. 552

26.4.2 PROM write procedure ........................................................................................................ 554

26.4.3 PROM reading procedure.................................................................................................... 558

26.5 Erasure Procedure (µPD78P054KK-T and 78P058KK-T Only)...................................... 559

26.6 Opaque Film Masking the Window (µPD78P054KK-T and 78P058KK-T Only)............ 559

26.7 Screening of One-Time PROM Versions......................................................................... 559

CHAPTER 27 INSTRUCTION SET.................................................................................................... 561

27.1 Legends Used in Operation List...................................................................................... 562

27.1.1 Operand identifiers and description methods ...................................................................... 562

27.1.2 Description of “operation” column........................................................................................ 563

27.1.3 Description of “flag operation” column ................................................................................. 563

27.2 Operation List.................................................................................................................... 564

27.3 Instructions Listed by Addressing Type......................................................................... 572

APPENDIX A DIFFERENCES BETWEEN µPD78054, 78054Y SUBSERIES AND

µ

PD78058F, 78058FY SUBSERIES ........................................................................... 577

APPENDIX B DEVELOPMENT TOOLS............................................................................................ 579

B.1 Language Processing Software ...................................................................................... 582

B.2 PROM Writing Tools ......................................................................................................... 584

B.2.1 Hardware ............................................................................................................................. 584

B.2.2 Software............................................................................................................................... 584

B.3 Debugging Tools............................................................................................................... 585

B.3.1 Hardware ............................................................................................................................. 585

B.3.2 Software............................................................................................................................... 587

23

B.4 OS for IBM PC ................................................................................................................... 589

B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A .................. 589

APPENDIX C EMBEDDED SOFTWARE .......................................................................................... 593

APPENDIX D REGISTER INDEX...................................................................................................... 595

D.1 Register Index ................................................................................................................... 595

APPENDIX E REVISION HISTORY .................................................................................................. 599

24

LIST OF FIGURES (1/8)

Figure No. Title Page

3-1. Pin Input/Output Circuit of List....................................................................................................... 73

4-1. Pin Input/Output Circuit of List....................................................................................................... 89

µ

5-1. Memory Map (

5-2. Memory Map (µPD78053, 78053Y)............................................................................................... 92

5-3. Memory Map (

5-4. Memory Map (µPD78P054)........................................................................................................... 94

5-5. Memory Map (µPD78055, 78055Y)............................................................................................... 95

5-6. Memory Map (

5-7. Memory Map (µPD78058, 78058Y)............................................................................................... 97

5-8. Memory Map (µPD78P058, µPD78P058Y)................................................................................... 98

5-9. Data Memory Addressing (

5-10. Data Memory Addressing (µPD78053, 78053Y) ........................................................................... 102

5-11. Data Memory Addressing (µPD78054, 78054Y) ........................................................................... 103

5-12. Data Memory Addressing (

5-13. Data Memory Addressing (µPD78055, 78055Y) ........................................................................... 105

5-14. Data Memory Addressing (µPD78056, 78056Y) ........................................................................... 106

5-15. Data Memory Addressing (

5-16. Data Memory Addressing (µPD78P058, 78P058Y) ...................................................................... 108

5-17. Program Counter Configuration .................................................................................................... 109

5-18. Program Status Word Configuration ............................................................................................. 109

5-19. Stack Pointer Configuration........................................................................................................... 111

5-20. Data to be Saved to Stack Memory............................................................................................... 111

5-21. Data to be Reset from Stack Memory ........................................................................................... 111

5-22. General Register Configuration..................................................................................................... 113

PD78052, 78052Y)............................................................................................... 91

µ

PD78054, 78054Y)............................................................................................... 93

µ

PD78056, 78056Y)............................................................................................... 96

µ

PD78052, 78052Y) ........................................................................... 101

µ

PD78P054) ....................................................................................... 104

µ

PD78058, 78058Y) ........................................................................... 107

6-1. Port Types ..................................................................................................................................... 129

6-2. P00 and P07 Block Diagram ......................................................................................................... 135

6-3. P01 to P06 Block Diagram ............................................................................................................ 135

6-4. P10 to P17 Block Diagram ............................................................................................................ 136

6-5. P20, P21, P23 to P26 Block Diagram ........................................................................................... 137

6-6. P22 and P27 Block Diagram ......................................................................................................... 138

6-7. P20, P21, P23 to P26 Block Diagram ........................................................................................... 139

6-8. P22 and P27 Block Diagram ......................................................................................................... 140

6-9. P30 to P37 Block Diagram ............................................................................................................ 141

6-10. P40 to P47 Block Diagram ............................................................................................................ 142

6-11. Block Diagram of Falling Edge Detection Circuit........................................................................... 142

6-12. P50 to P57 Block Diagram ............................................................................................................ 143

6-13. P60 to P63 Block Diagram ............................................................................................................ 145

6-14. P64 to P67 Block Diagram ............................................................................................................ 145

6-15. P70 Block Diagram........................................................................................................................ 146

6-16. P71 and P72 Block Diagram ......................................................................................................... 147

6-17. P120 to P127 Block Diagram ........................................................................................................ 148

25

LIST OF FIGURES (2/8)

Figure No. Title Page

6-18. P130 and P131 Block Diagram ..................................................................................................... 149

6-19. Port Mode Register Format........................................................................................................... 152

6-20. Pull-Up Resistor Option Register Format ...................................................................................... 153

6-21. Memory Expansion Mode Register Format................................................................................... 154

6-22. Key Return Mode Register Format................................................................................................ 155

7-1. Block Diagram of Clock Generator ................................................................................................ 160

7-2. Subsystem Clock Feedback Resistor............................................................................................ 161

7-3. Processor Clock Control Register Format ..................................................................................... 162

7-4. Oscillation Mode Selection Register Format ................................................................................. 164

7-5. Main System Clock when Writing to OSMS .................................................................................. 164

7-6. External Circuit of Main System Clock Oscillator .......................................................................... 165

7-7. External Circuit of Subsystem Clock Oscillator ............................................................................. 166

7-8. Examples of Incorrect Oscillator Connection ................................................................................ 166

7-9. Main System Clock Stop Function ................................................................................................ 170

7-10. System Clock and CPU Clock Switching ...................................................................................... 173

8-1. 16-Bit Timer/Event Counter Block Diagram................................................................................... 179

8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram ............................................... 180

8-3. Timer Clock Selection Register 0 Format...................................................................................... 183

8-4. 16-Bit Timer Mode Control Register Format.................................................................................. 185

8-5. Capture/Compare Control Register 0 Format ............................................................................... 186

8-6. 16-Bit Timer Output Control Register Format................................................................................ 187

8-7. Port Mode Register 3 Format ........................................................................................................ 188

8-8. External Interrupt Mode Register 0 Format ................................................................................... 189

8-9. Sampling Clock Select Register Format........................................................................................ 190

8-10. Control Register Settings for Interval Timer Operation.................................................................. 191

8-11. Interval Timer Configuration Diagram............................................................................................ 192

8-12. Interval T imer Operation Timings .................................................................................................. 192

8-13. Control Register Settings for PWM Output Operation................................................................... 194

8-14. Example of D/A Converter Configuration with PWM Output ......................................................... 195

8-15. TV Tuner Application Circuit Example ........................................................................................... 195

8-16. Control Register Settings for PPG Output Operation.................................................................... 196

8-17. Control Register Settings for Pulse Width Measurement with Free-Running Counter and

One Capture Register ................................................................................................................... 197

8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter ........................ 198

8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter and

One Capture Register (with Both Edges Specified) ...................................................................... 198

8-20. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter ........ 199

8-21. Timing of Pulse Width Measurement Operation with Free-Running Counter

(with Both Edges Specified) .......................................................................................................... 200

8-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and

Two Capture Registers.................................................................................................................. 201

26

LIST OF FIGURES (3/8)

Figure No. Title Page

8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and

Two Capture Registers (with Rising Edge Specified).................................................................... 202

8-24. Control Register Settings for Pulse Width Measurement by Means of Restart............................. 203

8-25. Timing of Pulse Width Measurement Operation by Means of Restart

(with Rising Edge Specified) ......................................................................................................... 203

8-26. Control Register Settings in External Event Counter Mode .......................................................... 204

8-27. External Event Counter Configuration Diagram ............................................................................ 205

8-28. External Event Counter Operation Timings (with Rising Edge Specified) ..................................... 205

8-29. Control Register Settings in Square-Wave Output Mode .............................................................. 206

8-30. Square-Wave Output Operation Timing ........................................................................................ 207

8-31. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger............. 208

8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger ........................................... 209

8-33. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger.............. 210

8-34. Timing of One-Shot Pulse Output Operation Using External Trigger

(With Rising Edge Specified)......................................................................................................... 211

8-35. 16-Bit Timer Register Start Timing ................................................................................................ 212

8-36. Timings After Change of Compare Register During Timer Count Operation................................. 212

8-37. Capture Register Data Retention Timing....................................................................................... 213

8-38. Operation Timing of OVF0 Flag..................................................................................................... 214

9-1. 8-Bit Timer/Event Counters 1 and 2 Block Diagram...................................................................... 221

9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 .......................................... 222

9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 .......................................... 222

9-4. Timer Clock Select Register 1 Format........................................................................................... 224

9-5. 8-Bit Timer Mode Control Register 1 Format................................................................................. 225

9-6. 8-Bit Timer Output Control Register Format.................................................................................. 226

9-7. Port Mode Register 3 Format ........................................................................................................ 227

9-8. Interval Timer Operation Timings .................................................................................................. 228

9-9. External Event Counter Operation Timings (with Rising Edge Specified) ..................................... 231

9-10. Square-Wave Output Operation Timing ........................................................................................ 233

9-11. Interval T imer Operation Timing .................................................................................................... 234

9-12. External Event Counter Operation Timings (with Rising Edge Specified) ..................................... 236

9-13. Square-Wave Output Operation Timing ........................................................................................ 238

9-14. 8-Bit Timer Registers 1 and 2 Start Timing.................................................................................... 238

9-15. Event Counter Operation Timing ................................................................................................... 239

9-16. Timing after Compare Register Change during Timer Count Operation ....................................... 239

10-1. Watch Timer Block Diagram .......................................................................................................... 243

10-2. Timer Clock Select Register 2 Format........................................................................................... 244

10-3. Watch Timer Mode Control Register Format ................................................................................. 245

11-1. Watchdog Timer Block Diagram.................................................................................................... 249

11-2. Timer Clock Select Register 2 Format........................................................................................... 251

11-3. Watchdog Timer Mode Register Format........................................................................................ 252

27

LIST OF FIGURES (4/8)

Figure No. Title Page

12-1. Remote Controlled Output Application Example ........................................................................... 255

12-2. Clock Output Control Circuit Block Diagram ................................................................................. 256

12-3. Timer Clock Select Register 0 Format........................................................................................... 258

12-4. Port Mode Register 3 Format ........................................................................................................ 259

13-1. Buzzer Output Control Circuit Block Diagram ............................................................................... 261

13-2. Timer Clock Select Register 2 Format........................................................................................... 263

13-3. Port Mode Register 3 Format ........................................................................................................ 264

14-1. A/D Converter Block Diagram ....................................................................................................... 266

14-2. Handling of AV

14-3. A/D Converter Mode Register Format........................................................................................... 270

14-4. A/D Converter Input Select Register Format................................................................................. 271

14-5. External Interrupt Mode Register 1 Format................................................................................... 272

14-6. A/D Converter Basic Operation..................................................................................................... 274

14-7. Relations between Analog Input Voltage and A/D Conversion Result........................................... 275

14-8. A/D Conversion by Hardware Start ............................................................................................... 276

14-9. A/D Conversion by Software Start................................................................................................. 277

14-10. Example of Method of Reducing Current Dissipation in Standby Mode........................................ 278

14-11. Analog Input Pin Disposition ......................................................................................................... 279

14-12. A/D Conversion End Interrupt Request Generation Timing........................................................... 280

14-13. Handling of AV

DD Pin ..................................................................................................................... 268

DD Pin ..................................................................................................................... 280

15-1. D/A Converter Block Diagram ....................................................................................................... 282

15-2. D/A Converter Mode Register Format ........................................................................................... 284

15-3. Use Example of Buffer Amplifier.................................................................................................... 286

16-1. Serial Bus Interface (SBI) System Configuration Example ........................................................... 289

16-2. Serial Interface Channel 0 Block Diagram .................................................................................... 291

16-3. Timer Clock Select Register 3 Format........................................................................................... 295

16-4. Serial Operating Mode Register 0 Format..................................................................................... 296

16-5. Serial Bus Interface Control Register Format................................................................................ 298

16-6. Interrupt Timing Specify Register Format ...................................................................................... 300

16-7. 3-Wire Serial I/O Mode Timings .................................................................................................... 305

16-8. RELT and CMDT Operations......................................................................................................... 305

16-9. Circuit of Switching in Transfer Bit Order ...................................................................................... 306

16-10. Example of Serial Bus Configuration with SBI .............................................................................. 307

16-11. SBI Transfer Timings ..................................................................................................................... 309

16-12. Bus Release Signal ....................................................................................................................... 310

16-13. Command Signal ........................................................................................................................... 310

16-14. Addresses ..................................................................................................................................... 311

16-15. Slave Selection with Address ........................................................................................................ 311

16-16. Commands .................................................................................................................................... 312

28

LIST OF FIGURES (5/8)

Figure No. Title Page

16-17. Data ............................................................................................................................................... 312

16-18. Acknowledge Signal ...................................................................................................................... 313

16-19. BUSY and READY Signals............................................................................................................ 314

16-20. RELT, CMDT, RELD, and CMDD Operations (Master) ................................................................. 319

16-21. RELT and CMDD Operations (Slave)............................................................................................ 319

16-22. ACKT Operation ............................................................................................................................ 320

16-23. ACKE Operations .......................................................................................................................... 321

16-24. ACKD Operations .......................................................................................................................... 322

16-25. BSYE Operation ............................................................................................................................ 322

16-26. Pin Configuration ........................................................................................................................... 325

16-27. Address Transmission from Master Device to Slave Device (WUP = 1) ....................................... 327

16-28. Command Transmission from Master Device to Slave Device ..................................................... 328

16-29. Data Transmission from Master Device to Slave Device .............................................................. 329

16-30. Data Transmission from Slave Device to Master Device .............................................................. 330

16-31. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ................................................. 333

16-32. 2-Wire Serial I/O Mode Timings .................................................................................................... 337

16-33. RELT and CMDT Operations......................................................................................................... 338

16-34. SCK0/P27 Pin Configuration ......................................................................................................... 339

2

17-1. Serial Bus Configuration Example Using I

C Bus ......................................................................... 343

17-2. Serial Interface Channel 0 Block Diagram .................................................................................... 345

17-3. Timer Clock Select Register 3 Format........................................................................................... 349

17-4. Serial Operating Mode Register 0 Format..................................................................................... 351

17-5. Serial Bus Interface Control Register Format................................................................................ 352

17-6. Interrupt Timing Specify Register Format ...................................................................................... 354

17-7. 3-Wire Serial I/O Mode Timings .................................................................................................... 359

17-8. RELT and CMDT Operations......................................................................................................... 359

17-9. Circuit of Switching in Transfer Bit Order ...................................................................................... 360

17-10. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ................................................. 361

17-11. 2-Wire Serial I/O Mode Timings .................................................................................................... 365

17-12. RELT and CMDT Operations......................................................................................................... 366

2

17-13. Example of Serial Bus Configuration Using I

C Bus ..................................................................... 367

17-14. I2C Bus Serial Data Transfer Timing.............................................................................................. 368

17-15. Start Condition............................................................................................................................... 369

17-16. Address ......................................................................................................................................... 369

17-17. Transfer Direction Specification..................................................................................................... 369

17-18. Acknowledge Signal ...................................................................................................................... 370

17-19. Stop Condition ............................................................................................................................... 370

17-20. Wait Signal .................................................................................................................................... 371

17-21. Pin Configuration ........................................................................................................................... 377

17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) .......... 379

17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) .......... 382

17-24. Start Condition Output ................................................................................................................... 385

17-25. Slave Wait Release (Transmission) .............................................................................................. 386

29

LIST OF FIGURES (6/8)

Figure No. Title Page

17-26. Slave Wait Release (Reception).................................................................................................... 387

17-27. SCK0/SCL/P27 Pin Configuration ................................................................................................. 390

17-28. SCK0/SCL/P27 Pin Configuration ................................................................................................. 390

17-29. Logic Circuit of SCL Signal ............................................................................................................ 391

18-1. Serial Interface Channel 1 Block Diagram .................................................................................... 395

18-2. Timer Clock Select Register 3 Format........................................................................................... 398

18-3. Serial Operation Mode Register 1 Format..................................................................................... 399

18-4. Automatic Data Transmit/Receive Control Register Format.......................................................... 400

18-5. Automatic Data Transmit/Receive Interval Specify Register Format............................................. 401

18-6. 3-Wire Serial I/O Mode Timings .................................................................................................... 407

18-7. Circuit of Switching in Transfer Bit Order ...................................................................................... 408

18-8. Basic Transmission/Reception Mode Operation Timings .............................................................. 417

18-9. Basic Transmission/Reception Mode Flowchart............................................................................ 418

18-10. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode)...... 419

18-11. Basic Transmission Mode Operation Timings ............................................................................... 421

18-12. Basic Transmission Mode Flowchart............................................................................................. 422

18-13. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode)..................................... 423

18-14. Repeat Transmission Mode Operation Timing .............................................................................. 425

18-15. Repeat Transmission Mode Flowchart .......................................................................................... 426

18-16. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode).................................. 427

18-17. Automatic Transmission/Reception Suspension and Restart........................................................ 429

18-18. System Configuration When the Busy Control Option is Used ..................................................... 430

18-19. Operation Timings when Using Busy Control Option (BUSY0 = 0) ............................................... 431

18-20. Busy Signal and Wait Cancel (when BUSY0 = 0) ......................................................................... 432

18-21. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) ................................ 433

18-22. Operation Timing of the Bit Slippage Detection Function Through the Busy SIgnal

(when BUSY0 = 1)......................................................................................................................... 434

18-23. Automatic Data Transmit/Receive Interval .................................................................................... 435

18-24. Operation Timing with Automatic Data Transmit/Receive Function Performed by

Internal Clock ................................................................................................................................ 436

19-1. Serial Interface Channel 2 Block Diagram .................................................................................... 441

19-2. Baud Rate Generator Block Diagram............................................................................................ 442

19-3. Serial Operating Mode Register 2 Format..................................................................................... 444

19-4. Asynchronous Serial Interface Mode Register Format.................................................................. 445

19-5. Asynchronous Serial Interface Status Register Format ................................................................ 447

19-6. Baud Rate Generator Control Register Format............................................................................. 448

19-7. Asynchronous Serial Interface Transmit/Receive Data Format..................................................... 461

19-8. Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing.. 463

19-9. Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing ....... 464

19-10. Receive Error Timing..................................................................................................................... 465

19-11. The State of Receive Buffer Register (RXB) and Whether the Receive Completion

Interrupt Request (INTSR) is Generated....................................................................................... 466

30

LIST OF FIGURES (7/8)

Figure No. Title Page

19-12. 3-Wire Serial I/O Mode Timing ...................................................................................................... 472

19-13. Circuit of Switching in Transfer Bit Order ...................................................................................... 473

19-14. Reception Completion Interrupt Request Generation Timing (when ISRM = 1)............................ 474

19-15. Receive Buffer Register Read Disable Period .............................................................................. 475

20-1. Real-time Output Port Block Diagram ........................................................................................... 478

20-2. Real-time Output Buffer Register Configuration............................................................................ 479

20-3. Port Mode Register 12 Format...................................................................................................... 480

20-4. Real-time Output Port Mode Register Format............................................................................... 480

20-5. Real-time Output Port Control Register Format ............................................................................ 481

21-1. Basic Configuration of Interrupt Function...................................................................................... 486

21-2. Interrupt Request Flag Register Format........................................................................................ 489

21-3. Interrupt Mask Flag Register Format............................................................................................. 490

21-4. Priority Specify Flag Register Format............................................................................................ 491

21-5. External Interrupt Mode Register 0 Format................................................................................... 492

21-6. External Interrupt Mode Register 1 Format................................................................................... 493

21-7. Sampling Clock Select Register Format........................................................................................ 494

21-8. Noise Eliminator Input/Output Timing (during rising edge detection) ............................................ 495

21-9. Program Status Word Configuration ............................................................................................. 496

21-10. Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment................... 498

21-11. Non-Maskable Interrupt Request Acknowledge Timing................................................................. 498

21-12. Non-Maskable Interrupt Request Acknowledge Operation ........................................................... 499

21-13. Interrupt Request Acknowledge Processing Algorithm.................................................................. 501

21-14. Interrupt Request Acknowledge Timing (Minimum Time) .............................................................. 502

21-15. Interrupt Request Acknowledge Timing (Maximum Time) ............................................................. 502

21-16. Multiple Interrupt Example ............................................................................................................. 504

21-17. Interrupt Request Hold .................................................................................................................. 506

21-18. Basic Configuration of Test Function............................................................................................. 507

21-19. Format of Interrupt Request Flag Register 1L ............................................................................... 508

21-20. Format of Interrupt Mask Flag Register 1L.................................................................................... 508

21-21. Key Return Mode Register Format................................................................................................ 509

22-1. Memory Map when Using External Device Expansion Function................................................... 512

22-2. Memory Expansion Mode Register Format................................................................................... 516

22-3. Memory Size Switching Register Format ...................................................................................... 517

22-4. Instruction Fetch from External Memory ....................................................................................... 519

22-5. External Memory Read Timing ...................................................................................................... 520

22-6. External Memory Write Timing ...................................................................................................... 521

22-7. External Memory Read Modify Write Timing ................................................................................. 522

µ

22-8. Connection Example of

23-1. Oscillation Stabilization Time Select Register Format ................................................................... 526

23-2. HALT Mode Clear upon Interrupt Request Generation ................................................................. 528

PD78054 and Memory .......................................................................... 523

31

LIST OF FIGURES (8/8)

Figure No. Title Page

23-3. HALT Mode Release by RESET Input........................................................................................... 529

23-4. STOP Mode Release by Interrupt Request Generation ................................................................ 531

23-5. Release by STOP Mode RESET Input.......................................................................................... 532

24-1. Block Diagram of Reset Function.................................................................................................. 533

24-2. Timing of Reset Input by RESET Input.......................................................................................... 534

24-3. Timing of Reset due to Watchdog Timer Overflow ........................................................................ 534

24-4. Timing of Reset Input in STOP Mode by RESET Input ................................................................. 534

25-1. Block Diagram of ROM Correction................................................................................................ 537

25-2. Correction Address Registers 0 and 1 Format .............................................................................. 538

25-3. Correction Control Register Format .............................................................................................. 539

25-4. Storing Example to EEPROM (when one place is corrected) ....................................................... 540

25-5. Connecting Example with EEPROM (using 2-wire serial I/O mode)............................................. 540

25-6. Initialization Routine ...................................................................................................................... 541

25-7. ROM Correction Operation............................................................................................................ 542

25-8. ROM Correction Example ............................................................................................................. 543

25-9. Program Transition Diagram (when one place is corrected) ......................................................... 544

25-10. Program Transition Diagram (when two places are corrected) ..................................................... 545

µ

26-1. Memory Size Switching Register Format (
26-2. Memory Size Switching Register Format (

26-3. Internal Expansion RAM Size Switching Register Format ............................................................ 551

26-4. Page Program Mode Flowchart..................................................................................................... 554

26-5. Page Program Mode Timing.......................................................................................................... 555

26-6. Byte Program Mode Flowchart...................................................................................................... 556

26-7. Byte Program Mode Timing ........................................................................................................... 557

26-8. PROM Read Timing ...................................................................................................................... 558

B-1. Development Tool Configuration ................................................................................................... 580

B-2. EV-9200GC-80 Drawing (For Reference Only)............................................................................. 590

B-3. EV-9200GC-80 Footprint (For Reference Only)............................................................................ 591

B-4. TGK-080SDW Drawing (For Reference) (unit: mm)...................................................................... 592

PD78P054) ............................................................... 549

µ

PD78P058) ............................................................... 550

32

LIST OF TABLES (1/3)

Table No. Title Page

1-1. Differences between Standard Quality Grade Products and (A) Products.................................... 48

1-2. Mask Options of Mask ROM Versions...........................................................................................48

2-1. Mask Options of Mask ROM Versions...........................................................................................58

3-1. Pin Input/Output Circuit Types....................................................................................................... 71

4-1. Pin Input/Output Circuit Types....................................................................................................... 87

5-1. Internal ROM Capacity .................................................................................................................. 99

5-2. Vector Table................................................................................................................................... 99

5-3. Internal High-Speed RAM Capacity .............................................................................................. 100

5-4. Internal High-Speed RAM Area ..................................................................................................... 110

5-5. Correspondent Table of Absolute Addresses in the General Registers......................................... 112

5-6. Special-Function Register List....................................................................................................... 115

µ

6-1. Port Functions (

6-2. Port Functions (µPD78054Y subseries) ........................................................................................ 132

6-3. Port Configuration ......................................................................................................................... 134

6-4. Pull-up Resistor of Port 6 .............................................................................................................. 144

6-5. Port Mode Register and Output Latch Settings when Using Dual-Functions ................................ 151

6-6. Comparison between Mask ROM Version and PROM Version..................................................... 157

PD78054 subseries) .......................................................................................... 130

7-1. Clock Generator Configuration ...................................................................................................... 159

7-2. Relationship between CPU Clock and Minimum Instruction Execution Time................................ 163

7-3. Maximum Time Required for CPU Clock Switchover .................................................................... 172

8-1. Timer/Event Counter Operations................................................................................................... 176

8-2. 16-Bit Timer/Event Counter Interval Times .................................................................................... 177

8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges........................................................... 178

8-4. 16-Bit Timer/Event Counter Configuration..................................................................................... 179

8-5. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge .............................................. 181

8-6. 16-Bit Timer/Event Counter Interval Times .................................................................................... 193

8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges .............................................................. 207

9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times ....................................................................... 216

9-2. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges .............................................. 217

9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as

16-Bit Timer/Event Counters ......................................................................................................... 218

9-4. Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as

16-Bit Timer/Event Counters ......................................................................................................... 219

9-5. 8-Bit Timer/Event Counters 1 and 2 Configurations ...................................................................... 220

9-6. 8-Bit Timer/Event Counter 1 Interval Time .................................................................................... 229

9-7. 8-Bit Timer/Event Counter 2 Interval Time .................................................................................... 230

33

LIST OF TABLES (2/3)

Table No. Title Page

9-8. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges .............................................. 232

9-9. Interval Times when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) are Used

as 16-Bit Timer/Event Counter ...................................................................................................... 235

9-10. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2)

are Used as 16-Bit Timer/Event Counter....................................................................................... 237

10-1. Interval T imer Interval Time........................................................................................................... 241

10-2. Watch Timer Configuration ............................................................................................................ 242

10-3. Interval T imer Interval Time........................................................................................................... 246

11-1. Watchdog Timer Runaway Detection Times.................................................................................. 247

1 1-2. Interval Times................................................................................................................................ 248

1 1-3. W atchdog Timer Configuration ...................................................................................................... 249

11-4. Watchdog Timer Runaway Detection Times.................................................................................. 253

1 1-5. Interval Timer Interval Time........................................................................................................... 254

12-1. Clock Output Control Circuit Configuration ................................................................................... 256

13-1. Buzzer Output Control Circuit Configuration ................................................................................. 261

14-1. A/D Converter Configuration ......................................................................................................... 265

15-1. D/A Converter Configuration ......................................................................................................... 282

16-1. Differences between Channels 0, 1, and 2 ................................................................................... 287

16-2. Serial Interface Channel 0 Configuration ...................................................................................... 290

16-3. Various Signals in SBI Mode ......................................................................................................... 323

17-1. Differences between Channels 0, 1, and 2 ................................................................................... 341

17-2. Serial Interface Channel 0 Configuration ...................................................................................... 344

17-3. Serial Interface Channel 0 Interrupt Request Signal Generation .................................................. 347

2

17-4. Signals in I

C Bus Mode................................................................................................................ 376

18-1. Serial Interface Channel 1 Configuration ...................................................................................... 394

18-2. Interval Timing Through CPU Processing (when the internal clock is operating).......................... 436

18-3. Interval Timing Through CPU Processing (when the external clock is operating)......................... 437

19-1. Serial Interface Channel 2 Configuration ...................................................................................... 440

19-2. Serial Interface Channel 2 Operating Mode Settings.................................................................... 446

19-3. Relation between Main System Clock and Baud Rate.................................................................. 450

19-4. Relation between ASCK Pin Input Frequency and Baud Rate

(When BRGC is set to 00H) .......................................................................................................... 451

19-5. Relation between Main System Clock and Baud Rate.................................................................. 459

19-6. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)......... 460

34

LIST OF TABLES (3/3)

Table No. Title Page

19-7. Receive Error Causes ................................................................................................................... 465

20-1. Real-time Output Port Configuration ............................................................................................. 478

20-2. Operation in Real-time Output Buffer Register Manipulation ........................................................ 479

20-3. Real-time Output Port Operating Mode and Output Trigger .......................................................... 481

21-1. Interrupt Source List...................................................................................................................... 484

21-2. Various Flags Corresponding to Interrupt Request Sources ......................................................... 488

21-3. Times from Maskable Interrupt Request Generation to Interrupt Service ..................................... 500

21-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing .................................. 503

21-5. Test Input Factors.......................................................................................................................... 507

21-6. Flags Corresponding to Test Input Signals.................................................................................... 507

22-1. Pin Functions in External Memory Expansion Mode..................................................................... 511

22-2. State of Ports 4 to 6 Pins in External Memory Expansion Mode................................................... 511

22-3. Values when the Memory Size Switching Register is Reset ......................................................... 517

23-1. HALT Mode Operating Status........................................................................................................ 527

23-2. Operation after HALT Mode Release ............................................................................................ 529

23-3. STOP Mode Operating Status....................................................................................................... 530

23-4. Operation after STOP Mode Release............................................................................................ 532

24-1. Hardware Status after Reset ......................................................................................................... 535

25-1. ROM Correction Configuration...................................................................................................... 537

µ

26-1. Differences between
26-2. Differences between

26-3. Examples of Memory Size Switching Register Settings (µPD78P054) ......................................... 549

26-4. Examples of Memory Size Switching Register Settings (µPD78P058) ......................................... 550

26-5. Value Set to the Internal Expansion RAM Size Switching Register .............................................. 551

26-6. PROM Programming Operating Modes ........................................................................................ 552

27-1. Operand Identifiers and Description Methods ............................................................................... 562

A-1. Major differences between

µ

PD78058F, 78058FY Subseries .................................................................................................. 578

PD78P054, 78P058 and Mask ROM Versions.......................................... 547

µ

PD78P054 and 78P058............................................................................. 548

µ

PD78054, 78054Y Subseries and

B-1. OS for IBM PC............................................................................................................................... 589

B-2. Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A.................................... 589

35

[MEMO]

36

CHAPTER 1 GENERAL (µPD78054 Subseries)

1.1 Features

On-chip high-capacity ROM and RAM

Type

Part Number

µ

PD78052

µ

PD78053

µ

PD78054

µ

PD78P054

µ

PD78055

µ

PD78056

µ

PD78058

µ

PD78P058

Program Memory

(ROM)

16 Kbytes
24 Kbytes
32 Kbytes
32 Kbytes
40 Kbytes
48 Kbytes
60 Kbytes
60 Kbytes

Note1

Note1

Internal High-Speed RAM Internal Buffer RAM Internal Expansion RAM

512 bytes
1024 bytes

1024 bytes
1024 bytes

1024 bytes

Note1

Note1

Data Memory

32 bytes None

1024 bytes
1024 bytes

Note2

Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the

memory size switching register (IMS).

2. The capacity of internal high-speed RAM can be changed by means of the internal expansion RAM
size switching register (IXS).

External Memory Expansion Space: 64 Kbytes
Minimum instruction execution time changeable from high speed (0.4 µs: In main system clock 5.0 MHz operation)
to ultra-low speed (122 µs: In subsystem clock 32.768 kHz operation)
Instruction set suited to system control

• Bit manipulation possible in all address spaces

• Multiply and divide instructions
69 I/O ports: (4 N-ch open-drain ports)
8-bit resolution A/D converter: 8 channels
8-bit resolution D/A converter: 2 channels
Serial interface: 3 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel

• 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel

• 3-wire serial I/O/UART mode: 1 channel
Timer: 5 channels

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer : 1 channel

• Watchdog timer : 1 channel
22 vectored interrupt sources
2 test inputs
Two types of on-chip clock oscillators (main system clock and subsystem clock)
Supply voltage: VDD = 2.0 to 6.0 V

37

CHAPTER 1 OUTLINE (µPD78054 Subseries)

1.2 Applications

µ

PD78052, 78053, 78054, 78P054, 78055, 78056, 78058, 78P058:

Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending

machines, etc.

µ

PD78052(A), 78053(A), 78054(A):

Control unit for automobile electronics, gas detector/breaker, various safety unit, etc.

1.3 Ordering Information

Part number Package Internal ROM

µ

PD78052GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78052GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Mask ROM

µ

PD78053GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78053GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Mask ROM

µ

PD78054GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78054GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Mask ROM

µ

PD78P054GC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) One-time PROM

µ

PD78P054GC-8BT

µ

PD78P054GK-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) One-time PROM

µ

PD78P054KK-T 80-pin ceramic WQFN (14 × 14 mm) EPROM

µ

PD78055GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78055GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Mask ROM

µ

PD78056GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78056GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Mask ROM

µ

PD78058GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78058GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Mask ROM

µ

PD78P058GC-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) One-time PROM

µ

PD78P058KK-T 80-pin ceramic WQFN (14 × 14 mm) EPROM

µ

PD78052GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Mask ROM

µ

PD78053GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Mask ROM

µ

PD78054GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Mask ROM

Note

80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) One-time PROM

Note Under development

µ

Caution The

PD78P054GC is available in two packages. For the package that can be supplied, consult

NEC.

Remark ××× indicates ROM code suffix.

38

CHAPTER 1 OUTLINE (µPD78054 Subseries)

1.4 Quality Grade

Part number Package Quality grade

µ

PD78052GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78052GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard

µ

PD78053GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78053GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard

µ

PD78054GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78054GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard

µ

PD78P054GC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard

µ

PD78P054GC-8BT

µ

PD78P054GK-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard

µ

PD78P054KK-T 80-pin ceramic WQFN (14 × 14 mm) Not applicable

µ

PD78055GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

Note

80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

(for function evalution)

µ

PD78055GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard

µ

PD78056GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78056GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard

µ

PD78058GC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78058GK-×××-BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard

µ

PD78P058GC-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78P058KK-T 80-pin ceramic WQFN (14 × 14 mm) Not applicable

(for function evalution)

µ

PD78052GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Special

µ

PD78053GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Special

µ

PD78054GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Special

Note Under development

Cautions 1. The µPD78P054GC is available in two packages. For the package that can be supplied,

consult NEC.

µ

2. The

PD78054KK-T and 78P058KK-T should be used only for experiment or function
evaluation, because they are not intended for use in equipment that will be mass-produced
and require high reliability.

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC

Corporation to know the specification of quality grade on the devices and its recommended applications.

39

CHAPTER 1 OUTLINE (µPD78054 Subseries)

1.5 Pin Configuration (Top View)

(1) Normal operating mode

• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)

µ

PD78P054GC-3B9

• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

µ

PD78052GC-×××-8BT, 78053GC-×××-8BT, 78054GC-×××-8BT, 78P054GC-8BT

µ

PD78055GC-×××-8BT, 78056GC-×××-8BT, 78058GC-×××-8BT, 78P058GC-8BT

• 80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

µ

PD78052GK-×××-BE9, 78053GK-×××-BE9, 78054GK-×××-BE9, 78P054GK-BE9

µ

PD78055GK-×××-BE9, 78056GK-×××-BE9, 78058GK-×××-BE9

• 80-pin ceramic WQFN (14 × 14 mm)

µ

PD78P054KK-T, 78P058KK-T

P14/ANI4

P13/ANI3

P12/ANI2

REF0AVDD

P11/ANI1

P10/ANI0

AV

)

PP

XT1/P07

XT2

IC (V

X1X2V

DD

P06/INTP6

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2

P01/INTP1/TI01

Note

P00/INTP0/TI00

P15/ANI5
P16/ANI6
P17/ANI7

AV

AV

REF1

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P27/SCK0

P40/AD0
P41/AD1

SS

P130/ANO0
P131/ANO1

P70/SI2/RxD

P71/SO2/TxD

P72/SCK2/ASCK

P25/SI0/SB0

P26/SO0/SB1

Note Under development

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

SS

V

P60

P61

P62

P50/A8

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

P63

P64/RD

RESET
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37
P36/BUZ
P35/PCL
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
P67/ASTB
P66/WAIT
P65/WR

Cautions 1. Be sure to connect IC (Internally Connected) pin to V

2. Connect AVDD pin to VDD.

3. Connect AV

SS pin to VSS.

Remark Pin connection in parentheses is intended for the µPD78P054, 78P058.

40

SS directly.

CHAPTER 1 OUTLINE (µPD78054 Subseries)

Pin Identifications

A8 to A15 : Address Bus P130, P131 : Port13
AD0 to AD7 : Address/Data Bus PCL : Programmable Clock
ANI0 to ANI7 : Analog Input RD : Read Strobe
ANO0, ANO1 : Analog Output RESET : Reset
ASCK : Asynchronous Serial Clock RTP0 to RTP7 : Real-Time Output Port
ASTB : Address Strobe RxD : Receive Data

DD : Analog Power Supply SB0, SB1 : Serial Bus

AV
AVREF0, AVREF1 : Analog Reference Voltage SCK0 to SCK2 : Serial Clock
AVSS : Analog Ground S10 to S12 : Serial Input
BUSY : Busy SO0 to SO2 : Serial Output
BUZ : Buzzer Clock STB : Strobe
IC : Internally Connected TI00, TI01 : Timer Input
INTP0 to INTP6 : Interrupt from Peripherals TI1, TI2 : Timer Input
P00 to P07 : Port0 TO0 to TO2 : Timer Output
P10 to P17 : Port1 TxD : Transmit Data
P20 to P27 : Port2 V
P30 to P37 : Port3 VPP : Programming Power Supply
P40 to P47 : Port4 VSS : Ground
P50 to P57 : Port5 WAIT : Wait
P60 to P67 : Port6 WR : Write Strobe
P70 to P72 : Port7 X1, X2 : Crystal (Main System Clock)
P120 to P127 : Port12 XT1, XT2 : Crystal (Subsystem Clock)

DD : Power Supply

41

CHAPTER 1 OUTLINE (µPD78054 Subseries)

(2) PROM programming mode

• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)

µ

PD78P054GC-3B9

• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

µ

PD78P054GC-8BT

Note

, 78P058GC-8BT

• 80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

µ

PD78P054GK-BE9

• 80-pin ceramic WQFN (14 × 14 mm)

µ

PD78P054KK-T, 78P058KK-T

(L)

(L)

(L)

(L)

VSS VDD (L)

Open

VPP (L)

Open

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1
2

V

SS

V

DD

A0
A1

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A2A3A4A5A6A7A8

A16

A10

A11

A12

A13

DD

V

SS

V

A14

(L)

A15

PGM

(L)

(L)

A9

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

OE

RESET

(L)

D7
D6
D5
D4
D3
D2
D1
D0

(L)

CE

Note Under development

Cautions 1. (L) : Connect individually to VSS via a pull-down resistor.

2. VSS : Connect to the ground.

3. RESET : Set to the low level.

4. Open : Leave this pin unconnected.

A0 to A16 : Address Bus RESET : Reset
CE : Chip Enable V

DD : Power Supply

D0 to D7 : Data Bus VPP : Programming Power Supply
OE : Output Enable VSS : Ground
PGM : Program

42

CHAPTER 1 OUTLINE (µPD78054 Subseries)

1.6 78K/0 Series Expansion

The products in the 78K/0 Series are listed below. The names in boxes are subseries names.

Mass-produced products
Products under development

The subseries whose name ends with Y support

2

C bus specifications.

the I

Control

100-pin
100-pin Added timers to µPD78054 and enhanced external interface
100-pin
100-pin
80-pin Enhanced serial I/O of µPD78054, reduced EMI noise version
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
42-/44-pin

µPD78075B

µPD78078 µPD78078Y

µPD78070A µPD78070AY

µ

PD780018AY

µPD780058

µPD78058F

µPD78054
µPD780034
µPD780024

µPD780058Y

µPD78058FY

µPD78054Y
µPD780034Y
µPD780024Y

µPD78014H
µPD78018F

µPD78014

µPD78018FY

µPD78014Y

µPD780001

µPD78002

µPD78002Y

µPD78083

Reduced EMI noise version of µPD78078

ROM-less version of µPD78078
Enhanced serial I/O of µPD78078Y and functions are defined.

Note

Reduced EMI noise version of µPD78054
Added UART and D/A to µPD78014 and enhanced I/Os
Enhanced A/D of µPD780024
Enhanced serial I/O of µPD78018F
Reduced EMI noise version of µPD78018F
Low-voltage (1.8 V) version of µPD78014 and enhanced ROM/RAM size options
Added A/D and 16-bit timer to µPD78002
Added A/D to µPD78002
Basic subseries for control applications
Equipped with UART and operates at low-voltage (1.8 V)

78K/0

Series

64-pin
64-pin

100-pin
100-pin
80-pin

100-pin
100-pin
100-pin

80-pin

Inverter control

µPD78098864-pin
µPD780964
µPD780924

TM

driving

FIP

µPD780208
µPD780228
µPD78044H

Enhanced inverter control, timer, and SIO of µPD780964, expanded ROM and RAM
Enhanced A/D of µPD780924
Equipped with inverter control circuit and UART, reduced EMI noise version

Enhanced I/O and FIP C/D of µPD78044F, 53 display outputs
Enhanced I/O and FIP C/D of µPD78044H, 48 display outputs
Added N-ch open-drain I/O to µPD78044F, 34 display outputs

µPD78044F80-pin Basic subseries for driving FIPs, 34 display outputs

LCD driving

µPD780308
µPD78064B

µPD78064

TM

IEBus

µPD78098B

µPD780308Y

µPD78064Y

supported

Enhanced SIO of µPD78064, expanded ROM and RAM
Reduced EMI noise version of µPD78064
Basic subseries for driving LCDs, equipped with UART

Reduced EMI noise version of µPD78098

µPD7809880-pin Added IEBus controller to µPD78054

Meter control

µPD78097380-pin

Equipped with controller/driver for driving automobile meters

Note Planned

43

CHAPTER 1 OUTLINE (µPD78054 Subseries)

The following shows the major differences between subseries products.

Function ROM Timer 8-bit 10-bit 8-bit
Subseries Name
ControlµPD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch – 2 ch 3 ch (UART: 1 ch) 88 1.8 V √

µ

PD78078 48 K to 60 K

µ

PD78070A – 61 2.7 V

µ

PD780058 24 K to 60 K 2 ch

µ

PD78058F 48 K to 60 K 3 ch (UART: 1 ch) 69 2.7 V

µ

PD78054 16 K to 60 K 2.0 V

µ

PD780034 8 K to 32 K – 8 ch –

µ

PD780024 8 ch –

µ

PD78014H 2 ch 53

µ

PD78018F 8 K to 60 K

µ

PD78014 8 K to 32 K 2.7 V

µ

PD780001 8 K – – 1 ch 39 –

µ

PD78002 8 K to 16 K 1 ch – 53 √

µ

PD78083 – 8 ch

InverterµPD780988 32 K to 60 K 3 ch
control

FIP
driving

LCD
driving UART: 1 ch)

IEBusµPD78098B 40 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch – 2 ch 3 ch (UART: 1 ch) 69 2.7 V √
supported

MeterµPD780973 24 K to 32 K 3 ch 1 ch 1 ch 1 ch 5 ch – – 2 ch (UART: 1 ch) 56 4.5 V –
control

µ

PD780964 8 K to 32 K

µ

PD780924 8 ch

µ

PD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch – – 2 ch 74 2.7 V –

µ

PD780228 48 K to 60 K 3 ch – – 1 ch 72 4.5 V

µ

PD78044H 32 K to 48 K 2 ch 1 ch 1 ch 68 2.7 V

µ

PD78044F 16 K to 40 K 2 ch

µ

PD780308 48 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch – –

µ

PD78064B 32 K 2 ch (UART: 1 ch)

µ

PD78064 16 K to 32 K

µ

PD78098 32 K to 60 K

Capacity 8-bit 16-bit

Note 1
Note 2

Watch

WDT A/D A/D D/A

– 1 ch – 8 ch

–

Serial Interface I/O

3 ch (Time division
UART: 1 ch)

3 ch (UART: 1 ch, Time
division 3-wire: 1 ch)

1 ch (UART: 1 ch)

–

3 ch (UART: 2 ch) 47 4.0 V √
2 ch (UART: 2 ch) 2.7 V

3 ch (Time division

VDD

Externa

MIN. Value Expansion

68 1.8 V

51 1.8 V

33 1.8 V –

57 2.0 V –

l

Notes 1. 16-bit timer: 2 channels

10-bit timer: 1 channel

2. 10-bit timer: 1 channel

44

1.7 Block Diagram

CHAPTER 1 OUTLINE (µPD78054 Subseries)

TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

16-bit TIMER/
EVENT COUNTER

8-bit TIMER/
EVENT COUNTER 1

8-bit TIMER/
EVENT COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL
INTERFACE 0

SERIAL
INTERFACE 1

78K/0
CPU CORE

ROM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

P00
P01-P06
P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P72

SI2/RxD/P70

SO2/TxD/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

SERIAL
INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT
CONTROL

BUZZER OUTPUT

CLOCK OUTPUT
CONTROL

RAM

V

DD

PORT 12

PORT 13

REAL-TIME
OUTPUT PORT

P120-P127

P130, P131

RTP0/P120­RTP7/P127

AD0/P40­AD7/P47

A8/P50-

EXTERNAL
ACCESS

A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67

RESET

SYSTEM
CONTROL

V

SS

IC

(V

PP

)

X1
X2
XT1/P07
XT2

Remarks 1. The internal ROM and RAM capacities depend on the product.

2. Pin connection in parentheses is intended for the µPD78P054, 78P058.

45

1.8 Outline of Function

CHAPTER 1 OUTLINE (µPD78054 Subseries)

Part Number

Item

Internal
memory

Memory space 64 Kbytes
General register 8 bits × 8 × 4 banks

Minimum
instruction
execution t ime

Instruction set • 16-bit operation

I/O port • Total : 69

A/D converter 8-bit resolution × 8 channels

ROM

High-speed RAM

Buffer RAM 32 bytes
Expansion RAM None

With main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0 MHz)
With subsystem clock selected 122 µs (@ 32.768 kHz)

µ

PD78052µPD78053µPD78054µPD78P054µPD78055µPD78056µPD78058µPD78P058

Mask ROM
16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes

512 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation)

• BCD adjust, etc.

• CMOS input : 2

• CMOS I/O : 63

• N-ch open-drain I/O : 4

Note 1 Note 2

PROM

Note 3 Note 3

Note 3 Note 3

Mask ROM

1024 bytes

PROM

1024 bytes

Note 4

D/A converter 8-bit resolution × 2 channels
Serial interface • 3-wire serial I/O/SBI/2-wire serial I/O mode selection possible : 1 channel

• 3-wire serial I/O mode (Max. 32-byte on-chip auto-transmit/receive) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

Timer • 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer : 1 channel

• Watchdog timer : 1 channel
Timer output Three outputs: (14-bit PWM output enable: 1)
Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,

2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock)

32.768 kHz (@ 32.768 kHz with subsystem clock)
Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock)

Notes 1. The µPD78P054 is the PROM version for the µPD78052, 78053, and 78054.

2. The µPD78P058 is the PROM version for the µPD78055, 78056, and 78058.

3. The capacities of the internal PROM and the internal high-speed RAM can be changed using the

memory switching register (IMS).

4. The capacity of the internal expansion RAM can be changed using the internal expansion RAM size
switching register (IXS).

46

CHAPTER 1 OUTLINE (µPD78054 Subseries)

Part NumberµPD78052µPD78053µPD78054µPD78P054µPD78055µPD78056µPD78058µPD78P058

Item

Vectored Maskable Internal: 13 External: 7
interrupt Non-maskable Internal: 1
source Software 1

Test input Internal: 1 External: 1
Supply voltage VDD = 2.0 to 6.0 V
Operating ambient temperature TA = –40 to +85°C
Package • 80-pin plastic QFP

• 80-pin plastic QFP

• 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) (except µPD78P058)

• 80-pin ceramic WQFN (14 × 14 mm) (µPD78P054, 78P058 only)

(14 × 14 mm, Resin thickness : 2.7 mm) (µPD78P054 only)

Note 3

Note 1 Note2

(14 × 14 mm, Resin thickness : 1.4 mm)

Notes 1. The µPD78P054 is the PROM version for the µPD78052, 78053, 78054.

2. The µPD78P058 is the PROM version for the µPD78055, 78056, 78058.

3. The µPD78P054 is under development.

47

CHAPTER 1 OUTLINE (µPD78054 Subseries)

1.9 Differences between Standard Quality Grade Products and (A) Products

Table 1-1 shows the differences between the standard quality grade products (µPD78052, 78053, 78054) and (A)

products (µPD78052(A), 78053(A), 78054(A)).

Table 1-1. Differences between Standard Quality Grade Products and (A) Products

Part Number

Item
Quality grade Standard Special

Package • 80-pin plastic QFP

Recommended
soldering conditions

Standard Quality Grade Products (A) Products

Note 3

(14 × 14 mm, Resin thickness : 1.4 mm) (14 × 14 mm, Resin thickness : 2.7 mm)

• 80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

Refer to separate Data Sheets

80-pin plastic QFP

1.10 Mask Options

The mask ROM versions (µPD78052, 78053, 78054, 78055, 78056, 78058) provide pull-up resistor mask options
which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order
for the device production. Using this mask option when pull-up resistors are required reduces the number of
components to add to the device, resulting in board space saving.

µ

The mask options provided in the

Table 1-2. Mask Options of Mask ROM Versions

Pin names Mask options

P60 to P63 Pull-up resistor connection can be specified in 1-bit units.

PD78054 subseries are shown in Table 1-2.

48

CHAPTER 2 GENERAL (µPD78054Y Subseries)

2.1 Features

On-chip high-capacity ROM and RAM

Data Memory

32 bytes None

1024 bytes
1024 bytes

Note 2

Part Number

µ

PD78052Y

µ

PD78053Y

µ

PD78054Y

µ

PD78055Y

µ

PD78056Y

µ

PD78058Y

µ

PD78P058Y

Type

Program Memory

(ROM)

16 Kbytes
24 Kbytes
32 Kbytes
40 Kbytes
48 Kbytes
60 Kbytes
60 Kbytes

Note 1

Internal High-Speed RAM Internal Buffer RAM Internal Expansion RAM

512 bytes
1024 bytes

1024 bytes

Note 1

Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the

memory size switching register (IMS).

2. The capacity of internal high-speed RAM can be changed by means of the internal expansion RAM
size switching register (IXS).

External Memory Expansion Space: 64 Kbytes
Minimum instruction execution time changeable from high speed (0.4 µs: In main system clock 5.0 MHz operation)
to ultra-low speed (122 µs: In subsystem clock 32.768 kHz operation)
Instruction set suited to system control

• Bit manipulation possible in all address spaces

• Multiply and divide instructions
I/O ports: 69 (N-ch open-drain ports: 4)
8-bit resolution A/D converter: 8 channels
8-bit resolution D/A converter: 2 channels
Serial interface: 3 channels

2

• 3-wire serial I/O/2-wire serial I/O/I

C bus mode: 1 channel

• 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel

• 3-wire serial I/O/UART mode: 1 channel
Timer: Five channels

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer : 1 channel

• Watchdog timer : 1 channel
22 vectored interrupt sources
2 test inputs
Two types of on-chip clock oscillators (main system clock and subsystem clock)
Supply voltage: VDD = 2.0 to 6.0 V

49

CHAPTER 2 OUTLINE (µPD78054Y Subseries)

2.2 Applications

Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending

machines, etc.

2.3 Ordering Information

Part number Package Internal ROM

µ

PD78052YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78053YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78054YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78055YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78056YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78058YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Mask ROM

µ

PD78P058YGC-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) One-time PROM

µ

PD78P058YKK-T 80-pin ceramic WQFN (14 × 14 mm) EPROM

Remark ××× indicates ROM code suffix.

2.4 Quality Grade

Part number Package Quality grade

µ

PD78052YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78053YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78054YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78055YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78056YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78058YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78P058YGC-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard

µ

PD78P058YKK-T 80-pin ceramic WQFN (14 × 14 mm) Not applicable

(for function evaluation)

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC

Corporation to know the specification of quality grade on the devices and its recommended applications.

50

CHAPTER 2 OUTLINE (µPD78054Y Subseries)

2.5 Pin Configuration (Top View)

(1) Normal operating mode

• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

µ

PD78052YGC-×××-8BT, 78053YGC-×××-8BT, 78054YGC-×××-8BT

µ

PD78055YGC-×××-8BT, 78056YGC-×××-8BT, 78058YGC-×××-8BT, 78P058YGC-8BT

• 80-pin ceramic WQFN (14 × 14 mm)

µ

PD78P058YKK-T

P14/ANI4

P13/ANI3

P12/ANI2

REF0AVDD

P11/ANI1

P10/ANI0

AV

)

PP

XT1/P07

XT2

IC (V

X1X2V

DD

P06/INTP6

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2

P01/INTP1/TI01

P00/INTP0/TI00

P15/ANI5
P16/ANI6
P17/ANI7

AV
P130/ANO0
P131/ANO1

AV

P70/SI2/RxD

P71/SO2/TxD

P72/SCK2/ASCK

P25/SI0/SB0/SDA0

P26/SO0/SB1/SDA1

P27/SCK0/SCL

REF1

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P40/AD0
P41/AD1

SS

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

SS

V

P60

P61

P50/A8

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

P62

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

P63

P64/RD

Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly.

2. Connect AVDD pin to VDD.

3. Connect AVSS pin to VSS.

RESET
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37
P36/BUZ
P35/PCL
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
P67/ASTB
P66/WAIT
P65/WR

Remark Pin connection in parentheses is intended for the

µ

PD78P058Y.

51

CHAPTER 2 OUTLINE (µPD78054Y Subseries)

Pin Identifications

A8 to A15 : Address Bus PCL : Programmable Clock
AD0 to AD7 : Address/Data Bus RESET : Reset
ANI0 to ANI7 : Analog Input RD : Read Strobe
ANO0 to ANO7 : Analog Output RTP0 to RTP7 : Real-Time Output Port
ASCK : Asynchronous Serial Clock RxD : Receive Data
ASTB : Address Strobe SB0, SB1 : Serial Bus

DD : Analog Power Supply SCK0 to SCK1 : Serial Clock

AV
AVREF0, AVREF1 : Analog Reference Voltage SCL : Serial Clock
AVSS : Analog Ground SDA0, SDA1 : Serial Data
BUSY : Busy SI0, SI1 : Serial Input
BUZ : Buzzer Clock SO0, SO1 : Serial Output
IC : Internally Connected STB : Strobe
INTP0 to INTP6 : Interrupt from Peripherals TI1, TI2 : Timer Input
P00 to P07 : Port0 TI00 to TI01 : Timer Input
P10 to P17 : Port1 TO0 to TO2 : Timer Output
P20 to P27 : Port2 TxD : Transmit Data
P30 to P37 : Port3 V
P40 to P47 : Port4 VPP : Programming Power Supply
P50 to P57 : Port5 V
P60 to P67 : Port6 WAIT : Wait
P70 to P72 : Port7 WR : Write Strobe
P120 to P127 : Port12 X1, X2 : Crystal (Main System Clock)
P130, P131 : Port13 XT1, XT2 : Crystal (Subsystem Clock)

DD : Power Supply

SS : Ground

52

CHAPTER 2 OUTLINE (µPD78054Y Subseries)

(2) PROM programming mode

• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

µ

PD78P058YGC-8BT

• 80-pin ceramic WQFN (14 × 14 mm)

µ

PD78P058YKK-T

(L)

(L)

(L)

(L)

VSS VDD (L)

Open

VPP (L)

Open

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1
2

V

SS

V

DD

A0
A1

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A2A3A4A5A6A7A8

A16

A10

A11

A12

A13

DD

V

SS

V

A14

(L)

A15

PGM

(L)

(L)

A9

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

OE

RESET

(L)

D7
D6
D5
D4
D3
D2
D1
D0

(L)

CE

Cautions 1. (L) : Connect individually to V

SS via a pull-down resistor.

2. VSS : Connect to the ground.

3. RESET : Set to the low level.

4. Open : Leave this pin unconnected.

A0 to A16 : Address Bus RESET : Reset
CE : Chip Enable V

DD : Power Supply

D0 to D7 : Data Bus VPP : Programming Power Supply
OE : Output Enable VSS : Ground
PGM : Program

53

CHAPTER 2 OUTLINE (µPD78054Y Subseries)

2.6 78K/0 Series Expansion

The products in the 78K/0 Series are listed below. The names in boxes are subseries names.

Mass-produced products
Products under development

The subseries whose name ends with Y support

2

C bus specifications.

the I

Control

100-pin
100-pin Added timers to µPD78054 and enhanced external interface
100-pin
100-pin
80-pin Enhanced serial I/O of µPD78054, reduced EMI noise version
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
42-/44-pin

µPD78075B

µPD78078 µPD78078Y

µPD78070A µPD78070AY

µ

PD780018AY

µPD780058
µPD78058F

µPD78054
µPD780034
µPD780024
µPD78014H
µPD78018F

µPD78014
µPD780001

µPD78002

µPD78083

µPD780058Y

µPD78058FY

µPD78054Y
µPD780034Y
µPD780024Y

µPD78018FY

µPD78014Y

µPD78002Y

Reduced EMI noise version of µPD78078

ROM-less version of µPD78078
Enhanced serial I/O of µPD78078Y and functions are defined.

Note

Reduced EMI noise version of µPD78054
Added UART and D/A to µPD78014 and enhanced I/Os
Enhanced A/D of µPD780024
Enhanced serial I/O of µPD78018F
Reduced EMI noise version of µPD78018F
Low-voltage (1.8 V) version of µPD78014 and enhanced ROM/RAM size options
Added A/D and 16-bit timer to µPD78002
Added A/D to µPD78002
Basic subseries for control applications
Equipped with UART and operates at low-voltage (1.8 V)

78K/0

Series

64-pin
64-pin

100-pin
100-pin
80-pin

100-pin
100-pin
100-pin

80-pin

Inverter control

µPD78098864-pin
µPD780964
µPD780924

FIP driving

µPD780208
µPD780228
µPD78044H
µPD78044F80-pin Basic subseries for driving FIPs, 34 display outputs

LCD driving

µPD780308
µPD78064B

µPD78064

IEBus supported

µPD78098B

µPD7809880-pin Added IEBus controller to µPD78054

Meter control

µPD78097380-pin

µPD780308Y

µPD78064Y

Enhanced inverter control, timer, and SIO of µPD780964, expanded ROM and RAM
Enhanced A/D of µPD780924
Equipped with inverter control circuit and UART, reduced EMI noise version

Enhanced I/O and FIP C/D of µPD78044F, 53 display outputs
Enhanced I/O and FIP C/D of µPD78044H, 48 display outputs
Added N-ch open-drain I/O to µPD78044F, 34 display outputs

Enhanced SIO of µPD78064, expanded ROM and RAM
Reduced EMI noise version of µPD78064
Basic subseries for driving LCDs, equipped with UART

Reduced EMI noise version of µPD78098

Equipped with controller/driver for driving automobile meters

Note Planned

54

CHAPTER 2 OUTLINE (µPD78054Y Subseries)

Major differences among Y subseries are tabulated below.

Function ROM

Subseries Capacity MIN.
Control

LCD
drive 3-wire/time division UART : 1 ch

µ

PD78078Y 48K to 60K 3-wire/2-wire/I2C : 1 ch 88 1.8 V

µ

PD78070AY —

µ

PD780018AY

µ

PD780058Y 24K to 60K 3-wire/2-wire/I2C : 1 ch 68 1.8 V

µ

PD78058FY 48K to 60K 3-wire/2-wire/I2C : 1 ch 69 2.7 V

µ

PD78054Y 16K to 60K

µ

PD780034Y 8K to 32K UART : 1 ch 51 1.8 V

µ

PD780024Y

µ

PD78018FY 8K to 60K 3-wire/2-wire/I2C : 1 ch 53

µ

PD78014Y 8K to 32K 3-wire/2-wire/I2C : 1 ch 2.7 V

µ

PD78002Y 8K to 16K 3-wire/2-wire/SBI/I2C : 1 ch

µ

PD780308Y 48K to 60K 3-wire/2-wire/I2C : 1 ch 57 2.0 V

µ

PD78064Y 16K to 32K 3-wire/2-wire/I2C : 1 ch

48K to 60K 3-wire with automatic transmit/receive function : 1 ch 88

3-wire with automatic transmit/receive function : 1 ch
3-wire/UART : 1 ch

Time division 3-wire : 1 ch
I2C bus (supports multi-master) : 1 ch

3-wire with automatic transmit/receive function : 1 ch
3-wire/time division UART : 1 ch

3-wire with automatic transmit/receive function : 1 ch
3-wire/UART : 1 ch

3-wire : 1 ch
I2C bus (supports multi-master) : 1 ch

3-wire with automatic transmit/receive function : 1 ch

3-wire with automatic transmit/receive function : 1 ch

3-wire : 1 ch

3-wire/UART : 1 ch

Configuration of Serial Interface

I

/O

61

VDD

2.7 V

2.0 V

Remark The functions except serial interface are common with subseries without Y.

55

2.7 Block Diagram

CHAPTER 2 OUTLINE (µPD78054Y Subseries)

TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

16-bit TIMER/
EVENT COUNTER

8-bit TIMER/
EVENT COUNTER 1

8-bit TIMER/
EVENT COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL
INTERFACE 0

SERIAL
INTERFACE 1

78K/0
CPU CORE

ROM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

P00
P01-P06
P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P72

SI2/RxD/P70
SO2/TxD/P71
SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

SS

AV

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

SERIAL
INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT
CONTROL

BUZZER OUTPUT

CLOCK OUTPUT
CONTROL

RAM

V

DD

PORT 12

PORT 13

REAL-TIME
OUTPUT PORT

P120-P127

P130, P131

RTP0/P120­RTP7/P127

AD0/P40­AD7/P47

A8/P50-

EXTERNAL
ACCESS

A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67

RESET

SYSTEM
CONTROL

V

SS

IC

(V

PP

)

X1
X2
XT1/P07
XT2

56

Remarks 1. The internal ROM and RAM capacities depend on the product.

2. Pin connection in parentheses is intended for the µPD78P058.

2.8 Outline of Function

CHAPTER 2 OUTLINE (µPD78054Y Subseries)

Part Number

Item

Internal
memory

Memory space 64 Kbytes
General register 8 bits × 8 × 4 banks

Minimum
instruction
execution t ime

Instruction set • 16-bit operation

I/O port • Total : 69

A/D converter 8-bit resolution × 8 channels

ROM

High-speed RAM

Buffer RAM 32 bytes
Expansion RAM None

With main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0 MHz)
With subsystem clock selected 122 µs (@ 32.768 kHz)

µ

PD78052YµPD78053YµPD78054YµPD78055YµPD78056YµPD78058YµPD78P058Y

Mask ROM

16 Kbytes 24 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes

512 bytes 1024 bytes 1024 bytes

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation)

• BCD adjust, etc.

• CMOS input : 2

• CMOS I/O : 63

• N-ch open-drain I/O : 4

1024 bytes

PROM

Note 1

Note 1

1024 bytes

Note 2

D/A converter 8-bit resolution × 2 channels
Serial interface • 3-wire serial I/O/2-wire serial I/O/I2C bus mode selection possible : 1 channel

• 3-wire serial I/O mode (Max. 32-byte on-chip auto-transmit/receive) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

Timer • 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer : 1 channel

• Watchdog timer : 1 channel
Timer output Three outputs: (14-bit PWM output enable: 1)
Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,

2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock)

32.768 kHz (@ 32.768 kHz with subsystem clock)
Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock)

Notes 1. The capacities of the internal PROM and the internal high-speed RAM can be changed using the

memory switching register (IMS).

2. The capacity of the internal expansion RAM can be changed using the internal expansion RAM size
switching register (IXS).

57

CHAPTER 2 OUTLINE (µPD78054Y Subseries)

Part Number

Item

Maskable Internal: 13

Vectored
interrupt
source

Test input Internal: 1

Supply voltage VDD = 2.0 to 6.0 V
Operating ambient temperature TA = –40 to +85 °C
Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)

Non-maskable Internal: 1
Software 1

µ

PD78052YµPD78053YµPD78054YµPD78055YµPD78056YµPD78058YµPD78P058Y

External: 7

External: 1

• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)

• 80-pin ceramic WQFN (14 × 14 mm) (µPD78P058 only)

2.9 Mask Options

The mask ROM versions (µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y) provide pull-up resistor mask
options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places
an order for the device production. Using this mask option when pull-up resistors are required reduces the number
of components to add to the device, resulting in board space saving.

µ

The mask options provided in the

PD78054Y subseries are shown in Table 2-1.

Table 2-1. Mask Options of Mask ROM Versions

Pin names Mask options

P60 to P63 Pull-up resistor connection can be specified in 1-bit units.

58

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

3.1 Pin Function List

3.1.1 Normal operating mode pins

(1) Port pins (1/3)

Pin Name

P00 Input Input only Input INTP0/TI00
P01 Input/output mode can be specified INTP1/TI01
P02 in 1-bit units. INTP2
P03 Input/ Port 0. When used as an input port, an INTP3
P04 output 8-bit input/output port. on-chip pull-up resistor can be used INTP4
P05 by software. INTP5
P06 INTP6

P07

P10 to P17 Port 1.

P20 SI1
P21 SO1
P22 Port 2. SCK1
P23 Input/ 8-bit input/output port. STB
P24 output Input/output mode can be specified in 1-bit units. BUSY
P25 When used as an input port, an on-chip pull-up resistor can be used by SI0/SB0
P26 software. SO0/SB1
P27 SCK0

Note1

Input/Output

Input Input only Input XT1

Input/

output

8-bit input/output port.
Input/output mode can be specified in 1-bit units. Input ANI0 to ANI7
When used as input port, an on-chip pull-up resistor can be used by
software

Note2

.

Function After Reset

Input

Input

Alternate Function

Notes 1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register

(PCC) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator).

2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, set port 1 to input
mode. The on-chip pull-up resistor will automatically be disabled.

59

(1) Port pins (2/3)

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

Pin Name

P30 TO0
P31 TO1
P32 Port 3. TO2
P33 Input/ 8-bit input/output port. TI1
P34 output Input/output mode can be specified in 1-bit units. TI2
P35 When used as an input port, an on-chip pull-up resistor can be used by PCL
P36 software. BUZ
P37 —

P40 to P47 Input AD0 to AD7

P50 to P57 Input A8 to A15

P60 —
P61
P62 Port 6.
P63 Input/ 8-bit input/output port.
P64 output Input/output mode can be When used as an input port, an Input RD
P65 specified in 1-bit units. on-chip pull-up resistor can be used WR
P66 by software. WAIT
P67 ASTB

P70 SI2/RxD

P71 SO2/TxD

P72 SCK2/ASCK

Input/Output

Port 4.
8-bit input/output port.

Input/ Input/output mode can be specified in 8-bit units.

output When used as an input port, an on-chip pull-up resistor can be used by

software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Port 5.
8-bit input/output port.

Input/ LED can be driven directly.

output Input/output mode can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be used by
software.

Port 7.

Input/

output

3-bit input/output port.
Input/output mode can be specified in 1-bit units. Input
When used as an input port, an on-chip pull-up resistor can be used by
software.

Function After Reset

N-ch open-drain input/output port.
On-chip pull-up resistor can be
specified by mask option.
(Mask ROM version only).
LEDs can be driven directly.

Alternate Function

Input

60

(1) Port pins (3/3)

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

Pin Name

P120 to P127

P130 to P131

Input/Output

Input/ Port 12.

output 8-bit input/output port.

Input/output mode can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be used by
software.

Input/ Port 13.

output 2-bit input/output port.

Input/output mode can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be used by
software.

Function After Reset

Input RTP0 to RTP7

Input

Alternate Function

ANO0 to ANO1

61

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

(2) Pins other than port pins (1/2)

Pin Name

INTP0 P00/TI00
INTP1 P01/TI01
INTP2 External interrupt request inputs with specifiable valid edges (rising P02
INTP3 Input edge, falling edge, both rising and falling edges). Input P03
INTP4 P04
INTP5 P05
INTP6 P06

SI0 P25/SB0
SI1 Input Serial interface serial data input Input P20

SI2 P70/RxD
SO0 P26/SB1
SO1 Output Serial interface serial data output Input P21
SO2 P71/TxD
SB0 Input/ P25/SI0
SB1 output P26/SO0

SCK0 P27
SCK1 Serial interface serial clock input/output Input P22
SCK2 P72/ASCK

STB Output Serial interface automatic transmit/receive strobe output Input P23

BUSY Input Serial interface automatic transmit/receive busy input Input P24

RxD Input Asynchronous serial interface serial data input Input P70/SI2

TxD Output Asynchronous serial interface serial data output Input P71/SO2

ASCK Input Asynchronous serial interface serial clock input Input P72/SCK2

TI00 External count clock input to 16-bit timer (TM0) P00/INTP0
TI01 Capture trigger signal input to capture register (CR00) P01/INTP1

TI1 External count clock input to 8-bit timer (TM1) P33

TI2 External count clock input to 8-bit timer (TM2) P34
TO0 16-bit timer (TM0) output (also used for 14-bit PWM output) P30
TO1 Output P31
TO2 P32
PCL Output Clock output (for main system clock and subsystem clock trimming) Input P35
BUZ Output Buzzer output Input P36

RTP0 to RTP7

Input/Output

Serial interface serial data input/output Input

Input/

output

Input Input

8-bit timer (TM1) output
8-bit timer (TM2) output

Output Real-time output port outputting data in synchronization with trigger Input P120 to P127

Function After Reset

Input

Alternate Function

62

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

(2) Pins other than port pins (2/2)

Pin Name

AD0 to AD7

A8 to A15 Output High-order address bus when expanding external memory Input P50 to P57

RD Strobe signal output for read operation from external memory P64

WR Strobe signal output for write operation to external memory P65

WAIT Input Wait insertion when accessing external memory Input P66

ASTB Output Input P67

ANI0 to ANI7
ANO0, ANO1

AVREF0 Input A/D converter reference voltage input — —
AVREF1 Input D/A converter reference voltage input — —

AVDD — A/D converter analog power supply. Connect to VDD.——
AVSS — A/D and D/A converter ground potential. Connect to VSS.——

RESET Input System reset input — —

X1 Input ——

X2 — ——
XT1 Input Input P07
XT2 — ——

VDD — Positive power supply — —

VPP — ——

VSS — Ground potential — —

Input/Output
Input/Output

Output Input

Input A/D converter analog input Input P10 to P17

Output D/A converter analog output Input P130, P131

IC — Internally connected. Directly connect to the VSS pin. — —

Low-order address/data bus when expanding external memory Input P40 to P47

Strobe output externally latching address information output to ports 4,
5 to access external memory

Crystal connection for main system clock oscillation

Crystal connection for subsystem clock oscillation

High-voltage application for program write/verify. Directly connect to
VSS in normal operating mode.

Function After Reset

Alternate Function

3.1.2 PROM programming mode pins (PROM versions only)

Pin Name

RESET Input When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,

VPP Input High-voltage application for PROM programming mode setting and program write/verify.

A0 to A16 Input Address bus

D0 to D7

CE Input PROM enable input/program pulse input
OE Input Read strobe input to PROM

PGM Input Program/program inhibit input in PROM programming mode

VDD — Positive power supply

VSS — Ground potential

Input/Output

Input/output

Function

PROM programming mode setting.

the PROM programming mode is set.

Data bus

63

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

3.2 Description of Pin Functions

3.2.1 P00 to P07 (Port 0)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt
request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for
subsystem oscillation.

The following operating modes can be specified in 1-bit units.

(1) Port mode

P00 and P07 function as input-only ports and P01 to P06 function as input/output ports.
P01 to P06 can be specified for input or output ports in 1-bit units with a port mode register 0 (PM0). When
they are used as input ports, on-chip pull-up resistors can be used to them by defining the pull-up resistor
option register L (PUOL).

(2) Control mode

In this mode, these ports function as an external interrupt request input, an external count clock input to the
timer, and crystal connection for subsystem clock oscillation.

(a) INTP0 to INTP6

INTP0 to INTP6 are external interrupt request input pins which can specify valid edges (rising edge, falling
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture
trigger signal input pin with a valid edge input.

(b) TI00

Pin for external count clock input to 16-bit timer/event counter

(c) TI01

Pin for capture trigger signal to capture register (CR00) of 16-bit timer/event counter

(d) XT1

Crystal connect pin for subsystem clock oscillation

64

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

3.2.2 P10 to P17 (Port 1)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog

input.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports.
They can be specified in 1-bit units as input or output ports with a port mode register 1 (PM1). If used as input
ports, on-chip pull-up resistors can be used to these ports by defining the pull-up resistor option register L
(PUOL).

(2) Control mode

These ports function as A/D converter analog input pins (ANI0 to ANI7). The on-chip pull-up resistor is
automatically disabled when the pins specified for analog input.

3.2.3 P20 to P27 (Port 2)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/

from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 2 (PM2). When they are used as input ports, on-chip pull-up resistors can be used
to them by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy
input, and strobe output functions.

(a) SI0, SI1, SO0, SO1

Serial interface serial data input/output pins

(b) SCK0 and SCK1

Serial interface serial clock input/output pins

(c) SB0 and SB1

NEC standard serial bus interface input/output pins

65

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

(d) BUSY

Serial interface automatic transmit/receive busy input pins

(e) STB

Serial interface automatic transmit/receive strobe output pins

Caution When this port is used as a serial interface, the I/O and output latches must be set

according to the function the user requires. For the setting, refer to Figure 16-4 “Serial
Operation Mode Register 0 Format” and Figure 18-3 “Serial Operation Mode Register
1 Format.”

3.2.4 P30 to P37 (Port 3)

These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock
output and buzzer output.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 3 (PM3). When they are used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as timer input/output, clock output, and buzzer output.

(a) TI1 and TI2

Pin for external count clock input to the 8-bit timer/event counter.

(b) TO0 to TO2

Timer output pins.

(c) PCL

Clock output pin.

(d) BUZ

Buzzer output pin.

66

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

3.2.5 P40 to P47 (Port 4)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus.
The test input flag (KRIF) can be set to 1 by detecting a falling edge.
The following operating mode can be specified in 8-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 8-bit units for input or output ports
by using the memory expansion mode register (MM). When they are used as input ports, on-chip pull-up
resistors can be used by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as low-order address/data bus pins (AD0 to AD7) in external memory expansion mode.
When pins are used as an address/data bus, the on-chip pull-up resistor is automatically disabled.

3.2.6 P50 to P57 (Port 5)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus.
Port 5 can drive LEDs directly.
The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input/output ports with
port mode register 5 (PM5). When they are used as input ports, on-chip pull-up resistors can be used by
defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as high-order address bus pins (A8 to A15) in external memory expansion mode. When
pins are used as an address bus, the on-chip pull-up resistor is automatically disabled.

3.2.7 P60 to P67 (Port 6)

These are 8-bit input/output ports. Besides serving as input/output ports, they are used for control in external

memory expansion mode. P60 to P63 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 6 (PM6).
P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the mask option.
When P64 to P67 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor
option register L (PUOL).

(2) Control mode

These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.
When a pin is used as a control signal output, the on-chip pull-up resistor is automatically disabled.

Caution When external wait is not used in external memory expansion mode, P66 can be used as an

input/output port.

67

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

3.2.8 P70 to P72 (Port 7)

This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/
output and clock input/output functions.

The following operating modes can be specified in 1-bit units.

(1) Port mode

Port 7 functions as a 3-bit input/output port. 1-bit-units specification as an input port or output port is possible
by means of port mode register 7 (PM7). When used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register L (PUOL).

(2) Control mode

Port 7 functions as serial interface data input/output and clock input/output.

(a) SI2, SO2

Serial interface serial data input/output pins

(b) SCK2

Serial interface serial clock input/output pin.

(c) RxD, TxD

Asynchronous serial interface serial data input/output pins.

(d) ASCK

Asynchronous serial interface serial clock input/output pin.

Caution When this port is used as a serial interface, the I/O and output latches must be set according

to the function the user requires.
For the setting, see the operation mode setting list in Table 19-2 “Serial Interface Channel
2”.

68

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

3.2.9 P120 to P127 (Port 12)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port.
The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 12 (PM12). When they are used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register H (PUOH).

(2) Control mode

These ports function as real-time output ports (RTP0 to RTP7) outputting data in synchronization with a trigger.

3.2.10 P130 and P131 (Port 13)

These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog

output.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 2-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 13 (PM13). When they are used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register H (PUOH).

(2) Control mode

These ports allow D/A converter analog output (ANO0 and ANO1).

Caution When only either one of the D/A converter channels is used with AV

that are not used as analog outputs must be set as follows:

• Set PM13x bit of the port mode register 13 (PM13) to 1 (input mode) and connect the pin

SS.

to V

• Set PM13x bit of the port mode register 13 (PM13) to 0 (output mode) and the output latch
to 0, to output low level from the pin.

3.2.11 AV

REF0

A/D converter reference voltage input pin.
When A/D converter is not used, connect this pin to VSS.

3.2.12 AV

REF1

D/A converter reference voltage input pin.
When D/A converter is not used, connect this pin to V

REF1< VDD, the other pins

DD.

69

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

3.2.13 AVDD

Analog power supply pin of A/D converter. Always use the same voltage as that of the VDD pin even when A/D

converter is not used.

3.2.14 AVSS

This is a ground voltage pin of A/D converter and D/A converter. Always use the same voltage as that of the VSS

pin even when neither A/D nor D/A converter is used.

3.2.15 RESET

This is a low-level active system reset input pin.

3.2.16 X1 and X2

Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its

inverted signal to X2.

3.2.17 XT1 and XT2

Crystal resonator connect pins for subsystem clock oscillation.
For external clock supply, input it to XT1 and its inverted signal to XT2.

3.2.18 V

DD

Positive power supply pin

3.2.19 VSS

Ground potential pin

3.2.20 VPP (PROM versions only)

High-voltage apply pin for PROM programming mode setting and program write/verify. Directly connect to V

in the normal operating mode.

3.2.21 IC (Mask ROM version only)

µ

The IC (Internally Connected) pin is provided to set the test mode to check the

PD78054 Subseries before

shipment. Directly connect this pin to the VSS with the shortest possible wire in the normal operating mode.

When a voltage difference is produced between the IC pin and V

SS pin because the wiring between those two pins

is too long or an external noise is input to the IC pin, the user's program may not run normally.

Directly connect IC pins to VSS pins.

VSSIC

SS

70

As short as possible

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

3.3 Input/output Circuits and Recommended Connection of Unused Pins

Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.
Refer to Figure 3-1 for the configuration of the input/output circuit of each type.

Table 3-1. Pin Input/Output Circuit Types (1/2)

Pin Name Input/Output Recommended Connection of Unused Pins

P00/INTP0/TI00 2 Input Connect to VSS.
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
P07/XT1 16 Input Connect to VDD.
P10/ANI0 to P17/ANI7 11
P20/SI1 8-A
P21/SO1 5-A
P22/SCK1 8-A
P23/STB 5-A
P24/BUSY 8-A
P25/SI0/SB0
P26/SO0/SB1 10-A Individually connect to VDD or VSS via a
P27/SCK0 resistor.
P30/TO0
P31/TO1 5-A
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ 5-A
P37
P40/AD0 to P47/AD7 5-E Input/Output Individually connect to VDD via a resistor.

P50/A8 to P57/A15 5-A Input/output

Input/Output
Circuit Type

8-A Input/Output

8-A

Individually connect to VSS via a resistor.

Input/Output

Individually connect to VDD or VSS via a
resistor.

71

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

Table 3-1. Pin Input/Output Circuit Types (2/2)

Pin Name Input/Output Recommended Connection of Unused Pins

P60 to P63 (Mask ROM version) 13-B Input/output Individually connect to VDD via a resistor.
P60 to P63 (PROM version) 13-D
P64/RD Input/output
P65/WR
P66/WAIT
P67/ASTB
P70/SI2/RxD 8-A
P71/SO2/TxD 5-A
P72/SCK2/ASCK 8-A
P120/RTP0 to P127/RTP7 5-A
P130/ANO0, P131/ANO1 12-A Input/output Individually connect to VSS via a resistor.
RESET 2 Input —
XT2 16 — Leave open.
AVREF0 — Connect to VSS.
AVREF1 Connect to VDD.
AVDD
AVSS Connect to VSS.

Input/Output
Circuit Type

Individually connect to VDD or VSS via a resistor.

5-A

IC (Mask ROM version) Directly connect to VSS.
VPP (PROM version)

72

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

Figure 3-1. Pin Input/Output Circuit of List (1/2)

Type 2

IN

Type 5-A

pullup
enable

data

output
disable

Schmitt-Triggered Input with
Hysteresis Characteristics

V

VDD

P-ch

N-ch

DD

P-ch

IN/OUT

Type 8-A

pullup
enable

data

output
disable

Type 10-A

pullup
enable

data

open-drain

output disable

VDD

P-ch

N-ch

VDD

VDD

P-ch

N-ch

P-ch

V

IN/OUT

DD

P-ch

IN/OUT

input
enable

V

Type 5-E Type 11

DD

pullup

pullup
enable

P-ch

enable

VDD

data

P-ch

output

disable

IN/OUT

output
disable

N-ch

data

comparator

input
enable

P-ch

+
–

N-ch

V

REF (Threshold voltage)

VDD

P-ch

N-ch

V

DD

P-ch

IN/OUT

73

CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)

Figure 3-1. Pin Input/Output Circuit of List (2/2)

Type 12-A

pullup
enable

data

output

disable

input
enable

Type 13-B

output disable

data

analog output
voltage

RD

P-ch

N-ch

V

P-ch

N-ch

V

DD

DD

Mask
Option

N-ch

V

DD

P-ch

P-ch

IN/OUT

V

DD

IN/OUT

Type 13-D

output disable

data

Type 16

RD

medium breakdown
input buffer

feedback
cut-off

P-ch

N-ch

V

DD

P-ch

IN/OUT

medium breakdown
input buffer

XT2XT1

74

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

4.1 Pin Function List

4.1.1 Normal operating mode pins

(1) Port pins (1/3)

Pin Name

P00 Input Input only Input INTP0/TI00
P01 Input/output mode can be specified INTP1/TI01
P02 in 1-bit units. INTP2
P03 Input/ Port 0. When used as an input port, an INTP3
P04 output 8-bit input/output port. on-chip pull-up resistor can be used INTP4
P05 by software. INTP5
P06 INTP6

P07

P10 to P17 Port 1.

P20 SI1
P21 SO1
P22 Port 2. SCK1
P23 Input/ 8-bit input/output port. STB
P24 output Input/output mode can be specified in1-bit units. BUSY
P25 When used as an input port, an on-chip pull-up resistor can be used by SI0/SB0/SDA0
P26 software. SO0/SB1/SDA1
P27 SCK0/SCL

Note1

Input/Output

Input Input only Input XT1

Input/

output

8-bit input/output port.
Input/output mode can be specified in 1-bit units. Input ANI0 to ANI7
When used as input port, an on-chip pull-up resistor can be used by
software

Note2

.

Function After Reset

Input

Input

Alternate Function

Notes 1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register

(PCC) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator).

2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, set port 1 to input
mode. The on-chip pull-up resistor will automatically be disabled.

75

(1) Port pins (2/3)

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

Pin Name

P30 TO0
P31 TO1
P32 Port 3. TO2
P33 Input/ 8-bit input/output port. TI1
P34 output Input/output mode can be specified in 1-bit units. TI2
P35 When used as an input port, an on-chip pull-up resistor can be used by PCL
P36 software. BUZ
P37 —

P40 to P47 Input AD0 to AD7

P50 to P57 Input A8 to A15

P60 —
P61
P62 Port 6.
P63 Input/ 8-bit input/output port.
P64 output Input/output mode can be When used as an input port, an Input RD
P65 specified in 1-bit units. on-chip pull-up resistor can be used WR
P66 by software. WAIT
P67 ASTB

P70 SI2/RxD

P71 Input SO2/TxD

P72 SCK2/ASCK

Input/Output

Port 4.
8-bit input/output port.

Input/ Input/output mode can be specified in 8-bit units.

output When used as an input port, an on-chip pull-up resistor can be used by

software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Port 5.
8-bit input/output port.

Input/ LED can be driven directly.

output Input/output mode can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be used by
software.

Port 7.

Input/

output

3-bit input/output port.
Input/output mode can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be used by
software.

Function After Reset

N-ch open drain input/output port.
On-chip pull-up resistor can be
specified by mask option.
(Mask ROM version only).
LEDs can be driven directly.

Alternate Function

Input

76

(1) Port pins (3/3)

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

Pin Name

P120 to P127

P130 to P131

Input/Output

Input/ Port 12.

output 8-bit input/output port.

Input/output mode can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be used by
software.

Input/ Port 13.

output 2-bit input/output port.

Input/output mode can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be used by
software.

Function After Reset

Input RTP0 to RTP7

Input

Alternate Function

ANO0 to ANO1

77

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

(2) Pins other than port pins (1/2)

Pin Name

INTP0 P00/TI00
INTP1 P01/TI01
INTP2 External interrupt request inputs with specifiable valid edges (rising P02
INTP3 Input edge, falling edge, both rising and falling edges). Input P03
INTP4 P04
INTP5 P05
INTP6 P06

SI0 P25/SB0/SDA0
SI1 Input Serial interface serial data input Input P20

SI2 P70/RxD
SO0 P26/SB1/SDA1
SO1 Output Serial interface serial data output Input P21
SO2 P71/TxD
SB0 Input/ P25/SI0/SDA0
SB1 output P26/SO0/SDA1

SDA0 P25/SI0/SB0
SDA1 P26/SO0/SB1
SCK0 P27/SCL
SCK1 Serial interface serial clock input/output Input P22
SCK2 P72/ASCK

SCL P27/SCK0
STB Output Serial interface automatic transmit/receive strobe output Input P23

BUSY Input Serial interface automatic transmit/receive busy input Input P24

RxD Input Asynchronous serial interface serial data input Input P70/SI2

TxD Output Asynchronous serial interface serial data output Input P71/SO2

ASCK Input Asynchronous serial interface serial clock input Input P72/SCK2

TI00 External count clock input to 16-bit timer (TM0) P00/INTP0
TI01 Capture trigger signal input to capture register (CR00) P01/INTP1

TI1 External count clock input to 8-bit timer (TM1) P33

TI2 External count clock input to 8-bit timer (TM2) P34
TO0 Output 16-bit timer (TM0) output (also used for 14-bit PWM output) Input P30
TO1 P31
TO2 P32
PCL Output Clock output (for main system clock and subsystem clock trimming) Input P35
BUZ Output Buzzer output Input P36

RTP0 to RTP7

Input/Output

Serial interface serial data input/output Input

Input/

output

Input Input

8-bit timer (TM1) output
8-bit timer (TM2) output

Output Real-time output port outputting data in synchronization with trigger Input P120 to P127

Function After Reset

Alternate Function

78

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

(2) Pins other than port pins (2/2)

Pin Name

AD0 to AD7

A8 to A15 Output High-order address bus when expanding external memory Input P50 to P57

RD Strobe signal output for read operation from external memory P64

WR Strobe signal output for write operation to external memory P65

WAIT Input Wait insertion when accessing external memory Input P66

ASTB Output Input P67

ANI0 to ANI7
ANO0, ANO1

AVREF0 Input A/D converter reference voltage input — —
AVREF1 Input D/A converter reference voltage input — —

AVDD — A/D converter analog power supply. Connect to VDD.——
AVSS — A/D and D/A converter ground potential. Connect to VSS.——

RESET Input System reset input — —

X1 Input ——

X2 — ——
XT1 Input Input P07
XT2 — ——

VDD — Positive power supply — —

VPP — ——

VSS — Ground potential — —

Input/Output
Input/Output

Output Input

Input A/D converter analog input Input P10 to P17

Output D/A converter analog output Input P130, P131

IC — Internally connected. Connect directly to VSS.——

Low-order address/data bus when expanding external memory Input P40 to P47

Strobe output externally latching address information output to ports 4,
5 to access external memory

Crystal connection for main system clock oscillation

Crystal connection for subsystem clock oscillation

High-voltage application for program write/verify. Directly connect to
VSS in normal operating mode.

Function After Reset

Alternate Function

4.1.2 PROM programming mode pins (PROM versions only)

Pin Name

RESET Input When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,

VPP Input High-voltage application for PROM programming mode setting and program write/verify.

A0 to A16 Input Address bus

D0 to D7

CE Input PROM enable input/program pulse input
OE Input Read strobe input to PROM

PGM Input Program/program inhibit input in PROM programming mode

VDD — Positive power supply

VSS — Ground potential

Input/Output

Input/output

Function

PROM programming mode setting.

the PROM programming mode is set.

Data bus

79

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

4.2 Description of Pin Functions

4.2.1 P00 to P07 (Port 0)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt
request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for
subsystem oscillation.

The following operating modes can be specified in 1-bit units.

(1) Port mode

P00 and P07 function as input-only ports and P01 to P06 function as input/output ports.
P01 to P06 can be specified for input or output ports in 1-bit units with a port mode register 0 (PM0). When
they are used as input ports, on-chip pull-up resistors can be used to them by defining the pull-up resistor
option register L (PUOL).

(2) Control mode

In this mode, these ports function as an external interrupt request input, an external count clock input to the
timer, and crystal connection for subsystem clock oscillation.

(a) INTP0 to INTP6

INTP0 to INTP6 are external interrupt request input pins which can specify valid edges (rising edge, falling
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture
trigger signal input pin with a valid edge input.

(b) TI00

Pin for external count clock input to 16-bit timer/event counter

(c) TI01

Pin for capture trigger signal to capture register (CR00) of 16-bit timer/event counter

(d) XT1

Crystal connect pin for subsystem clock oscillation

80

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

4.2.2 P10 to P17 (Port 1)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog

input.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports.
They can be specified in 1-bit units as input or output ports with a port mode register 1 (PM1). If used as input
ports, on-chip pull-up resistors can be used to these ports by defining the pull-up resistor option register L
(PUOL).

(2) Control mode

These ports function as A/D converter analog input pins (ANI0 to ANI7). The on-chip pull-up resistor is
automatically disabled when the pins specified for analog input.

4.2.3 P20 to P27 (Port 2)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/

from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 2 (PM2). When they are used as input ports, on-chip pull-up resistors can be used
to them by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy
input, and strobe output functions.

(a) SI0, SI1, SO0, SO1, SB0, SB1, SDA0, SDA1

Serial interface serial data input/output pins

(b) SCK0, SCK1, SCL

Serial interface serial clock input/output pins

(c) BUSY

Serial interface automatic transmit/receive busy input pins

(d) STB

Serial interface automatic transmit/receive strobe output pins

Caution When this port is used as a serial interface, the I/O and output latches must be set

according to the function the user requires. For the setting, refer to Figure 17-4 “Serial
Operation Mode Register 0 Format” and Figure 18-3 “Serial Operation Mode Register
1 Format.”

81

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

4.2.4 P30 to P37 (Port 3)

These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock
output, and buzzer output.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 3 (PM3). When they are used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as timer input/output, clock output, and buzzer output.

(a) TI1 and TI2

Pin for external count clock input to the 8-bit timer/event counter.

(b) TO0 to TO2

Timer output pins.

(c) PCL

Clock output pin.

(d) BUZ

Buzzer output pin.

4.2.5 P40 to P47 (Port 4)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus.

The test input flag (KRIF) can be set to 1 by detecting a falling edge.

The following operating mode can be specified in 8-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 8-bit units for input or output ports
by using the memory expansion mode register (MM). When they are used as input ports, on-chip pull-up
resistors can be used by defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as low-order address/data bus pins (AD0 to AD7) in external memory expansion mode.
When pins are used as an address/data bus, the on-chip pull-up resistor is automatically disabled.

82

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

4.2.6 P50 to P57 (Port 5)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus.
Port 5 can drive LEDs directly.
The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input/output ports with
port mode register 5 (PM5). When they are used as input ports, on-chip pull-up resistors can be used by
defining the pull-up resistor option register L (PUOL).

(2) Control mode

These ports function as high-order address bus pins (A8 to A15) in external memory expansion mode. When
pins are used as an address bus, the on-chip pull-up resistor is automatically disabled.

4.2.7 P60 to P67 (Port 6)

These are 8-bit input/output ports. Besides serving as input/output ports, they are used for control in external

memory expansion mode. P60 to P63 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 6 (PM6).
P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the mask option.
When P64 to P67 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor
option register L (PUOL).

(2) Control mode

These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.
When a pin is used as a control signal output, the on-chip pull-up resistor is automatically disabled.

Caution When external wait is not used in external memory expansion mode, P66 can be used as an

input/output port.

83

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

4.2.8 P70 to P72 (Port 7)

This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/
output and clock input/output functions.

The following operating modes can be specified in 1-bit units.

(1) Port mode

Port 7 functions as a 3-bit input/output port. 1-bit-units specification as an input port or output port is possible
by means of port mode register 7 (PM7). When used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register L (PUOL).

(2) Control mode

Port 7 functions as serial interface data input/output and clock input/output.

(a) SI2, SO2

Serial interface serial data input/output pins

(b) SCK2

Serial interface serial clock input/output pin.

(c) RxD, TxD

Asynchronous serial interface serial data input/output pins.

(d) ASCK

Asynchronous serial interface serial clock input/output pin.

Caution When this port is used as a serial interface, the I/O and output latches must be set according

to the function the user requires.
For the setting, see to the operation mode setting list in Table 19-2 “Serial Interface Channel
2”.

4.2.9 P120 to P127 (Port 12)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 12 (PM12). When they are used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register H (PUOH).

(2) Control mode

These ports function as real-time output ports (RTP0 to RTP7) outputting data in synchronization with a trigger.

84

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

4.2.10 P130 and P131 (Port 13)

These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog

output.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 2-bit input/output ports. They can be specified in 1-bit units as input or output ports
with port mode register 13 (PM13). When they are used as input ports, on-chip pull-up resistors can be used
by defining the pull-up resistor option register H (PUOH).

(2) Control mode

These ports allow D/A converter analog output (ANO0 and ANO1).

Caution When only either one of the D/A converter channels is used with AV

REF1< VDD, the other pins

that are not used as analog outputs must be set as follows:

• Set PM13x bit of the port mode register 13 (PM13) to 1 (input mode) and connect the pin

SS.

to V

• Set PM13x bit of the port mode register 13 (PM13) to 0 (output mode) and the output latch
to 0, to output low level from the pin.

4.2.11 AV

REF0

A/D converter reference voltage input pin.
When A/D converter is not used, connect this pin to VSS.

4.2.12 AV

REF1

D/A converter reference voltage input pin.
When D/A converter is not used, connect this pin to V

DD.

4.2.13 AVDD

Analog power supply pin of A/D converter. Always use the same voltage as that of the VDD pin even when A/D

converter is not used.

4.2.14 AVSS

This is a ground voltage pin of A/D converter

and D/A converter.

Always use the same voltage as that of the VSS

pin even when neither A/D nor D/A converter is used.

4.2.15 RESET

This is a low-level active system reset input pin.

85

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

4.2.16 X1 and X2

Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its

inverted signal to X2.

4.2.17 XT1 and XT2

Crystal resonator connect pins for subsystem clock oscillation.
For external clock supply, input it to XT1 and its inverted signal to XT2.

4.2.18 V

DD

Positive power supply pin

4.2.19 V

SS

Ground potential pin

4.2.20 V

PP (PROM versions only)

High-voltage apply pin for PROM programming mode setting and program write/verify. Directly connect to VSS

in the normal operating mode.

4.2.21 IC (Mask ROM version only)

µ

The IC (Internally Connected) pin is provided to set the test mode to check the

shipment. Directly connect the pin to the V

SS with the shortest possible wire in the normal operating mode.

PD78054Y Subseries before

When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins

is too long or an external noise is input to the IC pin, the user's program may not run normally.

Directly connect IC pins to VSS pins.

VSSIC

86

As short as possible

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

4.3 Input/output Circuits and Recommended Connection of Unused Pins

Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.
Refer to Figure 4-1 for the configuration of the input/output circuit of each type.

Table 4-1. Pin Input/Output Circuit Types (1/2)

Pin Name Input/Output Recommended Connection of Unused Pins

P00/INTP0/TI00 2 Input Connect to VSS.
P01/INTP1/TI01 8-A
P02/INTP2
P03/INTP3 Individually connect to VSS via a resistor.
P04/INTP4
P05/INTP5
P06/INTP6
P07/XT1 16 Input Connect to VDD.
P10/ANI0 to P17/ANI7 11
P20/SI1 8-A
P21/SO1 5-A
P22/SCK1 8-A
P23/STB 5-A
P24/BUSY 8-A
P25/SI0/SB0/SDA0 10-A
P26/SO0/SB1/SDA1 Individually connect to VDD or VSS via a
P27/SCK0/SCL resistor.
P30/TO0 5-A
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL 5-A
P36/BUZ
P37
P40/AD0 to P47/AD7 5-E Input/Output Individually connect to VDD via a resistor.

P50/A8 to P57/A15 5-A Input/output

Input/Output
Circuit Type

Input/Output

Input/Output

8-A

Individually connect to VDD or VSS via a
resistor.

87

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

Table 4-1. Pin Input/Output Circuit Types (2/2)

Pin Name Input/Output Recommended Connection of Unused Pins

P60 to P63 (Mask ROM version) 13-B Input/output Individually connect to VDD via a resistor.
P60 to P63 (PROM version) 13-D
P64/RD Input/output
P65/WR
P66/WAIT
P67/ASTB
P70/SI2/RxD 8-A
P71/SO2/TxD 5-A
P72/SCK2/ASCK 8-A
P120/RTP0 to P127/RTP7 5-A
P130/ANO0 to P131/ANO1 12-A Input/output Individually connect to VSS via a resistor.
RESET 2 Input —
XT2 16 — Leave open.
AVREF0 — Connect to VSS.
AVREF1 Connect to VDD.
AVDD
AVSS Connect to VSS.
IC (Mask ROM version) Directly connect to VSS.
VPP (PROM version)

Input/Output
Circuit Type

5-A

Individually connect to VDD or VSS via a resistor.

88

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

IN

pullup
enable

V

DD

P-ch

IN/OUT

input
enable

output
disable

data

VDD

P-ch

N-ch

Type 2

Type 5-A

Schmitt-Triggered Input with
Hysteresis Characteristics

Type 5-E Type 11

Type 10-A

Type 8-A

pullup
enable

V

DD

P-ch

IN/OUT

output
disable

data

VDD

P-ch

N-ch

pullup
enable

VDD

P-ch

IN/OUT

output
disable

data

VDD

P-ch

N-ch

pullup
enable

V

DD

P-ch

IN/OUT

open-drain

output disable

data

VDD

P-ch

N-ch

pullup
enable

V

DD

P-ch

IN/OUT

output

disable

data

VDD

P-ch

N-ch

P-ch

comparator

N-ch

input
enable

V

REF (Threshold voltage)

+

–

Figure 4-1. Pin Input/Output Circuit of List (1/2)

89

CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)

Figure 4-1. Pin Input/Output Circuit of List (2/2)

Type 12-A

pullup
enable

data

output

disable

input
enable

Type 13-B

output disable

data

analog output
voltage

RD

P-ch

N-ch

V

P-ch

N-ch

V

DD

DD

Mask
Option

N-ch

V

DD

P-ch

P-ch

IN/OUT

V

DD

IN/OUT

Type 13-D

output disable

data

Type 16

RD

medium breakdown
input buffer

feedback
cut-off

P-ch

N-ch

V

DD

P-ch

IN/OUT

medium breakdown
input buffer

XT2XT1

90

CHAPTER 5 CPU ARCHITECTURE

0000H

Data memory
space

General Registers

32 × 8 bits

Internal ROM

16384 × 8 bits

3FFFH

1000H
0FFFH

0800H
07FFH

0080H
007FH

0040H
003FH

0000H

CALLF Entry Area

CALLT Table Area

Vector Table Area

Program Area

Program Area

Internal Buffer RAM

32 × 8 bits

External Memory

47744 × 8 bits

Reserved

Program
memory
space

4000H
3FFFH

FA80H
FA7FH

FAC0H
FABFH

FAE0H
FADFH

FEE0H
FEDFH

FF00H
FEFFH

FFFFH

Internal High-speed RAM

512 × 8 bits

Special Function
Registers (SFRs)

256 × 8 bits

Reserved

FD00H
FCFFH

5.1 Memory Spaces

Each product of the µPD78054 and 78054Y Subseries can access the memory space of 64 Kbytes. Figures 5-1

to 5-8 show memory maps.

µ

Figure 5-1. Memory Map (

PD78052, 78052Y)

91

CHAPTER 5 CPU ARCHITECTURE

Figure 5-2. Memory Map (µPD78053, 78053Y)

Data memory
space

Program
memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H
FADFH

FAC0H
FABFH

FA80H
FA7FH

6000H
5FFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

External Memory

39552 × 8 bits

5FFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

0000H

Internal ROM

24576 × 8 bits

0040H
003FH

Vector Table Area

0000H

92

CHAPTER 5 CPU ARCHITECTURE

Figure 5-3. Memory Map (µPD78054, 78054Y)

Data memory
space

Program
memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H
FADFH

FAC0H
FABFH

FA80H
FA7FH

8000H
7FFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

External Memory

31360 × 8 bits

7FFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

0000H

Internal ROM

32768 × 8 bits

0040H
003FH

Vector Table Area

0000H

93

CHAPTER 5 CPU ARCHITECTURE

Figure 5-4. Memory Map (µPD78P054)

Data memory
space

Program
memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H
FADFH

FAC0H
FABFH

FA80H
FA7FH

8000H
7FFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

External Memory

31360 × 8 bits

7FFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

0000H

Internal PROM

32768 × 8 bits

0040H
003FH

Vector Table Area

0000H

94

CHAPTER 5 CPU ARCHITECTURE

Figure 5-5. Memory Map (µPD78055, 78055Y)

Data memory
space

Program
memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H

FADFH

FAC0H
FABFH

FA80H
FA7FH

A000H
9FFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

External Memory

23168 × 8 bits

9FFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

0000H

Internal ROM

40960 × 8 bits

0040H
003FH

Vector Table Area

0000H

95

CHAPTER 5 CPU ARCHITECTURE

Figure 5-6. Memory Map (µPD78056, 78056Y)

Data memory
space

Program
memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H

FADFH

FAC0H
FABFH

FA80H
FA7FH

C000H
BFFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

External Memory

14976 × 8 bits

BFFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

0000H

Internal ROM

49152 × 8 bits

0040H
003FH

Vector Table Area

0000H

96

CHAPTER 5 CPU ARCHITECTURE

Figure 5-7. Memory Map (µPD78058, 78058Y)

Data memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H
FADFH

FAC0H
FABFH

F800H
F7FFH

F400H
F3FFH

F000H
EFFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

Internal

Expansion RAM

1024 × 8 bits

Reserved

Note

EFFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

Program
memory
space

Internal ROM

61440 × 8 bits

0000H

0040H
003FH

Vector Table Area

0000H

Note When internal ROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH

can be used as external memory by setting the internal ROM size to less than 56K bytes by the
memory size switching register (IMS).

97

CHAPTER 5 CPU ARCHITECTURE

Figure 5-8. Memory Map (µPD78P058, µPD78P058Y)

Data memory
space

FFFFH

FF00H
FEFFH

FEE0H
FEDFH

FB00H
FAFFH

FAE0H
FADFH

FAC0H
FABFH

F800H
F7FFH

F400H
F3FFH

F000H
EFFFH

Special Function
Registers (SFRs)

256 × 8 bits

General Registers

32 × 8 bits

Internal High-speed RAM

1024 × 8 bits

Reserved

Internal Buffer RAM

32 × 8 bits

Reserved

Internal

Expansion RAM

1024 × 8 bits

Reserved

Note

EFFFH

Program Area

1000H
0FFFH

CALLF Entry Area

0800H
07FFH

Program Area

0080H
007FH

CALLT Table Area

Program
memory
space

Internal PROM

61440 × 8 bits

0000H

0040H
003FH

Vector Table Area

0000H

Note When internal PROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH

can be used as external memory by setting the internal PROM size to less than 56K bytes by the
memory size switching register (IMS).

98

CHAPTER 5 CPU ARCHITECTURE

5.1.1 Internal program memory space

The internal program memory space stores programs and table data. Normally, they are addressed with a program

counter (PC).

µ

Each product of the

PD78054 and 78054Y Subseries has the internal ROM (or PROM) of the size shown below.

Table 5-1. Internal ROM Capacity

Part number

µ

PD78052, 78052Y Mask ROM 16384 x 8 bits (0000H to 3FFFH)

µ

PD78053, 78053Y 24576 x 8 bits (0000H to 5FFFH)

µ

PD78054, 78054Y 32768 x 8 bits (0000H to 7FFFH)

µ

PD78055, 78055Y 40960 x 8 bits (0000H to 9FFFH)

µ

PD78056, 78056Y 49152 x 8 bits (0000H to BFFFH)

µ

PD78058, 78058Y 61440 x 8 bits (0000H to EFFFH)

µ

PD78P054 PROM 32768 x 8 bits (0000H to 7FFFH)

µ

PD78P058, 78P058Y 61440 x 8 bits (0000H to EFFFH)

Type Capacity

Internal ROM

The following areas are allocated to the internal program memory space.

(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start
addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the
16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.

Table 5-2. Vector Table

Vector Table Address Interrupt Source Vector Table Address Interrupt Source
0000H RESET input 0018H INTSER
0004H INTWDT 001AH INTSR/INTCSI2
0006H INTP0 001CH INTST
0008H INTP1 001EH INTTM3
000AH INTP2 0020H INTTM00
000CH INTP3 0022H INTTM01
000EH INTP4 0024H INTTM1
0010H INTP5 0026H INTTM2
0012H INTP6 0028H INTAD
0014H INTCSI0 003EH BRK
0016H INTCSI1

(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

99

CHAPTER 5 CPU ARCHITECTURE

5.1.2 Internal data memory space

The µPD78054 and 78054Y subseries units incorporate the following RAMs.

(1) Internal high-speed RAM

µ

PD78054 and 78054Y Subseries are provided with the internal high-speed RAM as shown below.

The

Table 5-3. Internal High-Speed RAM Capacity

Part Number Internal High-Speed RAM

µ

PD78052, 78052Y 512 × 8 bits (FD00H to FEFFH)

µ

PD78053, 78053Y 1024 × 8 bits (FB00H to FEFFH)

µ

PD78054, 78054Y

µ

PD78P054

µ

PD78055, 78055Y

µ

PD78056, 78056Y

µ

PD78058, 78058Y

µ

PD78P058, 78P058Y

In this area, four banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the
32-byte area FEE0H to FEFFH.
The internal high-speed RAM can also be used as a stack memory.

(2) Buffer RAM

Buffer RAM is allocated to the 32-byte area from FAC0H to FADFH. The buffer RAM is used to store transmit/
receive data of serial interface channel 1 (in three-wire serial I/O mode with automatic transfer/receive
function). If the three-wire serial I/O mode with automatic transfer/receive function is not used, the buffer RAM
can also be used as normal RAM. Buffer RAM can also be used as normal RAM.

µ

(3) Internal expansion RAM (

PD78058, 78058Y, 78P058, 78P058Y only)

Internal expansion RAM is allocated to the 1024-byte area from F400H to F7FFH.

5.1.3 Special Function Register (SFR) area

An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH. (Refer

to Table 5-6. Special-Function Register List in 5.2.3 Special Function Register (SFR)).

Caution Do not access addresses where the SFR is not assigned.

5.1.4 External memory space

The external memory space is accessible by setting the memory expansion mode register (MM). External memory

space can store program, table data, etc. and allocate peripheral devices.

100